JPS5843897B2 - Method for measuring resistance of P-type silicon epitaxial layer - Google Patents

Method for measuring resistance of P-type silicon epitaxial layer

Info

Publication number
JPS5843897B2
JPS5843897B2 JP8528679A JP8528679A JPS5843897B2 JP S5843897 B2 JPS5843897 B2 JP S5843897B2 JP 8528679 A JP8528679 A JP 8528679A JP 8528679 A JP8528679 A JP 8528679A JP S5843897 B2 JPS5843897 B2 JP S5843897B2
Authority
JP
Japan
Prior art keywords
epitaxial layer
type silicon
silicon epitaxial
resistance
measuring resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8528679A
Other languages
Japanese (ja)
Other versions
JPS5610919A (en
Inventor
秀明 高橋
格 山仲
進 直本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP8528679A priority Critical patent/JPS5843897B2/en
Publication of JPS5610919A publication Critical patent/JPS5610919A/en
Publication of JPS5843897B2 publication Critical patent/JPS5843897B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Description

【発明の詳細な説明】 本発明は四探針法によりエピタキシャル層のシート抵抗
を測定する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring the sheet resistance of an epitaxial layer using a four-probe method.

四探針法は１表面が平らでかつ大きな試料、たとえば半
導体基板上に形成されたエピタキシャル層等のシート抵
抗または比抵抗の測定に広く用いられている方法であっ
て、測定すべき試料表面に一直線をなす４点をとり、探
針を立てて両端の２点に電流を流し、内側の２点間にか
かる電圧を測定することにより正確な測定値を得る方法
である。The four-point probe method is a method widely used to measure the sheet resistance or specific resistance of a large sample with a flat surface, such as an epitaxial layer formed on a semiconductor substrate. This method obtains accurate measurements by taking four points in a straight line, setting up a probe, passing current through two points at both ends, and measuring the voltage applied between the two inner points.

ところがこの四探針法を用いてシリコンエピタキシャル
層のシート抵抗を測定すると、理由は定かでないがｎ型
に比べてことにｐ型高比抵抗のものが測定結果に再現性
が乏しく、ばらつきが大きいという問題があり、多数回
の測定値の平均をとらなければならないという不都合が
あった。However, when the sheet resistance of a silicon epitaxial layer is measured using this four-probe method, for reasons that are not clear, the measurement results are poor in reproducibility and have large variations, especially for p-type materials with high resistivity compared to n-type materials. There is a problem in that it is necessary to take the average of a large number of measured values.

たとえば、第１図は、ｎ型シリコン基板上に。For example, FIG. 1 shows an example on an n-type silicon substrate.

比抵抗３０Ω温厚さ４０μｍのｐ型シリコンエピタキシ
ャル層を形成し、４探針法を用い試料に流す電流の方向
を順逆に反転させ、これを１回とし。A p-type silicon epitaxial layer with a specific resistance of 30Ω and a thickness of 40 μm was formed, and the direction of the current flowing through the sample was reversed using the four-probe method, and this was done once.

都合２０回にわたる測定を行った結果であるが。This is the result of a total of 20 measurements.

ばらつきは非常に大きいことがわかる。It can be seen that the variation is very large.

このばらつきは、同じ高比抵抗のエピタキシャル層でも
。This variation occurs even in epitaxial layers with the same high resistivity.

ｎ型のものに対しては、全くみられない。It is not observed at all for n-type.

本発明は、ｐ型高比抵抗エピタキシャル層の４探針法に
よる比抵抗測定にのみみられる上記の問題点に鑑みてな
されたもので、あらかじめ測定しようとする試料表面に
対し、弗酸によるエツチング処理等の表面処理を施した
のち測定を行うことにより、ばらつきなく精度の良い測
定値を得ることを見い出し、これに基いてなされたもの
である。The present invention has been made in view of the above-mentioned problems that occur only when measuring the resistivity of a p-type high resistivity epitaxial layer using the four-probe method. This was based on the discovery that by performing measurements after performing surface treatment, it is possible to obtain accurate measured values without variation.

次に本発明実施例の高比抵抗ｐ型シリコンエピタキシャ
ル層のシート抵抗測定方法について説明する。Next, a method for measuring the sheet resistance of a high resistivity p-type silicon epitaxial layer according to an embodiment of the present invention will be described.

ｎ型シリコン基板表面に、比抵抗３０Ωの厚さ４０μｍ
のｐ型シリコンエピタキシャル層の形成された試料を準
備し、これを４６．５条の弗酸と水をに１０の割合で混
合してなるエツチング液に１分４０秒浸漬したのち水洗
乾燥処理を行った。A 40μm thick layer with a specific resistance of 30Ω is placed on the surface of an n-type silicon substrate.
A sample with a p-type silicon epitaxial layer formed thereon was prepared, and it was immersed in an etching solution made by mixing 46.5 parts of hydrofluoric acid and 10 parts of water for 1 minute and 40 seconds, and then washed with water and dried. went.

その後、４探針法を用いて多数回にわたり。シート抵抗
を測定した。After that, multiple times using the 4-probe method. Sheet resistance was measured.

その結果を第２図に示す。この図から明らかなように、
測定値のばらつきは非常に小さくなった。The results are shown in FIG. As is clear from this figure,
The dispersion of measured values has become very small.

この理由は詳らかではないが、ことに高比抵抗ｐ型エピ
タキシャル層の場合においてのみ、大きかったシート抵
抗測定値のばらつきが、測定の前に弗酸処理を施すこと
により、非常に小さくなった。Although the reason for this is not clear, especially in the case of a high resistivity p-type epitaxial layer, the large dispersion of measured sheet resistance values became extremely small by performing hydrofluoric acid treatment before measurement.

これは弗酸処理により表面酸化膜が除去されたためとは
考えにくい。It is unlikely that this is because the surface oxide film was removed by the hydrofluoric acid treatment.

エピタキシャル成長を水累算囲気中で行い、かつリアク
タからとり出した直後、すなわち１表面に酸化膜が形成
されない状態で測定することによってもこのばらつきは
消滅しないことから、とくに表面の酸化膜の影響ではな
いように思われる。This variation does not disappear even if epitaxial growth is performed in a water accumulation atmosphere and measurements are taken immediately after removal from the reactor, that is, when no oxide film is formed on one surface. It seems not.

しかしながら、この表面処理により表面状態に何らかの
変化が生じ、四探針法に適したものとなっていると考え
られる。However, it is thought that this surface treatment causes some change in the surface condition, making it suitable for the four-probe method.

さらに、弗酸と水の混合比を１：１〜１００゜処理時間
を３秒〜１５分で、いろいろな組合せを選び実験を行っ
た。Furthermore, experiments were conducted by selecting various combinations of hydrofluoric acid and water at a mixing ratio of 1:1 to 100° and a treatment time of 3 seconds to 15 minutes.

この実験結果によれば、弗酸：水の混合比が１：１〜Ｉ
：Ｉｏｏ、処理時間が３０秒〜１０分の範囲において顕
著な効果がみられた。According to this experimental result, the mixing ratio of hydrofluoric acid:water is 1:1 to I
:Ioo, remarkable effects were observed when the treatment time was in the range of 30 seconds to 10 minutes.

弗酸：水−１＝１以上の濃い溶液を用いると１表面がス
テイニングされることがあり、又１００以下に希釈した
場合エツチング液の組成がばらつき、溶液濃度の再現性
に乏しく実用的には問題があった。If a concentrated solution of hydrofluoric acid: water - 1 = 1 or more is used, one surface may be stained, and if it is diluted to less than 100, the composition of the etching solution will vary and the reproducibility of the solution concentration will be poor, making it impractical. There was a problem.

また０時間については、３０秒以下では測定値のばらつ
きは解消されないばかりでなく、かえって、測定値のば
らつきを大きくする結果となることもある。Further, regarding time 0, if the time is 30 seconds or less, the variation in measured values is not only not eliminated, but may even increase the variation in measured values.

これは、エツチング処理が不充分であることの他に、エ
ツチングの「むら」なども関係していると考えられる。This is thought to be related not only to insufficient etching treatment but also to "unevenness" in etching.

一方、１０分以上行ってもさらに顕著な効果は認められ
ず１時間のロスが太きい。On the other hand, even if the treatment is carried out for more than 10 minutes, no more significant effect is observed and one hour is lost.

上述した範囲内に、エツチング時間および溶液濃度を選
んだ場合、その範囲内では、その効果に著しい差異は認
められず、いずれも、処理前のばらつきが１０％以上で
あったものが、処理後には１．５％以内となっている。When the etching time and solution concentration are selected within the above range, there is no significant difference in the effectiveness within that range, and in both cases, the variation before treatment was 10% or more, but after treatment is within 1.5%.

以上説明してきたように、測定値にばらつきが大きく多
数回の測定によらなければ、信頼性を得ることができな
かったとくに１００以上の高抵抗ｐ型エピタキシャル層
の測定値が１本発明の方法によれば測定値のばらつきが
小さくなり＋、−１回程度の測定値の平均を求めれば元
号であり、抵抗測定の為の作業能率を非常に大きく高め
ることができるものである。As explained above, the measured values have large variations and reliability cannot be obtained unless measurements are performed many times.In particular, the method of the present invention has a high resistance p-type epitaxial layer of 100 or more. According to this method, the dispersion of measured values is reduced, and if the average of the measured values of + and -1 times is calculated, it is possible to obtain the era name, and the work efficiency for resistance measurement can be greatly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来法によって測定したｐ型窩抵抗エビクキシ
ャル層のシート抵抗を示す図、第２図は本発明実施例の
方法を用いて測□したｐ型高抵抗エピタキシャル層のシ
ート抵抗を示す図である。FIG. 1 is a diagram showing the sheet resistance of a p-type epitaxial layer with high resistance measured using the conventional method, and FIG. 2 is a diagram showing the sheet resistance of a p-type high-resistance epitaxial layer measured using the method of the embodiment of the present invention. It is.

Claims (1)

【特許請求の範囲】[Claims] １ 四探針法を用いて、ｐ型のシリコンエピタキシャル
層のシート抵抗又は比抵抗を測定するにあたり、あらか
じめ前記シリコンエピタキシャル層に対し弗酸による表
面処理を施したのちに測定を行うことを特徴とするｐ型
シリコンエピタキシャル層の抵抗測定方法。1. When measuring the sheet resistance or specific resistance of a p-type silicon epitaxial layer using the four-probe method, the silicon epitaxial layer is first subjected to surface treatment with hydrofluoric acid, and then the measurement is performed. A method for measuring the resistance of a p-type silicon epitaxial layer.
JP8528679A 1979-07-05 1979-07-05 Method for measuring resistance of P-type silicon epitaxial layer Expired JPS5843897B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8528679A JPS5843897B2 (en) 1979-07-05 1979-07-05 Method for measuring resistance of P-type silicon epitaxial layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8528679A JPS5843897B2 (en) 1979-07-05 1979-07-05 Method for measuring resistance of P-type silicon epitaxial layer

Publications (2)

Publication Number Publication Date
JPS5610919A JPS5610919A (en) 1981-02-03
JPS5843897B2 true JPS5843897B2 (en) 1983-09-29

Family

ID=13854320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8528679A Expired JPS5843897B2 (en) 1979-07-05 1979-07-05 Method for measuring resistance of P-type silicon epitaxial layer

Country Status (1)

Country Link
JP (1) JPS5843897B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953263B2 (en) * 1993-07-16 1999-09-27 信越半導体株式会社 Method for measuring resistivity of n-type silicon epitaxial layer

Also Published As

Publication number Publication date
JPS5610919A (en) 1981-02-03

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