JPS5843054A - Multicontrol system of microcontroller - Google Patents

Abstract

PURPOSE:To ensure a high-speed transmission of data among plural microcontrollers, by deciding the transmission or the reception through the microcontroller and with an address signal and transmitting the data simultaneously to plural microcontrollers. CONSTITUTION:A microcontroller decides the transmission or the reception with an address signal, and the data are transmitted simultaneously to plural microcontrollers. The address signals are outputted consecutively from a multibus orbiter MBA10 for example and inputted to the multibus interfaces MBI111- 11n+1 and a system memories SM12 via a multibus. The output signals obtained on the basis of the address signals are transmitted to the microcontrollers MC131-13n from the interfaces MBI111-11n via the local buses. At the same time, the input/output signals to the MBI11n+1 are controlled by the process input/output controllers 14A and 14B via the local bus. Then each MC decides the transmission or the reception based on the address signal delivered from the MBA10 and by the MBI111-11n.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-control system for a microcontroller, and in particular, to a multi-control system for a microcontroller, and particularly to the requirements for multi-systems, failure diagnosis, and pump-up switching according to process scale.

This paper relates to a multi-control method for a microcontroller suitable for a certain system.

FIG. 1 is a circuit diagram of a conventional microcontroller multi-control device using a microprocessor.

In FIG. 1, 1a, 1b and IC are microcontrollers, 2a and 2b are receivers 3a for performing data transmission between the microcontrollers.

3b is a transmitter, and 4'a and 4b are process input/output devices. When transmitting data from the microcontroller 1a to the microcontrollers 1b and 1c, the transmitter 3
A, 3b remigrated product controller 1b.

, 1c is transmitted to the receivers 2a, 2b via the individual routers.The voice is transmitted to the controlled target program from each of the process input/output devices 4a, 4b, and 4c. (In Fig. 1, the receiver is omitted in 1a, and the transmitter is omitted in 1b and 1c.) In such a configuration, as is clear from the figure, data should be transmitted. Number of microcontrollers If a controller goes down, there are drawbacks such as the need for a one-to-one spare because it cannot be backed up with just one spare.In other words, the number of microcontrollers for backing up each microcontroller, Although we do not have control data for other machines, and the programs are different for each microcontroller and controller, it is difficult to transfer the programs to a backup controller, so we will back them up using one spare controller. In addition, since switching is not performed smoothly, it is difficult to transmit data at high speed, and
It is not possible to improve processing capacity.
- An object of the present invention is to provide a multi-control system for microcontrollers that can perform data transmission between a plurality of microcontrollers at high speed.

In other words, the present invention allocates an address to each piece of commonly required data in multiple microcontrollers, determines whether the microcontrollers should transmit or receive data based on the address signal, and simultaneously transmits data to multiple microcontrollers. This is what I decided to do.

Specifically, Bus Orbi, which controls one multipath,
(1) Broadcast data via multipath (However, if the data is not broadcast) The microcontroller can be any one (6) (2) Receives data (it is also possible to receive all data except for the controller that sends it) (3) Determines the 03 mode in which neither broadcast nor receive, (4) Broadcasting is also possible. It determines whether the data has been received or not, and transmits the data in one step to any controller or to all controllers that require the data.

In other words, the -7 address signal not only specifies data but also
■The first feature is that you can also specify the controller to broadcast and the controller to receive θ, and the data sent from each controller is sent with first priority in the event of an abnormality such as one controller going down. Divided into four blocks: ultra-high-speed data, high-speed data that requires processing faster than normal process requirements, medium-speed data that can be processed at medium speed, and low-speed data that can be processed at low speed. hand,
The second feature is the ability to perform emergency processing in the event of an abnormality and high-speed processing according to the process.When any one controller goes down, programs and data can be stored in a spare microcontroller as an ultra-high-speed data group and backed up. The third feature of this configuration is that

FIG. 2 shows an embodiment of the present invention. In Figure 2, 10 is the multipath orbiter that controls the multipath, 111 to 1.1 is the multibus interface that interfaces the local bus of each multiburst controller, and 12 is the multibus interface that controls the local bus of each controller. System memory, 131-13. is micro control, 14A,
14B is a process input/output controller that takes in data from the 7' process scalar and outputs data to the process.

→Multibus (MB) K is Multipath Orbiter (MBA)
101 Multi-path interface microcontroller, roller (MO') 13-1 to 13, If a failure occurs in the microcontroller consisting of 1, 1 transfers the program of the microcontroller to a spare device (MC for backup) 5 It is a diagram showing mapping of data. As shown in the figure, 1 system memory (SM) contains data groups for ultra-high-speed processing, high-speed, medium-speed, and low-speed processing. The data that requires processing is BDO.

They are mapped as BDl, BD2, etc.

In addition, the data group for ultra-high-speed processing includes program program P-A for controller 13° and program P-B for controller 13〒.

...and it's pine pink. On the other hand, on the local side, each controller has data groups for high-speed, medium-speed, and low-speed processing,
And program data unique to each controller is mapped, and data groups for high-speed, medium-speed, and low-speed processing are data groups for each controller to transmit data to others, as shown in the enlarged view of the figure. For example, BDO.

BDI, BD2. It is mapped as BDO... 5 Under normal conditions without any failures, if the multipath address becomes ABO, as shown in the figure, the data BDO linked to address ABO will be transferred to the controller all at once, as shown in - (■). Transmission is possible.

A group of addresses linked to one PC is generated in multipath, and the controller (1) is a standby device as shown by the dotted line.
3. The program data P-C of the controller 133 is input to the controller 13. is the controller 1330
As is known from the above explanation, the characteristic features of the main gate embodiment will be explained with reference to figures.

FIG. 4 shows a detailed diagram of the multipath orbiter 10, and FIG. 5 shows its circuit diagram. Fourth
In the figure, the multipath orbiter 10 is .

It consists of address generators 101, 102, 103, 104, a mode specifying address generator 105, a stroop generator 106, and a switch 107.

The address generator 101 inputs data from the multi-error data bus, determines which microcontroller has failed (replaces the failed microcontroller, and continues operation with a standby unit connected to the multipath). Address group for inputting the program data in the microcontroller to the standby device (in order to input the program data in the microcontroller to the standby device) When the address A't occurs consecutively, the address generator stop signal and the mode designation address generator are sent to the emergency generator. It has the function of generating a processing mode command signal, which is a ready signal from the standby machine. -Updates the address generated by the ready signal, and generates error reset No. 4 when data is input manually to the standby machine. It also has the function of canceling the emergency processing mode, and also has an address that generates the reception/transmission mode data necessary for the backup device to transfer data with other controllers in place of the failed microcontroller. It has the function of linking and generating. The address generator 102 has a function of rapidly generating an address group address B linked to data for which evening transmission is required (data must be transmitted in short cycles) in each controller. Address generator 1 in emergency processing mode
01 is stopped, the address generator of the low-speed processing monitor is activated by the signal that the address generation is stopped or the 11th cycle is completed, and like the address generator 101, the address generated by the ready signal is designated as one address. Vessel 1
05 and the medium speed processing address generator 1"0.
It has the function of generating 4 activation command signals. The address generator 103 also has a function of linking data that requires medium-speed ≠-data transmission between each controller and generating an address 〇. Unlike 102, this address generator has the function of stopping once the middle mode is completed and generating a signal to switch to the next low speed mode. address generator 1
04 is activated by the pause signal of the address generator 103, and has the ability to generate a link L7 address L/2 group for a data group that can be transmitted between each controller at a low speed. It has the function of generating the main switch signal for mote switching. The mode designation address generator 101 inputs signals from each of the address generators 101, 102, 103, and 104, and generates a mode designation address and a start signal for the address generator 102. Has good functionality. The voice generator 107 corresponds to each address generator 10.
This switch has the function of selecting and outputting the address generated from 2 to 104 by the address signal generated by the address generator 105 specifying the mode. The -Puji generator 106 selects the valley controller "2"'j'? from the start timing of the ready signal from each controller.
Sanawachi Multibus Oni and Vita 10 output error set signals, reception and transmission mode signals, etc. together with Natres.
The output of any one of the address generators 102 to 104 is outputted in multiple ways via a switch 107. Furthermore, the circuit diagram shown in FIG. 5) and the basic Maruna orbiter 10 will be described in detail. .

In FIG. 5, the fall address generator 101 consists of a flip-flop 15A, an AND circuit 16A, and a counter i'7A.
, an address generator 18 and an error detection circuit 19, and the address circuit 102 is a flip-flop 15B1.
The address generator 104 consists of a flip 70 block 15D1, a mode specifying address generator 10, a counter 17B, and an inverter 20.
5 consists of an OR gate 21 and a counter 22. Flip-flops 15A to 1'5D are cassette reset flip-flops, 15A is a flip-flop that is set to v' when an error occurs and is reset when the ultra-high-speed data group broadcast ends, and 15B is a flip-flop that resets when the ultra-high speed data group broadcast ends and 1. 15C is set at the end of the broadcast of cycle 2 and reset at the end of the broadcast of the high-speed data group.15C is set at the end of the transmission of the high-speed data group,
15D is reset at 1st block of the medium speed data group, and 15D is set at the end of the 1st broadcast of the medium and high speed data group, and 1 block of the low speed data group (1 block of the low speed data group is reset at the end of low speed data group) AND gates 16A to 16D are for controlling the updating of the address to be broadcast and prohibition of updating, 16.A is for updating and prohibition is canceled by flip-flop output, and 16'B is for prohibiting update by flip-flop 15C. 16D is controlled by flip-flop 15D to release the prohibition.Counts 17A to 17.D
The counter 17A counts up at the end of the ready signal from each controller, and the output of the counter 17A is the address group (selected by the multi-era data bus duplex) corresponding to the ultra-high-speed data group to be broadcast at the time of an abnormality. - there are data groups as many as the number of data groups). The output of counter 17B generates an address group corresponding to a high-speed data group. The output of counter 17C generates an address group corresponding to a medium-speed data group, and the output of counter 17D generates an address group corresponding to a low-speed data group. The OR gate 21 ORs high speed, medium and low speed one block, and broadcast end signals, and counts up one counter 22 for each end signal. Based on the output of the counter 22, the sear address generator 18 and the counter 17
B~1.7 The address group created in D is selected by the multi-channel lexer 107 and broadcast to the multi-address bus.The error detection circuit 19 detects that there is an error from the data on the multi-error data bus. It also detects the start timing of the strobe signal.
It generates a read or write strobe signal to each controller.
.

, then the multipath interface Refer to the detailed block diagram in Figure 6. I will explain based on this.

The MA/L/F mains interface receives the address from the multipath orbiter 1o and determines whether the microcontroller connected to its own spacecraft should transmit or receive, and it also malfunctions. It has a function of determining the microcontroller and performing processing such as disconnection of the controller and emergency processing. Figure 6: Smell.

The multipath interface is the transmit/receive i circuit 30.
It is composed of an S address prediction/conversion circuit 31, a buffer gate 32, a bidirectional backgate 33, an emergency processing control circuit 34, a local data control circuit 35, an error decoder 36, and an error decoder generator 37''.Transmission/reception determination circuit 3o is a group of addresses linked to a group of data that must be sent to other controllers among the data of the controller connected to the multipath interface 4, and data to be sent to other controllers. It detects a group of addresses linked to a group of data that must be received and generates control signals for transmitting and receiving data between the multipath and the controller.The address conversion circuit 31 converts the multi-address bus atrear signal Q This is a circuit that converts the address of each controller into the address of the local address bus.By the control signal generated in the four buffer gates 32 and 30, in other words, when transmitting and receiving, the i
The back gate 33 is a circuit that connects the exchanged address to the local bus, and the back gate 33 is a bidirectional back gate that connects the data bus and the local bus. Now connect the multipath data to the local bus.

The error decoder 36 determines whether the error decoder bus data is faulty or faulty in the controller connected to the multipath interface, disconnects it from the multipath and issues a command, or if it is a standby device, the program or initial data. Issues data loading commands such as The emergency processing control circuit 34 inputs a command from Korg due to an error, and if the connected device is a faulty one, it will be disconnected due to multipath.
Generates a signal that disables the data enable signal, but if the connected device is a standby device, it switches to the reception mode and also sends and receives a mode linked to the address generated by the address generator 101 in the emergency processing mode. It has a function of generating a signal for inputting a message to the transmission/reception determination circuit 30 and also generates a data enable signal.1 Normally, the transmission/reception determination signal and data enable signal output from the transmission/reception determination circuit 30 are output as they are. It has a function.

The local data control circuit 35 generates a strobe signal for controlling the writing and reading of data on the local side and a read/write signal based on signals from the multipath, and the error data generator 37 generates a read/write signal for controlling the writing and reading of data on the local side. It has a function of transmitting error data (error code) to the t-multibus in response to the controller that has generated it.

FIG. 7 is an explanatory diagram of address generation in the multipath orbiter 10. This will be explained in relation to the circuits of FIGS. 5 and 6.

First, during normal operation, address group B corresponds to high-speed data group.
is broadcast from counter 17'B for a time of tl, and at the end! Then, the address group c1 corresponding to one block of the medium-speed data group (in the figure, 1 block is - of the medium-speed data group) is set to t2.
At the end of the broadcast, an address group corresponding to one block of the low-speed data group and one block after the previous address cycle is broadcast. In addition, in the event of an error or emergency, if an abnormality occurs in the unique controller,
The abnormal multipath orbiter generates the backup controller program and initial data into the system memory, and the necessary data is broadcast from each controller to the multipath and is unconditionally fixed in reception mode by the emergency processing control circuit 34. It is stored (received) in the Yohayabusa controller. In addition, in order to make the transmission/reception determination circuit 30 for the spare controller the same as the transmission/reception determination circuit 30 of the controller in which the abnormality has occurred, the transmission/reception determination circuit 30 is switched to the write mode and the address for controlling the transmission is sent via the emergency processing control circuit 34. At the same time as writing the transmission and reception mode signals linked to the controller, the data enable signal □ is written, and at the same time as the storage of necessary data such as the program and initial data of the controller where the error occurred is completed, the transmission/reception judgment circuit of the standby unit is activated. Also, the transmission/reception determination path 30 of the controller in which the abnormality has occurred can be made the same.

As described in detail above, according to the embodiment of the present invention, process data commonly required between each controller can be inputted from one process input/output controller, thereby improving the hub system that reduces the number of process input/output controllers. Then, it is possible to perform this rapid transmission with the addition of ultra-high speed, high speed, medium speed, low speed, etc. in one multipath, and the building blocks can be used to transmit data at high speed. You will be able to do righteousness.

[Brief explanation of the drawing]

The circuit diagram of the multipath orbiter 10, FIG. 6, shows the multipath interface 13 shown in FIG. ~13- detailed block diagram, FIG. 7 is an explanatory diagram of address generation of the multipath orbiter 10, 010... multipath orbiter,
11't~11. ...multipath interface,
12... System memo L131-13. ...Microcontroller 114A, 14B...Process input/output controller 11゛5A-15D...R-8 flip-flop, 16A-16D...7 gate, 17A
~17D. 22...Counter, 18...Address generation circuit) 1
9°°°" 2-Detection circuit・20°°°ear press 21...OR gate, 30...Address detection control circuit, 31...Address conversion circuit, 32...Buffer gate, 33 ...Bidirectional buffer gate, 35...
- Local data control circuit, 36...Error, -decoder, 37...Error decoder generator, 101
...Address generator in emergency processing mode, 102...
・Address generator in high-speed data processing mode, -103
...Address generator in constant speed data processing mode, 10
4...Address generator in low-speed data processing mode, 1
o5 Agent 7 Physician Takashi AkiraContinued from page 10 Author Nagase Yoshihito 5-2-1 Hitachi University Mika-cho ゛ Hitachi Co., Ltd. Omika Factory Author Yutaka Saito 5-2 Hitachi University Mika-cho No. 1 Hitachi, Ltd. Omika Factory □ 0 inventors Takahiro Sakurai 5-2-1 Hitachi University, Mika-cho Hitachi Ltd. Omika Factory 0 inventors Susumu Kitani. 5-2-1 Hitachi Daimika-cho Hitachi, Ltd. Omika Factory 0 Inventor: Yuji Kikuchi 5-21-1 Hitachi Daimika-cho, Hitachi, Ltd. Omika Factory 0 Inventor: Yoshihiro Kamigane, Hitachi, Ltd. Omika Factory 5-2-1 Hitachi, Ltd. Omika Factory

Claims (1)

[Claims] 1. In a multi-microcontroller system in which a process is controlled by a plurality of microcontrollers connected via multipaths, each of the data commonly required by the plurality of microcontrollers is Connecting a path orbiter to which a corresponding address is assigned to the i■Lerci bus, and periodically outputting at least a group of consecutive addresses from the path orbiter to the multipath,
Whether a microcontroller connected to the multipath interface should transmit or receive based on an address signal output from the path orbiter by a plurality of multipath interfaces having a function of connecting the multipath and the plurality of microcontrollers. A multi-control system for microcontrollers, characterized in that any one microcontroller simultaneously transmits data to at least 41 other microcontrollers. 2. The microcontroller multi-control system according to claim 1, wherein the address output from the multipath orbiter has each mode of ultra-high speed, high-speed, medium-speed, and low-speed. 3. Among the multiple modes of AT/S generated by the Multi-Fusion Operator, use the ultra-high speed mode to send data to the backup unit in the event of a controller failure! 3. A multi-control system for a microcontroller according to claim 2, characterized in that the microcontroller is in a storage mode.