JPS584274Y2 - Fiber optic digital link receiver circuit - Google Patents

Fiber optic digital link receiver circuit

Info

Publication number
JPS584274Y2
JPS584274Y2 JP1976151484U JP15148476U JPS584274Y2 JP S584274 Y2 JPS584274 Y2 JP S584274Y2 JP 1976151484 U JP1976151484 U JP 1976151484U JP 15148476 U JP15148476 U JP 15148476U JP S584274 Y2 JPS584274 Y2 JP S584274Y2
Authority
JP
Japan
Prior art keywords
output
comparator
digital link
amplifier
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1976151484U
Other languages
Japanese (ja)
Other versions
JPS5370113U (en
Inventor
遠藤守
本多正典
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1976151484U priority Critical patent/JPS584274Y2/en
Publication of JPS5370113U publication Critical patent/JPS5370113U/ja
Application granted granted Critical
Publication of JPS584274Y2 publication Critical patent/JPS584274Y2/en
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は、閾値レベル変動を補償した光フアイバディジ
タルリンク受信回路tこ関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical fiber digital link receiver circuit that compensates for threshold level variations.

光フアイバディジタルリンク受信系の回路構成は第1図
tこ示すよう1こフォトダイオードなどの受光素子り、
抵抗R1増幅器A、比較器C1および基準電源Esから
なり、ファイバを通して伝送される信号の光を受光素子
りで受け、抵抗Rと供に電気信号1こ変換し、これを増
幅器Aで増幅し、その後比較器Cで基準電圧と比較して
波形成形する。
The circuit configuration of the optical fiber digital link reception system is shown in Figure 1, which includes one light receiving element such as a photodiode,
It consists of a resistor R1, an amplifier A, a comparator C1, and a reference power source Es, receives the signal light transmitted through the fiber with a light-receiving element, converts it into one electrical signal with the resistor R, and amplifies this with the amplifier A. Thereafter, a comparator C compares it with a reference voltage and shapes the waveform.

この受信回路は直流から伝送できるようtこ受光素子り
、増幅器A、比較器Cは直結されでおり、そのため電源
変動、温度変動の影響を受けやすい。
This receiving circuit has a light receiving element, amplifier A, and comparator C that are directly connected to each other so that direct current can be transmitted, and is therefore susceptible to power supply fluctuations and temperature fluctuations.

例えば電源電圧が変動すると増幅器Aの出力電圧Vou
tの直流レベルが変り、一方、基準電源Esの電圧は一
定であるから比較器Cの識別レベルが変動することをこ
なり、特性上好ましくない。
For example, when the power supply voltage fluctuates, the output voltage Vou of amplifier A
Since the DC level of t changes and, on the other hand, the voltage of the reference power source Es is constant, the discrimination level of the comparator C fluctuates, which is unfavorable in terms of characteristics.

例えば本回路1こおいではこれは最低受信レベルの変動
としで現われる。
For example, in the present circuit 1, this appears as a variation in the minimum reception level.

温度変動1こついても同様である。本考案は極めて簡単
な手段會こよってか\る点を改善するものであって、そ
の特徴とする所は光ファイバデイジタルリンク受信回路
を受光素子と。
The same applies if there is a temperature fluctuation. The present invention is an attempt to improve these points by using extremely simple means, and its feature is that an optical fiber digital link receiving circuit is used as a light receiving element.

該素子の出力を受けで正、負方向1こ変化する2つの出
力を生じる2出力型の増幅器と、該増幅器の2出力を正
1頁入力端子1こ抵抗素子を介して加えられる比較器と
、該比較器の正、負入力端子tこ一端および他端を接続
され、中間摺動端子には基準電圧を印加されるポテンシ
ョメータとで構成した点1こある。
a two-output type amplifier that generates two outputs that change by one in the positive and negative directions in response to the output of the element, and a comparator to which the two outputs of the amplifier are applied to the positive input terminal and one resistor element. , the positive and negative input terminals of the comparator are connected to one end and the other end, and a potentiometer is connected to the intermediate sliding terminal to which a reference voltage is applied.

以下実施例を参照しながらこれを詳細に説明する。This will be explained in detail below with reference to Examples.

第2図は本考案の実施例を示し、D、R,およびCは第
1図と同様1こ受光素子、抵抗、および比較器である。
FIG. 2 shows an embodiment of the present invention, in which D, R, and C are a light receiving element, a resistor, and a comparator, as in FIG.

本考案では増幅器Aとして、入力信号奢こ応じて正、負
、方向1こ変化する2つの出力+Vout 、−Vou
tを生じる2出力型の増幅器Aaを用い、一方の出力+
Voutは比較器Cの正入力端子+■N1こ抵抗R1を
介して、また他方の出力−Voutは比較器Cの負入力
端子−IN+こ抵抗R2を介してそれぞれ接続し、これ
らの比較器入力端子+IN −IN#こは更1こポテ
ンショメーりVRの一端および他端を接続し、該ポテン
ショメータの中間摺動端子をこ基準電圧Vcを加える。
In the present invention, the amplifier A has two outputs +Vout, -Vou that change by one direction, positive or negative, depending on the input signal.
Using a two-output amplifier Aa that produces t, one output +
Vout is connected to the positive input terminal of the comparator C through the resistor R1, and the other output -Vout is connected to the negative input terminal of the comparator C through the negative input terminal -IN+ through the resistor R2. The terminal +IN -IN# is further connected to one end and the other end of the potentiometer VR, and a reference voltage Vc is applied to the middle sliding terminal of the potentiometer.

この回路をこよれば、増幅器Aaの出力+Voutと−
Voutの直流レベルははゾ同じであり、電源電圧変動
1こよる該直流レベルの変動量もはゾ同じであってかつ
その変化方向も同じであるので、比較器Cから見ればこ
の電源電圧の変動1こよる直流レベルの変動は打消され
てしまい、こうして電源電圧変動の影響を除去すること
ができる。
If you go through this circuit, the outputs of amplifier Aa +Vout and -
The DC level of Vout is the same, and the amount of variation in the DC level due to power supply voltage fluctuation is also the same and the direction of change is also the same, so from the perspective of comparator C, this power supply voltage The fluctuation in the DC level due to the fluctuation 1 is canceled out, and thus the influence of the power supply voltage fluctuation can be eliminated.

比較器Cの正、負入力端子+IN、−IN*こ加わる電
圧をVinl 、 Vin2とすればこれらは次式で表
わされる。
If the voltages applied to the positive and negative input terminals +IN and -IN* of the comparator C are Vinl and Vin2, these can be expressed by the following equation.

こ\でvRl、VR2はポテンショメータVRのR2側
、R2側の抵抗である。
Here, vRl and VR2 are the resistances on the R2 side and R2 side of the potentiometer VR.

こ\で直流レベルについては■Vou t =Q Vo
u tであり、これをVとおくと、比較器Cに加わる差
電圧、l(VはJV=Vjn −Vin2 ■ 即ち抵抗R19R2,ポテンショメータの分割抵抗VR
,,VR2)こよって定まる係数が掛かるが、これらを
適当1こ選べば比較器Ctこは第1図と同様1こ増幅器
Aaの出力電圧Vと基準電圧Vcとの差電圧が入力する
Regarding the DC level, ■ Vout = Q Vo
u t, and let this be V, then the differential voltage applied to the comparator C, l (V is JV = Vjn - Vin2 ■ That is, resistor R19R2, potentiometer dividing resistor VR
, , VR2), and by selecting one of them, the difference voltage between the output voltage V of the amplifier Aa and the reference voltage Vc is input to the comparator Ct, as in FIG.

従って基準電圧Vcで受信電圧を識別して波形整形を行
なうことができる。
Therefore, it is possible to identify the received voltage using the reference voltage Vc and perform waveform shaping.

識別レヘ/L/ Gi コt’lらの抵抗R1,R2,
vRl、VR2を調整すること1こより調整できる。
Identification Rehe/L/ Gi Kot'l's resistances R1, R2,
It can be adjusted simply by adjusting vRl and VR2.

なお抵抗R1゜R2は通常R1=R2をこしでおく。Note that the resistance R1°R2 is usually set so that R1=R2.

温度変動・こよる識別レベルの変動は第3図または第4
図の回路1こより補償することができる。
Temperature fluctuations and fluctuations in discrimination level are shown in Figure 3 or 4.
Compensation can be achieved using the circuit 1 shown in the figure.

これらの図でり、R2Aa、およびCは第1図と同様1
こ受光素子、抵抗、増幅器、および比較器であり、そし
てR1,R2は抵抗、VRはポテンショメータ、VCは
基準電圧である。
In these figures, R2Aa and C are 1 as in Figure 1.
These are a light receiving element, a resistor, an amplifier, and a comparator, and R1 and R2 are resistors, VR is a potentiometer, and VC is a reference voltage.

本回路では第3図の場合tこは抵抗R2iこ直列に半導
体ダイオードD1を挿入し、このダイオードの温度特性
を利用して温度補償し、第4図の例では抵抗R2の代り
tこサーミスタと抵抗を組合せた温度特性のある素子R
THを用いて温度補償する。
In this circuit, in the case of Fig. 3, a semiconductor diode D1 is inserted in series with the resistor R2i, and temperature compensation is performed using the temperature characteristics of this diode.In the example of Fig. 4, a thermistor is inserted in place of the resistor R2. Element R with temperature characteristics combined with resistance
Temperature compensation is performed using TH.

以上詳細に説明したよう・こ本考案(こよれば2出力型
の増幅器を用い、これ・こ抵抗回路網を組合せるという
簡単な手段1こより電源電圧の変動・こ基ずく識別レベ
ルの変動を抑えることができ、またダイオード、サーミ
スタなどの感温素子を簡単tこ組込んで温度補償するこ
とができ、光フアイバディジタルリンクの受信回路とし
で優れた受信回路が得られる。
As explained in detail above, this invention (according to this invention) uses a two-output type amplifier and combines it with a resistor network, which is a simple method to reduce fluctuations in the power supply voltage and, therefore, in the identification level. It is possible to easily incorporate temperature sensitive elements such as diodes and thermistors for temperature compensation, and an excellent receiving circuit for optical fiber digital links can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の受信回路図、第2図〜第4図は本考案の
受信回路の実施例を示す回路図である。 D・・・・・・受光素子、Vc・・・・・・基準電圧、
R,R,。 R2・・・・・・抵抗、VR・・・・・・ポテンショメ
ータA。 Aa・・・・・・増幅器、Dl・・・・・・ダイオード
、C・・・・・・比較器、RTH・・・・・・温度特性
素子、R8・・・・・・基準電圧。
FIG. 1 is a conventional receiving circuit diagram, and FIGS. 2 to 4 are circuit diagrams showing embodiments of the receiving circuit of the present invention. D... Light receiving element, Vc... Reference voltage,
R, R,. R2...Resistance, VR...Potentiometer A. Aa...Amplifier, Dl...Diode, C...Comparator, RTH...Temperature characteristic element, R8...Reference voltage.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)受光素子と、該素子の出力を受けで正、負方向1
こ変化する2つの出力を生じる2出力型の増幅器と、該
増幅器の2出力を正、負入力端子tこ抵抗素子を介して
加えられる比較器と、該比較器の正、負入力端子1こ一
端および他端を接続され、中間摺動端子には基準電圧を
印加されるポテンショメータとを備えることを特徴とす
る光フアイバディジタルリンク受信回路。
(1) A light-receiving element and the output of the element in positive and negative directions 1
A two-output amplifier that produces two outputs that change, a comparator to which the two outputs of the amplifier are applied to positive and negative input terminals via a resistor element, and one positive and negative input terminal of the comparator. 1. An optical fiber digital link receiving circuit comprising a potentiometer having one end connected to the other end and having a reference voltage applied to an intermediate sliding terminal.
(2)2出力型理幅器の負方向1こ変化する出力を生じ
る端子1こ直列1こ接続された抵抗素子が、純抵抗とそ
れ・こ直列な温度特性を持つダイオードとで構成された
ことを特徴とする実用新案登録請求の範囲第(1)項記
載の光フアイバディジタルリンク受信回路。
(2) The resistance element connected in series with one terminal that produces an output that changes by one in the negative direction of the two-output width divider is composed of a pure resistance and a diode with temperature characteristics in series with it. An optical fiber digital link receiving circuit according to claim (1) of the utility model registration.
(3)2出力型理幅器の負方向1こ変化する出力を生じ
る端子1こ直列に接続された抵抗素子がサーミスタであ
ることを特徴とする。 実用新案登録請求の範囲第(1)項記載の光フアイバデ
ィジタルリンク受信回路。
(3) The two-output width divider is characterized in that the resistance element connected in series with one terminal that produces an output that changes by one in the negative direction is a thermistor. An optical fiber digital link receiving circuit according to claim (1) of the utility model registration.
JP1976151484U 1976-11-11 1976-11-11 Fiber optic digital link receiver circuit Expired JPS584274Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1976151484U JPS584274Y2 (en) 1976-11-11 1976-11-11 Fiber optic digital link receiver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1976151484U JPS584274Y2 (en) 1976-11-11 1976-11-11 Fiber optic digital link receiver circuit

Publications (2)

Publication Number Publication Date
JPS5370113U JPS5370113U (en) 1978-06-13
JPS584274Y2 true JPS584274Y2 (en) 1983-01-25

Family

ID=28759734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1976151484U Expired JPS584274Y2 (en) 1976-11-11 1976-11-11 Fiber optic digital link receiver circuit

Country Status (1)

Country Link
JP (1) JPS584274Y2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55130262A (en) * 1979-03-30 1980-10-08 Nec Corp Bipolarity discrimination circuit
JPS5912661A (en) * 1982-07-13 1984-01-23 Fujitsu Ltd Variable threshold value type differential signal receiver
US4499386A (en) * 1982-11-26 1985-02-12 Tektronix, Inc. Trigger circuit

Also Published As

Publication number Publication date
JPS5370113U (en) 1978-06-13

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