JPS5842687B2 - Static overcurrent protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static overcurrent protection device, and more particularly to a circuit for generating a charging pulse current for an integrating circuit.

FIG. 1 is a block diagram showing a typical example of a static overcurrent relay, which is the background of the present invention.

In this example, a three-phase AC circuit is shown as the main circuit.

Therefore, the main circuit is provided with three-phase electric wires 1a, 1b, and 1C, and an air circuit breaker 2 is inserted into each of the wires 1a to 1c.

Each of these lines 1a to 1C is individually provided with a current transformer 3 for detecting the current flowing through each line.

The currents detected by these current transformers 3 are given to auxiliary current transformers 4, respectively.

Then, each input current from the auxiliary current transformer 4 is applied to a rectifier circuit 5 such as a full-wave rectifier circuit, and is extracted as a direct current.

In this case, the direct current taken out from each line 1 a t
Of l b t l c, it responds to the current of the phase with the maximum absolute value at each time point.

A direct current correlated to the maximum input current from the rectifier circuit 5 is shunted to a control power supply circuit 6, a long time signal circuit 7, and a short time signal circuit 8, respectively.

Then, in the control power supply circuit 6, a DC voltage is generated from the shunted DC current, and is used as a power source for each element of the damping circuit shown surrounded by the two-dot dotted line in FIG.

In addition, the long time signal circuit 7 (the short time signal circuit 8 is also similar, but is omitted because it is not related to this application) generates a long time signal necessary for long time operation based on the shunted DC current. Derived as a flow.

The long time signal is input to a peak value holding circuit 9 and a pickup circuit 10.

The peak value holding circuit 9 generates a DC voltage at a level corresponding to the peak value of the maximum input current, and supplies it to the subsequent pulse charging circuit 11.

Further, the pickup circuit 10 determines whether or not to operate for a long time depending on the maximum input current that has passed through the long time limit signal circuit 7 and whether this maximum input current is a percentage of the rated current.

Therefore, in this pickup circuit 10, when the maximum input current exceeds the rated current by a predetermined ratio, the integrating circuit 12 forming the time limit circuit is activated.

The pulse charging circuit 11 generates a charging pulse current to the integrating circuit 12 according to the DC voltage of the peak value holding circuit 9.

Further, the integrating circuit 12 includes, for example, a capacitor, and the voltage across the capacitor or the terminal voltage is compared with a predetermined voltage by a subsequent comparing circuit 13.

Then, in the comparator circuit 13, when the terminal voltage of the integrating circuit 12 exceeds a predetermined voltage, the trip coil 1 is
The SCR trigger circuit 14, which is to apply a trigger voltage to the thyristor (SCR) for causing current to flow through the SCR circuit 5, is instructed to output a trigger output.

Therefore, in a static overcurrent protection device having such a configuration, for example, as shown in FIG. 2, when the main circuit current, that is, the maximum input current reaches 100% to 125% of the rated current, the pickup Circuit 10 is activated.

Accordingly, the integrator circuit 12 is activated and the pulse charging circuit 1
The integrator circuit 12 is charged by a charging pulse with an energy corresponding to the maximum input current from 1 .

When the terminal voltage of the integrating circuit 12 exceeds a predetermined voltage after a certain period of time has elapsed, the tripping coil 15 is activated and the air circuit breaker 2 provided in the main circuit is tripped.

The detailed operation of such a static overcurrent relay is well known, so a detailed explanation thereof will be omitted.

Further, short-time operation and instantaneous tripping operation will also be omitted.

Generally, the time limit of the long drive operation of such a static overcurrent relay has an inverse time limit characteristic as shown in FIG.

Further, in consideration of the Joule heat characteristics of the device to be protected, it is preferable that such an inverse time limit characteristic is such that the square of the input current times the tripping operation time is constant (I2t=constant).

And, in such a long-term stationary overcurrent relay,
Because the time limit for this charge is long, a pulsed current is used instead of a continuous current to charge the integrating capacitor.

The present invention is directed to a pulse charging circuit for obtaining constant characteristics of I2 through such pulse charging.

Therefore, the main object of the invention is to provide a new type of static overcurrent protection device in which the integrating capacitor is charged with 2t=constant current pulses.

In summary, this invention applies a charging current to a capacitor of an integrating circuit as a pulse current, makes the width of the pulse proportional to the input current, makes the pulse repetition frequency or synchronization constant regardless of the input current, and This is a static overcurrent protection device in which the pulse current value is made proportional to the input current.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 3 is an electric circuit diagram showing a specific embodiment of the present invention.

In the structure, FIG. 3 particularly shows the pulse charging circuit 11 and the integrating circuit 12 in detail.

Then, the input current from the rectifier circuit 5 and therefore the long time signal circuit 7 (correlated with the maximum instantaneous value of the main circuit current)
is given to the peak value holding circuit 9.

The peak value holding circuit 9 generates a voltage Vin corresponding to this input current (2).

This input voltage V in is commonly applied to the bases of the transistors Trl, Tr2, and Tr4 that constitute the pulse charging circuit 11.

The emitter of this transistor Tr1 is a resistor R1.
is connected to the voltage Vs via the resistor R2, and its collector is connected to the ground potential via the resistor R2.

Furthermore, the collector of this transistor Trl is connected to PUT(
Programmable unijunction transistor)S
It is connected to the gate electrode of l.

Further, the transistor Tr2 is connected to the power source Vs via an emitter resistor R3, and its collector is connected to the PU
It is connected to the anode of T81 and to the positive side of capacitor C1.

The cathode of this PUT 81 is grounded.

The negative side of the capacitor C1 is connected to the transistor Tr.
3 and is grounded via a series connection circuit of a diode D1 and a resistor R5.

The emitter of the transistor Tr3 is connected to the power supply Vs via a resistor R4, and the base thereof is connected to the power supply Vs.
A constant voltage is provided in which s is divided by resistor R6, diode D2, and resistor R7.

Furthermore, the emitter of the transistor Tr4 is connected to a resistor R8.
is connected to the voltage Vs via the transistor Tr5, and its collector is connected to the collector of the transistor Tr5.

The base of the transistor Tr5 is connected to the diode D1.
and the resistor R5, and its emitter is grounded.

The collector of the transistor Tr5 serves as the output terminal of the pulse charging circuit 11, which is connected to the anode of the diode D3 and to the comparison input terminal of the comparison circuit 13.

The cathode of the diode D3 constituting the integration circuit 12 is connected to one electrode of the integration capacitor C2.

The other electrode of this integrating capacitor C2 is grounded.

Note that the comparison circuit 13 is energized by the power supply Vs.

The operation of the above configuration will be explained in detail below with reference to the waveform diagram of each part in FIG. 4.

As mentioned above, the voltage Vin from the peak value holding circuit 9 is proportional to the input current, and its magnitude is determined by the following formula (
1).

Vin=kI+0.7 (V)...
・・・・・・・・・・・・(1) Here, this input voltage V
The transistor T whose in is increased by 0.7V
ri, Tr2. This is to compensate for the forward voltage drop between the penis emitters of Tr4.

Therefore, the emitter current, that is, the collector current ICI of the transistor Tr1 is expressed by Kuji 2).

■ ＝に■／R1・・・・・・・・・・・・・・・・・・
(21) Therefore, the voltage drop across the resistor R2, that is, the bias voltage fc2 of PUTS1 is given by the following equation (3).

2 V = I XR2 = −−kI ・−−
(3) R2CI R1 As is clear from this equation (3), it can be seen that the bias voltage h2 of PUTS1 is proportional to the input current I.

Next, consider the charging current of capacitor C1.

The charging current of this capacitor C1 is: power supply ■s - resistor R3
- collector capacitor C1 of emitter Tr2 of transistor Tr2 - diode D1 - flows into ground potential via resistor R5 and transistor Tr5.

That is, when the charging current of the capacitor C1 flowing through the resistor R5 causes the voltage across the resistor R5 to exceed approximately 0.7V (the forward voltage between the base and emitter of the transistor Tr5), the transistor Tr5 is turned on and the capacitor C1 is turned on. A charging current flows between the base and emitter of this transistor Tr5.

Further, when the transistor Tr5 is turned on, the emitter current, that is, the collector current IC'4 of the transistor Tr4, which is turned on by the input voltage Vin, flows into the transistor Tr5 and does not flow in the direction of the integrating circuit 12.

Here, if the voltage drop between the base and emitter of the transistor Tr5 is approximately 0.7 V as described above, and the voltage drop of the diode b1 is also approximately 0.7 V, the potential on the negative side of the capacitor C1 is approximately 1 .4V (0,
7+0.7).

Now, when charging using this charging path, as an initial condition, the positive side potential of capacitor C1 is O, and if the time for this positive side potential to reach the bias voltage ■R2 of PUTSl is tl, then the voltage drop across resistor R3 is Since VR3= is (2), the emitter current of the transistor Tr2 and therefore the collector current (2) c2, that is, the charging current is expressed by the following equation -.

I = k I/R3・・・・・・・・・・・・・
......(4)2 Therefore, the charging time t1 is given by the following equation (5).
6・8゜kwork/R3・tl=c1・−・kI I R2・R3 tl=・C1・・・・・・(5)1 As can be seen from this equation (5), this charging time t1
is constant regardless of the input current ■.

This charging time t1 is determined by the integration capacitor C as described later.
This corresponds to a charging pulse period of 2.

Therefore, from this equation (5), it can be seen that this charging pulse period, that is, the pulse repetition frequency is constant regardless of the input current I.

When the potential on the anode side of the PUTS1 becomes equal to the bias voltage (2) by -2, the anode and cathode of the PUTS1 become conductive.

Therefore, when time t1 elapses after charging of capacitor C1 is started, PUTS1 is turned on, and the positive side of capacitor C1 is grounded.

However, immediately before this PUTS1 becomes conductive, there is a potential difference between the positive side and the negative side of the capacitor C1 as shown in the following equation (6).

2 ■ =-・kI-1,4(V)=Vi□-1,4(V)
” R1, -1-0-0 (6) Therefore, when the positive side of this capacitor C1 is forced to the ground potential, that is, O■, at the moment this PUTSl is turned on, the negative side of the capacitor C1 maintains the above potential difference. In order to do this, from the previous 1.4■
) changes to a negative potential of V.

Here, as can be seen from the equation (3) above, the voltage vk2 changes depending on the input current I, but generally, even when this input current ■ is about 100% of the rated current, it varies by at least 2 It can be seen that the potential on the negative side of this capacitor C1 is always 1.multidot. because it is determined to exceed (2).

Therefore, in this way, the positive side potential of capacitor C1 becomes equal to voltage vR2, and PUT 81. At the moment D1 is turned on, die No. 1 is reverse biased.

Therefore, the transistor Tr5 is turned off, and the emitter current of the turned-on transistor Tr4 passes through the diode D3 and charges the integrating capacitor C2.

That is, the integrating capacitor C2 of the integrating circuit 10 is charged only when the anode and cathode of PUTS1 are in a conductive state.

On the other hand, the current for discharging the capacitor C1 is
It flows through the path of power supply Vs-resistor-4-transistor Tr3-capacitor-PUTS1-ground.

In other words, this discharge current and the collector current of the transistor Tr2 flow through the PUT 81.
This discharge current is set to significantly exceed the valley point current of PUTS1 (the current value that returns to a non-conductive state when the anode current of PUTS1, which has entered a conductive state, is decreased).

When the voltage at one side of the capacitor C1 reaches approximately 1.4V, the collector current of the transistor Tr3 is transferred to the diode DI, the resistor R5, and the transistor Tr5.
The current flows to the capacitor C1 and stops flowing to the capacitor C1.

Therefore, the current flowing through PUT Sl is only the collector current of transistor Tr2, but since this current is set to be below the valley point current of PUTSl mentioned above, PUT 81 quickly becomes non-conductive. .

Further, this discharge current is a constant current determined by the constant bias of the transistor Tr3 (that is, the sizes of the resistors R6, R7, and R4), and the
3's collector current is Ic3, and the time until the potential on the one terminal side of the capacitor C1 returns to 1.4V (PUTS1 becomes non-conductive) is t2, this time t2
(7) This discharge time t2 is proportional to the input current ■.

That is, since the discharge current of the capacitor C1 is set to be a constant current, the larger the input current I, the larger the charge, and therefore the longer the discharge time t2.

Therefore, the off time of the transistor Tr5 becomes longer, and the charging pulse width t2 to the integrating capacitor C2 becomes larger.

As shown in equation (7), the charging pulse width t2 becomes proportional to the input current I.

Further, the charging current to the integrating capacitor C2 is the emitter current of the transistor Tr4, that is, the collector current IC
4 and is expressed by the following equation (8).

I = ni■/R8・・・・・・・・・・・・・・・・・・
...(8)4 As can be seen from this equation (8), the integral capacitor C
The magnitude of the charging current to 2, that is, the magnitude of the pulse current, is proportional to the input current I.

The above explanation is summarized and shown by each waveform in FIG. 4.

In addition, in FIG. 4, the charging time, that is, the pulse repetition period t1, is shown to be slightly different when the input current I is small and when the input current I is large, but this is due to the charging pulse width t2 to the integrating capacitor C2. This is because the illustration was exaggerated to clearly show the difference.

In reality, the time t1 is several tens of milliseconds, and the time t2 is several tens to hundreds of microseconds.

Therefore, this time t1 is extremely large compared to time t2, and this time t2 can be almost ignored.

Therefore, the pulse repetition period t1 is constant.

As mentioned above, according to this embodiment, the integrating capacitor C
2t is always constant because the charging pulse width t2 to 2 is made proportional to the input current, the repetition period t1 is made constant, and the magnitude of the current is made proportional to the input current.

That is, the pulse repetition period t1 is constant, and if the number of charging pulses within a unit time is f, then f'', t.

Therefore, if the number of pulses generated during the operating time t is n, then from the previous equation (5), this number n is given by the following equation (9).

Rlot R2-R3,.

1°−°−°−−−−−−−−−−−−°(9) n =
f t = Further, the pulse width t2 is expressed by equation (7), and the pulse current is expressed by equation (8).

Therefore, if the integrating capacitor C2 reaches a predetermined voltage E at time t, then it becomes nt2・Io42C2・E, and from the above formulas, R1・t R2・kI KI X −X −= C2X E R2−R3−CI R1− Ic3 R8l2t=R3
°R8°C1°IC3・C2・E2, and ■2t=constant.

Furthermore, the electric charge charged in the capacitor C1 at each period t1 is eventually completely discharged by the constant collector current ICa of the transistor Tr3, and the PUT
The long drive operation time t remains constant regardless of slight variations in the on-timing of Sl, that is, the bias voltage 8□.

In other words, even if the bias voltage VR2 fluctuates due to some reason (temperature, etc.), the operating time t remains constant.
It can be seen that the temperature characteristics are extremely good.

Note that the above-mentioned embodiment is merely shown as one specific example in order to omit the details of the pickup circuit and specifically explain the idea of the present invention, and the present invention is not limited to such a specific circuit. Of course, it is not limited to.

As described above, according to the present invention, in the static overcurrent protection device, it is possible to extremely stably obtain the characteristic l2t=constant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a static overcurrent relay which is the background of the present invention. FIG. 2 is a graph showing the time-limiting characteristics of this static overcurrent relay, where the horizontal axis shows the percentage of the rated current, and the vertical axis shows the tripping operation time (1). FIG. 3 is an electrical circuit diagram showing one embodiment of the present invention. FIG. 4 is an operational waveform diagram of each part for explaining this embodiment. In the figure, 1a, 1b, 1c are main circuit lines, 5 is a rectifier circuit, 9 is a peak value holding circuit, 11 is a pulse charging circuit, 12 is an integration circuit, 13 is a comparison circuit, 15 is a tripping coil, Trl or Tr5 is a transistor, R1 to R8 are resistors, C1 is a capacitor, C2 is an integrating capacitor, and Sl is a PUT.

Claims (1)

[Scope of Claims] 1. In an overcurrent protection device that interrupts the main circuit current with a time limit when the main circuit current exceeds a predetermined value, the current is proportional to the magnitude of the main circuit current. When the positive terminal voltage of the capacitor reaches a threshold proportional to the magnitude of the main circuit current, the positive terminal of the capacitor is grounded and the capacitor is charged. a grounding means for bringing the negative terminal to a negative potential with respect to the ground potential; and after the positive terminal of the capacitor is grounded, the capacitor is discharged with a constant current unrelated to the magnitude of the main circuit current. , is conductive during the charging period of the capacitor,
a pulse oscillation means including a switching element that is non-conducting during a discharging period; an integrating capacitor that is provided in parallel with the pulse oscillation means and charged with a current proportional to the magnitude of the main circuit current; tripping means for interrupting the main circuit in response to a terminal voltage of the integrating capacitor reaching a predetermined value; A static overcurrent protection device that is charged by current.