JPS5841783B2 - Static induction transistor logic semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static induction transistor logic (hereinafter referred to as 5ITL) semiconductor integrated circuit device with improved frequency characteristics.

Due to the high density and high integration of semiconductor integrated circuits, there is no need to separate elements, and the number of steps is simple.
The S, FET method has been mainly used.

Considering the formation of the base layer of the bipolar system and the channel layer of the MO8 system, which have an important influence on the comprehensive comparison of the electrical performance of the bipolar system and the MO8 system, precise control of the base layer of the bipolar system is important when comparing the electrical performance of the MO8 system. It is easier than controlling the length, it is easier to achieve higher speeds, and there are fewer problems in manufacturing, so it is easier to control the separation between elements.
If problems such as the large number of steps are solved, it is inevitable that high-density, highly integrated semiconductor integrated circuits that can be used on floor desks at higher speeds and higher frequencies will emerge.

As a method to improve the above-mentioned problems in the bipolar system, a composite structure of a conventional horizontal PNP transistor and a vertical NPN transistor is used, and I
c-tion Logic) or horizontal PNP)
5ITL (Sta
ticI induction Transitor
Logic) has been proposed.

As mentioned above, the present invention relates to a semiconductor integrated circuit device having a 5ITL configuration.
In order to facilitate understanding of the TL, the structure of the conventionally known IIL shown in FIG. 1a will be explained first, and the conventional 5ITL will be explained in comparison with this.

Figure 1a shows the basic gate structure of IIL, in which 1 is an n-type semiconductor substrate, 2 is an n-type semiconductor layer formed on the n-senju conductor substrate 1 by vapor phase growth, etc. 3 is a P formed in the n-type semiconductor layer 2 including its main surface 2a.
A type base region 4 has the main surface 2a in the P type base region 3.
a plurality of n-type collector regions formed including n
A P-type injector region that includes the main surface 2a of the semiconductor layer 2 and is separated from the P-type base region 3;
is an injector terminal connected to the injector area 5,
B is an input terminal connected to the P-type base region 3, C□, C
2 is a multi-collector output terminal connected to a plurality of n-type collector regions, respectively.

Reference numeral 100 denotes a horizontal pnp (pnp) transistor formed by the above-mentioned elements 5 and 2.3, which functions as a constant current source and a load.

Reference numeral 110 denotes a vertical NPN (npn) transistor formed by the above-mentioned elements 1 to 4, which functions as a switching transistor.

In the figure, ``A'' represents a hole, and ``A'' represents an electron, and the behavior of each is shown.

Figure 1 shows the basic gate structure of S ITL.
In the figure, reference numeral 11 denotes an n-type semiconductor substrate serving as a second region, and reference numeral 12 denotes an n-type semiconductor substrate formed on the semiconductor substrate 11 by a vapor phase growth method, etc., with an impurity concentration as low as 1013 to 1014/cm.
The first region, 13, of the mold has its major surface 1 within the first region 12.
A plurality of n-type third regions formed including 2a, 1
4 includes its principal surface 12a within the first region 12, surrounds the third region 13, and is formed deeper than the third region 13. This is the area of

By providing a difference in impurity concentration between the fourth region 12 and the fourth region 14 in this way, the channel length in the fourth region 12 can be easily controlled and a wide control variable range can be provided. Even when no voltage is applied to the fourth region 14, the fourth region 12 below the third region 13 is connected to the depletion layer >J, and the channel is in a pinch-off state.

At this time, a high potential barrier is generated within the channel, and no drain current flows when the drain voltage is low.

Reference numeral 15 denotes a P-type fifth region I, which is formed within the fourth region 12 and separated from the fourth region 14, including its main surface 12a.
s is an injector terminal connected to the fifth region 15, G
is an input terminal connected to the fourth region 14, and Dl and D2 are multi-drain terminals connected to a plurality of third regions 13.

Note that the P-type fourth region 14 is the n-type third region 13.
They are electrically connected in plan view except for the 0 portion.

20 is the horizontal PNP formed in 14.12.15)
A transistor that acts as a constant current source and load.

21 replaces the vertical NPN) transistor of the IIL,
The reverse-operating vertical static induction transistor C (hereinafter referred to as SIT) formed by the above-mentioned elements 11 to 14 functions as a switching transistor.

Figure 2 shows the static characteristics of 5ITL.

In the figure, I is the drain voltage vD, tt is the drain current ID,
III is the forward junction characteristic between the gate and source of SIT constituting the 5ITL inverter, and IV is the gate voltage 0.6
Current characteristics at ~0.7 volts, ■ indicates the load curve.

As long as the drain voltage is low, no drain current flows, which corresponds to the curve (■).

Next, when the gate voltage is increased in the positive direction, the potential barrier decreases.

For this reason, electrons begin to flow from the source to the drain.

VD-I when applying 0.6 to 0.7 volts to the gate
The D characteristic is the curve ■ on the left side of Figure 2.

At this time, the junction between the gate and n-channel of P+ is in a forward bias state, and holes 2 are injected from the gate to the channel.

The 5ITL uses the above two states (A, B), the load of the switching transistor is a PnP constant current source like the IIL, and the load characteristics are as shown by the curve 2 in FIG.

A is in the off state and B is in the on state.

As described above, the pnp transistor in both IIL and 5ITL functions as both a constant current source and a load, and no resistance is used for either the power source or the load.

In addition, the common area n layer is grounded in order to have a common emitter and common source configuration for qpn) transistors and SIT, and a common base configuration for pnp) transistors, and there is no need for any separation distance between elements. There is no need for any structural complexity, and the integration density is similar to that of conventional bipolar and MOS
, much higher than the FET method.

On the other hand, IIL from a performance standpoint! :5ITL, they all have a small capacity and a low power consumption, which is the figure of merit of a logic circuit.
The delay time product C (referred to as PD product) is extremely small.

The capacity that affects performance is, in the case of IIL in Figure 1a,
In the case of 5ITIC, the emitter-base capacitance Ceb and the collector-base capacitance Ccb are the source-gate capacitance Csg and the drain-gate capacitance Cdg.

Comparing a and b in FIG. 1, Ceb is the capacitance of an M junction, whereas Csg is mainly a P+, n- junction.

Therefore, if the dimensions of each region are the same, Csg < Ce
It becomes b.

Next, when comparing the collector-base junction of IIL and the drain-gate junction of 5ITL, the latter junction area is much smaller.

Therefore, Cdg<Ccb.

Comparing basic gate structures with similar overall dimensions,
The total capacity of 5ITL is about 1/10 of the total capacity of IIL, and the PD product in the low current region is proportional to this capacity and is 0.01 to
0.001 PJ (Bujour) is possible.

In this way, 5ITL is a new bipolar type integrated circuit technology that surpasses the MO8FET type high-density and high-integration technology, and can be expected to exceed the above-mentioned IIL in terms of performance.

The present invention aims to improve a semiconductor integrated circuit device made with the above-mentioned 5ITL structure, particularly to improve frequency characteristics.
Specifically, the frequency response of the gate is improved by clamping the space between the fourth region 14, which becomes the gate region, and the first region 12, which becomes the channel, with a Schottky barrier diode (hereinafter referred to as SBD). It is an attempt to achieve a goal.

FIGS. 3a and 3b are a sectional view and a plan view of a semiconductor integrated circuit device having a 5ITL configuration, showing an embodiment of the present invention.

In the figure, 16 is an insulating film such as SiO2 formed on a predetermined portion of the main surface 12a, 17D is a drain metal electrode, and 1
7G is a gate metal electrode, 17I is an injector metal electrode, and each metal electrode is a corresponding external electrode D#Gs
Is, and especially the gate metal electrode 17G
straddles the fourth region 14 and the first region 12, the fourth region 14 forms an ohmic contact region 18b, and the first region
The region 12 is formed to form a Schottky barrier region 18a.

Note that the ohmic contact region 18b is also formed in other regions, such as the fifth region 15, but is not shown.

Further, the Schottky barrier region 18a is shown in an enlarged scale especially for the convenience of explaining the present invention in detail.

The normally-off type N-channel SIT, which constitutes the basic gate of the 5ITL, is pinched on with the gate voltage O as described above, and as the gate bias is applied in the forward direction, the depletion of the first region 12, which becomes the channel, decreases. The layer C is reduced, and at the same time the potential barrier is lower than 9, and the second layer becomes the source.
A current flows from the region 11 to the third region 13 which becomes the drain region.

However, when a positive potential is applied to the fourth region 14 which becomes the gate region, the space between the fourth region 14 and the first region 12 becomes forward biased, and the first region which becomes the channel becomes slightly biased.
Holes are injected into the region 12.

In order to pinch-on again from this state, the fourth area 1
When the positive potential of 4 is removed, a depletion layer expands within the first region 12, but the holes injected into the first region 12 slow down the expansion speed of the depletion layer and reduce the potential barrier. inhibits the rise.

That is, as the holes disappear, the depletion layer expands within the first region 12, the potential barrier rises, and the channel is pinched on.

Since the electron concentration in the first region 12 is low, the lifetime of holes is long.

The present invention aims to further shorten the switching-off time from on to off by further reducing the amount of holes injected into the first region 12 as described above. , as shown in FIG. 3, is to clamp the space between the fourth region 14 and the first region 12 with an SBD.

The 5BDO forward voltage drop is 0.3 to 0.51, and the fourth region 14 and the first region 12 in the on state are 5BDO
No voltage is applied higher than the forward voltage drop, and the voltage between the fourth region 14 and the first region 12 is clamped by the SBD, so holes are not injected into the first region 12. Compared to the conventional 5ITL in which the injection is performed through a PN junction, the amount can be kept to the minimum necessary to turn on the SIT.

Therefore, the switching time is shortened during the off-state transition from the on-state to the off-state, and the operating frequency of 5fTb can be improved.

Note that the forward voltage drop of the SBD is
Before attaching 7G to the main surface 12a on the first region 12 that becomes the SBD region 18a, N-type atoms are ion-implanted into the fourth region 12 at a predetermined depth from the main surface 12a to form a certain range. It can be adjusted with.

In the present invention, the above-mentioned 2.
The electrostatic dielectric transistor logic semiconductor integrated circuit device is formed over two regions, and has a Schottky barrier with the first region 12 and a metal layer making ohmic contact with the fourth region. It has excellent effects such as extremely small delay time product and rapid high frequency response.

[Brief explanation of the drawing]

Figure 1a is an IIL, Figure 1 is a cross-sectional view of a semiconductor integrated circuit configuration showing the operating principle of a conventional 5ITL, and Figure 2 is a 5ITL.
FIGS. 3A and 3B are a diagram showing the principle of operation showing ON, ON operation, and threshold voltage of the L basic gate. FIGS. 3A and 3B are a sectional view and a plan view showing an embodiment of the present invention. The same reference numerals in the figures indicate the same or corresponding parts. In the figure, 11... second area, 12...
°゛First area, 13...Third area, 14...
...Fourth area %15...Fifth area, 1
8a...SBD area, 17G...metal electrode, 18b...ohmic contact area.

Claims (1)

[Claims] 1. The first region of the semiconductor substrate is composed of a first region of the first conductivity type, and a second region of the first conductivity type that is adjacent to the first region and has a higher impurity concentration than the fourth region. within the area,
a third region of a fourth conductivity type formed including the main surface and having a higher impurity concentration than the first region, including the main surface within the first region and surrounding the third region; a fourth region of a second conductivity type formed deeper than the third region; and a second conductivity region including a main surface thereof within the first region and separated from the fourth region. a fifth region of the mold, said fourth region;
The first region and the fourth region are formed straddling the main surface on adjacent portions, and the first region and the fourth region form a Schottky barrier. is a static induction type transistor logic semiconductor integrated circuit device having a metal layer forming an ohmic contact.