JPS5840978U - back channel receiver - Google Patents
back channel receiverInfo
- Publication number
- JPS5840978U JPS5840978U JP13418781U JP13418781U JPS5840978U JP S5840978 U JPS5840978 U JP S5840978U JP 13418781 U JP13418781 U JP 13418781U JP 13418781 U JP13418781 U JP 13418781U JP S5840978 U JPS5840978 U JP S5840978U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- tuner
- processing circuit
- back channel
- recorded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案にかかる裏チャンネル受信装置を示すブロ
ック図である。
１・・・・・・アンテナ、２・！・・・・端子板、３・
・・・・・第１のチューナ、４．１２・・・・・・選局
スイッチ、５・・・・・・第１の選局回路、６・・・・
・・第１の中間周波処理回路、７．１５・・・・・・音
声処理回路、８・・・・・・拡声装置、９゜１６・・・
・・・映像信号処理回路、１０・・・・・・ディスプレ
イ装置、１１・・・・・・第２のチューナ、１３・・・
・・・第２の選局回路、１４・・・・・・第２の中間周
波処理回路、１７．２１・・・・・・出力端子。The drawing is a block diagram illustrating a back channel receiving device according to the present invention. 1...Antenna, 2...! ...Terminal board, 3.
...First tuner, 4.12...Tuning selection switch, 5...First tuning circuit, 6...
...First intermediate frequency processing circuit, 7.15... Audio processing circuit, 8... Public address system, 9°16...
...Video signal processing circuit, 10...Display device, 11...Second tuner, 13...
...Second tuning circuit, 14...Second intermediate frequency processing circuit, 17.21...Output terminal.
Claims (1)
、アンテナ信号を受信する第１、第２のチューナと、第
１のチューナを駆動する第１の選局回路と、第１のチュ
ーナで受信した信号を処理してディスプレイ装置あるい
は拡声装置に導く第１の信号処理回路と、第２のチュー
ナを駆動する第２の選局回路と、第２のチューナで受信
した信号を処理して出力端子に導く第２の信号処理回路
とを具備［７、前記第２のチューナで受信した信号を記
録し、かつ、この記録中の信号を前記第２の信号処理回
路の出力端子よりモニター可能にしたことを特徴とする
裏チャンネル受信装置。A receiving device having a function of recording an antenna signal includes first and second tuners that receive the antenna signal, a first tuning circuit that drives the first tuner, and a signal received by the first tuner. a first signal processing circuit that processes the signal and guides it to a display device or a public address device; a second tuning circuit that drives a second tuner; and a second signal processing circuit that processes the signal received by the second tuner and guides it to an output terminal. [7. The present invention is characterized in that the signal received by the second tuner is recorded, and the signal being recorded can be monitored from the output terminal of the second signal processing circuit. back channel receiving device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13418781U JPS5840978U (en) | 1981-09-11 | 1981-09-11 | back channel receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13418781U JPS5840978U (en) | 1981-09-11 | 1981-09-11 | back channel receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5840978U true JPS5840978U (en) | 1983-03-17 |
Family
ID=29927620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13418781U Pending JPS5840978U (en) | 1981-09-11 | 1981-09-11 | back channel receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840978U (en) |
-
1981
- 1981-09-11 JP JP13418781U patent/JPS5840978U/en active Pending
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