JPS5840846B2 - AGC amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AGC amplifier circuit that suppresses level fluctuations in an output signal when the input signal level fluctuates, and particularly relates to an AGC amplifier circuit that suppresses fluctuations in the level of an output signal when the input signal level fluctuates. The present invention relates to methods for improving temperature characteristics.

The compression ratio here refers to the ratio of the input change rate expressed in dB (logarithm) to the output change rate expressed in dB (logarithm).

There are various types of AGC amplifier circuits used in various transmission devices, but among them, the AGC amplifier circuit that utilizes the forward resistance characteristic of a special O diode in the micro current region is one of the circuits. It is widely used because of its relatively simple configuration.

FIG. 1 is a diagram showing a conventional AGC amplifier circuit that utilizes the forward resistance characteristic of the above diode in the micro current region.

Input voltage EIN applied to input terminals T and G is input to amplifier 1 via series resistor R1.

The input voltage EIN input to this amplifier 1 is amplified and
The output voltage EOUT is output from the output terminal T2.

From this output voltage EoUT4, only its positive side voltage is taken out by the rectifier circuit 2, passes through the low-pass filter 3, and is inputted to the non-inverting input terminal of the first operational amplifier 4.

A resistor R2 is connected between the inverting input terminal and the output terminal of the first operational amplifier 4, and a resistor R3 is connected between the inverting input terminal and the ground.

Therefore, the first operational amplifier 4 operates as a non-inverting amplifier.

Therefore, the voltage that is input to the non-inverting input terminal of the first operational amplifier 4 and has passed through the low-pass filter 3 is:
After being amplified according to the amplification factor determined by resistors R2 and R3, it is output from the output terminal as a positive voltage +E1.

This positive voltage +E1 is applied to the first gain adjustment diode C
It is applied to the anode pole of D1 and is also input to the inverting input terminal of the second operational amplifier 5 via the resistor R4.

A resistor R is connected between the inverting input terminal of the second operational amplifier 5.
A resistor R5 with a value equal to 4 is connected, and
Its non-inverting input terminal is grounded.

Therefore, the second operational amplifier 5 operates as an inverting amplifier with an amplification factor of 1.

Therefore, the inverting input terminal (
The input positive voltage 1E1 is applied to the second operational amplifier 5.
It is output from the output terminal as a negative voltage -El.

This negative voltage -El is applied to the cathode of the second gain adjustment diode CD2.

The anode pole button of the second gain adjustment diode CD2 and the cathode pole of the first gain adjustment diode CD1 are connected to the connection point between the series resistor R1 and the amplifier 1.

Therefore, the first and second gain adjustment diodes CD1 and CD2 are connected to the first and second gain adjusting diodes CD1 and CD2, respectively.
The operational amplifiers 4 and 5 generate a forward bias voltage El
, -El are applied.

That is, the first and second gain adjustment diodes CD1.
A forward bias current flows through the CD20.

The magnitude of the resistance value is inversely proportional to the magnitude of the forward bias current value.

Therefore, if the level of the input voltage EIN applied to the series resistor R14 is initially a constant level Aa as shown in FIG. Output.

Therefore, the voltage 1E 1 is output from the first and second operational amplifiers 4 and 5, respectively.

-El also becomes a constant value, and the first and second gain adjustment diodes CD1. A forward bias current flows through CD2.

As a result, the first and second gain adjustment diodes CD1.
CD2 acts as a parallel combined resistance.

That is, the input voltage EIN is generated by the series resistor R1 and the first and second gain adjustment diodes CD, which act as resistors.
CD2 and input to the amplifier 11, and as a result, the output voltage EOUT is output from the amplifier 1.

The level of the output voltage EOUT at this time is shown in Figure 3.Ab
shall be.

1. Suppose that the level of input voltage EIN is at time T as shown in FIG. 3a.

If Ba increases in , the level of the output voltage EOUT also increases accordingly.

Therefore, the level of the voltage output from the first and second operational amplifiers 4 and 5 also increases.

Therefore, the first and second gain adjustment diodes CD1. C
The forward bias current applied to D2 also increases.

First and second gain adjustment diodes CD1. CD20
As the applied forward bias current increases, its resistance value decreases.

That is, the resistance value of the first and second gain adjustment diodes CD1°CD2 acting as resistances is equal to the input voltage EI.
When the level of N increases, the output voltage is decreased to suppress the decrease in the level of E OUT.

Similarly, if the input voltage EIN decreases (in this case, the first
, second gain adjustment diode CD0. The resistance value of CD2 increases in a direction that suppresses a decrease in the level of output voltage EOUT.

Therefore, even if the level of the input voltage EIN fluctuates, the level fluctuation of the output voltage EOUT is suppressed.

If the fluctuation level of the output voltage E OUT at this time is Bb in Figure 3, then the compression ratio, that is, the output change rate Ab±B
The ratio between b and the input change rate A a + B a expressed in dB (to Ab Aa number) is expressed as 20g9μ/A a + B a log.

The value of the compression ratio at a in the above-mentioned conventional circuit is about 1/10, and this value cannot be said to be a good value.

Also, the first and second gain adjustment diodes CD1. used in the above circuit. Since the diodes built into CD2$- and rectifier circuit 2 have temperature-dependent characteristics,
There is a drawback that the level of the output voltage EOUT changes due to temperature changes.

For example, if the temperature changes by 50°C, the output voltage EOUT
The level changes by about 2 dB.

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to add a few components to the conventional circuit (which has a larger compression ratio, and further reduces the output voltage due to the temperature-dependent characteristics of the diode). An object of the present invention is to provide an AGC amplification circuit with little level fluctuation.

An embodiment of the AGC amplifier circuit according to the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

Note that parts that are the same as those in the circuit of FIG. 1 are given the same reference numerals as those in FIG. 1, and explanations of those parts will be omitted.

FIG. 2 (The first difference in the configuration from the circuit shown in FIG. 1 is that the output terminal of the first operational amplifier 4 and the inverting input of the second operational amplifier 5 A third operational amplifier 6 is provided between the resistor R4 connected to the terminal.

A resistor R6 is connected between the inverting input terminal of the third operational amplifier 60 and the output terminal of the first operational amplifier 4.

Also, between the inverting input terminal and the output terminal of the third operational amplifier 6, there is a resistor R7, and one or two (two in the circuit example of FIG. 2) diodes CD3. CD, is connected in series with its cathode toward the output terminal of the third operational amplifier 6.
This is connected.

Furthermore, a diode CD is connected in parallel with the diode CD3 DEG CD so that its anode pole is connected to the output terminal of the third operational amplifier 6.

The non-inverting input terminal of the third operational amplifier 6 is grounded via a resistor R8 and connected to a terminal T3G to which a positive bias voltage EB is applied via a resistor R0.

Therefore, this third operational amplifier 6 operates as a differential amplifier.

The circuit shown in FIG. 2 is different from the circuit shown in FIG. 1 in that the first and second gain adjustment diodes C
D1. The direction of the anode pole button and the cathode pole of CD2 is opposite.

That is, the cando pole of the first gain adjustment diode CD1 is connected to the output terminal of the third operational amplifier 6, and the anode of the second gain adjustment diode CD2 is connected to the second operational amplifier 6.
is connected to the output terminal of the operational amplifier 5.

The circuit configured as described above operates as follows.

Now, if a positive bias is not applied to the non-inverting input terminal of the third operational amplifier via the resistor R9, the third operational amplifier 6 operates as a mere inverting amplifier.

At this time, if the amplification factor is 1, which is represented by the ratio of the resistor R6 and the resistor R7, the third operational amplifier 6 inverts the positive voltage +E1 input to its inverting input terminal and outputs a voltage of -E1. .

In other words, the non-inverting input terminal of the third operational amplifier 6 (when the positive bias voltage +EB is not applied via the resistor R9, the circuit showing one embodiment of the present invention shown in FIG. 2 is the same as that shown in FIG. 1). This circuit has the same effect as the conventional circuit shown in FIG.

Next, when a positive bias EB is applied to the non-inverting terminal of the third operational amplifier 6 via the resistor R0, the absolute value of the output voltage level of the third operational amplifier 6 is compared to that before applying the bias. and decrease.

Since the absolute value of the output voltage level decreases, the first and second gain adjustment diodes CD1°C
The forward bias current of D2 decreases compared to the case where positive bias EB is not applied to the non-inverting input terminal of the third operational amplifier 6 via the resistor R0, and the resistance value increases accordingly.

Therefore, the level of the output voltage EOUT from the amplifier 1 is, as shown in Fig. 3C, the level Ab before applying the positive bias EB, plus the increase AC when the positive bias EB is applied. It takes shape.

The fluctuation level Bb of the output voltage in this case is the same level.

Therefore, the compression ratio S in this case is approximately Ab
Soil Ac is improved twice.

Specifically, the compression ratio b is variable between 1/10 and 1/Loot.

Also, due to temperature changes, the first and second gain adjustment diodes CD1. If the voltage drop when pressing CD2 changes,
Along with this, a diode CD3. The voltage drop due to CD4 also varies.

The first and second gain adjustment diodes CD1. CD
The cathode pole of 2 is directly or indirectly connected to a diode CD.
4 cathode poles (Since these are connected, the voltage drop due to the above temperature change cancels each other out.

Similarly, the diodes built into the rectifier circuit 2 cancel out the Q diode CD3.

Therefore, output level fluctuations due to temperature changes can be significantly reduced.

For example, the output level fluctuation is 0.2 for a temperature change of 50°C.
dB or less.

The diode CD5 is provided to prevent the resistance of the feedback circuit from increasing when the inverting input voltage of the third operational amplifier 6 becomes lower than the non-inverting input voltage.

Also, depending on the circuit system of rectifier circuit 2, diode CD3
I can laugh.

Further, in this embodiment, a positive bias is applied to the non-inverting terminal of the third operational amplifier 6, but the same operation can be achieved even if a negative bias is applied to the inverting terminal.

As explained above, according to the present invention, AGC using the forward resistance characteristic in the micro current region O of the diode
An operational amplifier is used as a means for applying DC bias to the diode in the circuit, and a DC bias is externally applied to the non-inverting input terminal or inverting terminal of this operational amplifier, and the feedback circuit of the operational amplifier has the same characteristics as the diode. Since the diodes are inserted with opposite polarities, it is possible to provide an AGC amplifier circuit which has a high compression ratio and has little variation in output level due to the temperature dependent characteristics of the diode.

[Brief explanation of drawings]

FIG. 1 shows a conventional AGC amplifier circuit, FIG. 2 shows an embodiment of the present invention, and FIGS. 3a and 3b show a conventional AGC amplifier circuit.
Figure 3 showing voltage levels for explaining the C amplifier circuit.
Figures a-c are diagrams showing voltage levels for explaining one embodiment of the present invention. 1... Amplifier, 2... Rectifier circuit, 3.
...Low pass filter, 4...First operational amplifier, 6...Second operational amplifier, 6...
...Third operational amplifier, CDI...First gain adjustment diode, CD2...Second gain adjustment diode, R1 to R0...Resistance, E
IN...Input voltage, EOUT...Output voltage, +E1゜E, , +EB...Voltage, C
D3 to CD5...Diode.

Claims (1)

[Claims] 1. In the AGC amplifier circuit O which utilizes the forward resistance characteristic of the diode in the micro current region O, an operational amplifier is used as a means to apply a DC bias to the diode, and the non-inverting or inverting input terminal of this operational amplifier is connected from the outside. An AGC amplifier circuit characterized in that a DC bias is applied and a diode having the same characteristics as the diode is inserted in the feedback circuit of the operational amplifier with opposite polarity.