JPS5840668A - Register selecting system - Google Patents

Abstract

PURPOSE:To decrease the number of bits of a microinstruction, and to reduce the capacity of a control storage, by using a register address register having a counting function, and executing direct designation of the register. CONSTITUTION:A register address register RAR 13 is set by a microinstruction from a result data bus ZB. The contents of the RAR 13 are added or subtracted by ''1'' by a counter 15, and after that, its updated value is fed back and is set to the RAR13. The contents set to the RAR13 are decoded by a source decoder 18, and a transfer register to the operating unit is selected. Also, the contents of the RAR 13 are latched by a delay RAR (DRAR) 14 after a half machine cycle, are decoded by a destination decoder 17, and the transfer register from the operating unit is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a register selection method, and in particular to a register selection method using indirect specification in which a large number of registers are selected by a miter award instruction with a short bit length.

In a microprogram-controlled central processing unit, the control logic is stored centrally in the control memory in the form of a programmable program, and it is relatively easy to change and modify the logic, giving eight-dounia flexibility. It has several advantages, such as:

Vertical! A microinstruction consists of an operation code and an operation operand field, and the operation operand field specifies the input to the arithmetic circuit and the destination of the result.

The first WJ is a block diagram of a central processing unit under Mitalo program control.

In Fig. 1, lti operation unit (MULU), 2#
Ca0U>, 3 is a unit that controls the sequence of micro programs (enin) that controls the i-storage device
IIQ), the number is the channel control unit (OH).

In each of these units IN4, a large number of registers selected by the miteropugadalam are distributed 9, and the contents of the selected registers are transferred between each unit 2 to 4 and the arithmetic unit 1 via a data bus. will be transferred.

In FIG. 1, an arithmetic unit 1 has a local storage (hereinafter referred to as L8) 5 and a register corresponding to L8! ¥7 is placed and the L85ri data bus (XB
) δ to the arithmetic unit 6, while the register r#7
is input to the arithmetic unit 6 through the data bus (YB) 9,
The result of the operation passes through the data AX (ZB) 11 and is stored in the register of each unit 1-4. Note that the registers existing in units 2 to 4 other than arithmetic unit 1 are as follows:
Through the common data bus IB) 10, the arithmetic unit 1
data bus (YB) 9. When selecting a register, you can directly specify it using a microinstruction (conventionally), for each register ■#)! ! The selected identification code is selected by specifying it in the operation operand field of the i ita cI instruction. therefore,! l
The field length for specifying the 1ll-code must provide the number of register selection bits necessary to distinguish all registers.For example, if there are 200 registers in the central processing unit, , to select these requires 8 bits by 2”-256,
If you specify the X, Y, and Z registers independently to perform Y-Z(7) operation, you will need 3 times 8 bits or 24 bits. To reduce the number of microinstruction bits required,
When performing the operation x + y - z, the registers for x2:z should be the same, or the registers for Y and 2 should be the same. A method is used in which only registers are selected in advance.

However, even with these methods, the number of bits required for microinstruction register selection still occupies a large proportion, so the capacity of the control storage device for storing microinstructions is large, resulting in high costs. I'm inviting you.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of microinstruction bits required for register selection, shorten the machine cycle, and reduce the number of microinstruction bits required for register selection without changing the number of microinstruction bits. The object of the present invention is to provide a register selection method that can increase the number of registers.

The register selection method of the present invention is that a data processing device that performs miml (by a micro program) is provided with a register address register that indirectly specifies a register to be used for an operation, and a shifter When a micro program sets an arbitrary value for , or initializes it at the start of instruction execution, and aIRs the register corresponding to that value, the register
It is characterized by counting down or counting down the value of the address register.
4 Below, the operating principle and embodiments of the present invention will be briefly explained with reference to the drawings.

In the central processing unit shown in Fig. 111, among the registers selected by the microprocessor and program, the registers that are used frequently and need to be selected at high speed are concentrated in the arithmetic unit 1, and other registers are In units 2 to 4, the registers that require high speed selection are 2 to 31 WN degrees, and most registers do not require high speed selection.

In the present invention, when register selection is performed by a microprogram, a register in the arithmetic unit 1 that requires high-speed selection, that is, one register (L8) that is read out through the degoter bus (xn)a, and a data bus (
YfS) For the register group of the arithmetic unit l that is read through
! lr-specified, requires high-speed selection & unit 2
The registers in ~4, that is, the ?ft data bus C
EB')10') For the registers that are extended by the arm, indirect specification is performed using a mital instruction. In this way, in the present invention, registers that are used frequently and would degrade the performance of the processing device if not directly specified by microinstructions are specified directly by microinstructions. Registers that are referenced only when an event occurs and do not require high-speed selection are indirectly specified using microinstructions. Furthermore, the register address register (hereinafter referred to as RAB) for indirect specification is provided with an AI function for initial setting at the start of an instruction, an arbitrary value setting by a microinstruction, and a count function. To speed up specification and enable register selection to be used only in specific instructions.

FIG. 112(a) is an explanatory diagram of a microinstruction register selection code showing an embodiment of the present invention.

The Mytaro command 12 is divided into fields F, gX, A, BY, ..., respectively. Fiy command (instructions for byte processing, word processing, transfer processing, etc.), sx specifies the source register selection of X @ of the arithmetic unit, A specifies the summary of the operation, BY specifies the source of Ya of the arithmetic unit - Specify register and destination register selection.

The 8x field is directly specified by a microinstruction as before, and the 8Y field is indirectly specified by removing the register group 7 of the arithmetic unit 1.

If there are, for example, 200 registers in the central processing unit, in the conventional method both 8X and 8Yy yields would be 8 bits long, but in Fig.
Since only register 1 is specified directly, the length of both 5Xt8Y fields can be 4 bits. Now, flowerpot unit 1
The register names of A, B, 0. ...then Regis #
A, B.

C2... and the #R placed for each unit 2 to 4.
and transfer data bus (SCU) for each unit 2 to 4.
B, 8NQB, 0RB) has its own 4-pit code in tk with the Mitaro instruction directly, and is indirectly specified by the registers FiR of other units 2 to 4. It has an independent code, and the number of pins can be determined arbitrarily.

@21m (&) SX field contains each register of arithmetic unit 1, B, 0 . ..., while the 8Y field contains the codes for each register ', B, 0°, etc. of calculation unit 1, and 81R and 81R of other units 2~. Cord Misaki, who was given an IA, enters the bus.

FIG. 2(b) shows an example of the code of the 1Y field number bit, where each register of the arithmetic unit l, B, .
In 1011, the RAR of channel 41p unit 4 and the data bus (CIIB) for transfer are connected to "1100~".
1101 has the RAR and transfer data bus C3CUB of the memory turtle 1" Misaki unit 2, and also "1110~"
1111 is a sequence: Total unit 3 RA, R
and a transfer data bus (SEQB), respectively. Therefore, registers A, B are created by the micro program.

..., as well as channel BAR (HR
AIIL), one control RAR (SRAR), sequence control RAR (QRAR), etc. are arbitrarily specified to specify it+r, and each unit 2 to 4 transfer data bus (OHE, 5OUB, 5EQB) is specified. do. O
RB, 5CUB, and 8EQB designate the transfer of the register of each unit 2 to 4 specified by RAR to the arithmetic unit)l, or the transfer from the arithmetic unit 1 to the register of each unit 2 to 4.

FIG. 3(b) is a block diagram of an RAR and its attached j4 circuit showing an embodiment of the present invention, and a diagram explaining the bit contents of the RAR.

RAR13Fi is installed independently in each unit 2 to 4, and each unit B is independently instructed by a microinstruction. For RAR13, any value can be saved from the result data bus (ZB) 11 using a microinstruction)
In addition, initial values can be set when executing instructions. In addition, the contents of RAR13 are the contents of counter 1.
After being incremented by 1 or minus 1 by δ, the updated value is field-puttered and set in BAR13. It is composed of a-th Kasumi (as shown in bz, jlAR13 is, for example, b-pit), and controls 1 bit.・
Pi) (0〒L) and Yo Pissi register code (00
It consists of (1.). Control bit (0〒L)
is used to control the suppression/enablement of counting and select the register code (0(14.)Fi 16 registers. The contents set in the RAR13 are decoded by the source decoder 18 and calculated. The transfer register to unit 1 is selected.t+, the contents of RAR13 are delayed RAR (DRAR) in half a machine cycle.
Lunch was held on the 14th, thereby making the Destiny
It is decoded by the decoder 17 and the transfer register from the program unit 1 is selected.

The counter 15 adds 1 to the current value, and when there is an indirect designation using RAR, the counted spear is fed back to the RM R13 and set.

The initializing means 16 initializes the RAR1 at the start of the instruction.
3 is initialized to "0" or, in the case of a special instruction, to a certain constant.

FIG. 4 is an explanatory diagram of the operation of the RAR shown in FIG. 3, and FIG. 5 is a Thai chart of the operation of the delay RAR. All registers in each unit 2 to 4 are assigned a 4-bit code for each unit, and this code is
It is selected and designated when it is sected to R13. Therefore, there is a code that repeats 11 times in the registers of different units! + Assigned - There is no problem.

Now, as shown in Figure 4, the channel
If there are 909 registers from ORI to CH in the file, and they are assigned oooo"-;xooo", if "1000" is specified in the 8Y field of the microinstruction, the ,channel,
RAR (nuAR) 13 is selected ◎ In this case, the initialization means 16 is selected during the preparation period before executing the instruction.
For example, if "0000" is initialized, the register (CHl) is specified, and then 1001 is specified in the 8Y field of the microinstruction, the channel data bus ( OHB)
101 is selected and the contents of the register (CHI) become 11.
It is transferred to one arithmetic unit 1 through the data bus (1EB). By the way, the way to use registers is as follows:
There are many microprograms that reserve and use registers in the circuit unit in the order of al, cH2tcn3, etc., so in this case, add 1 to the previous code and use the next specified register. It becomes a hood.

In the Hibanzu, the first code “oooo” is selected,
At the same time as the contents of register (CHI) are transferred, II
Since the contents of RAR13 are updated to candy with +1 added due to its own weight, the register corresponding to “OOO1” (OH
2) is specified. When "1001" is specified by the microinstruction and the contents of the register (CHl2) are transferred to the arithmetic unit 1, the contents of HRARl3 are immediately updated to V''0010, which is +1, and the contents of the register (OH3) are transferred.
In this way, the registers are stored in numerical order and calculations are performed at high speed.

Further, if it is in one of the programs, an arbitrary value can be set in the HRAR 13 through the arithmetic result data bus (zB) 11 by the micro program. For example,”
When 0111 is set, the register (OHM) corresponding to that code is selected, and the contents of register (CH8) are transferred to operation unit (CH8) 1 by a transfer instruction by a microinstruction. When specifying OH9), if you set the control pitch (0'!'L) of HRARl3 to 1 in advance, "Ol l l" will be automatically incremented by 1 and will become "1000" or HRA凰13. is set to ・t, then the register (O
When specifying H9) again, it is necessary to
If the control bit (OT L) of L13 is set to "0," the previous value will be sent to HRAR13 as it is without being incremented.Also, if a register other than register (OH9) is specified next, For the turtle, just select any value to HRAR13 through the data bus (ZB) 11 using the miter p program.

Furthermore, when the control bit (CTL) of km R13 is "l", the counter 1δ is decremented by 1, and O
They can also be specified in the order of H9,0)18, OH7... Additionally, the control bit (OTL)
is increased to 2 bits, and when ko is 01, plus 1. ”10
Minus 1. When it is '00, it can also be changed to - for that t. 0 In this way, the 85R has a counting function, so the second and subsequent microinstructions will be the channel data.
It is only necessary to issue the instructions of the data path (OII B) continuously, which makes the micro program extremely simple. In addition, in FIG. 4, the channel control unit 4
I explained about this, but it is exactly the same even if you coo at the pond's Unisshi 2 #3. In addition, although Fig. 4 shows the case where the number of registers in unit 4 is 9@, if there are 16 or more registers, it exceeds the range that can be specified with 4 bits.
It is only necessary to increase the number of bits, and there is no need to match the number of bits of the microinstruction with the number of bits of the microinstruction. power 2
Therefore, even if the number of registers in the unit is increased or decreased, Vi can be made independent of the bit length of the microinstruction by simply increasing or decreasing the number of RAR bits.

As shown in FIG. 6 (&) (b), when a microinstruction is executed, the contents of the source (&OE) register are read out in half of one machine cycle (IMC) and 1t7R.
Written to the destination (DEN) register in the cow cycle. Therefore, the selection of the destination register in the previous cycle and the source register iv (in the next cycle) are mt at the time fi++. As shown in FIG. 5 (6), the value set to RARkm is “00017.”0010”, the 51st
．． As shown in j(d), “QOOl”′, “0010” is set in I)lζAn after a half cycle delay,
After another half cycle, the counter 15 increments the value by 1 and updates the value of RATL.

FIG. 6 is a 70-chart of a micro program showing an embodiment of the present invention, and FIG. 7 is a time chart of the micro program shown in FIG.

Figure 6 (A) shows a microinstruction sequence that indirectly specifies the channel unit during execution, and Figure 6 (3) shows a microinstruction sequence that indirectly specifies the storage control unit at the beginning of execution. There is.

In Figure 6, the step (υ to nRAH')K
? Set 4 to 4, and in step ■ transfer the register specified by HRAR-4 to the local storage LS,
In step ■, the contents of H) LAR are converted to CB in step ■.
Since the source designation Lfc has been counted up from number 9 to 5, the register designated by HRAR-5 is transferred to the local storage L8. Step (gradient, (■), in the same way,
The contents of the register indicated by 7 are transferred to local storage L8.

FIG. 7 (→ indicates the timing at which the contents of the HRA box in FIG. 6 (4) described above are updated, and the contents of the HRA box are updated in each machine cycle of steps 2.3 and 4.5. 4.5 and 6.7 respectively. In this case, the source
Since this is a register selection, the contents of DHILAR are not used.

Next, Figure 6(2) shows the micro-product data from the start of the instruction, and it is initialized to 8, as in 11RARFi of the storage control unit (80U) (Figure 7). Ru. In step (1), data is transferred from the local streakage L8 to the register indicated by DSRA''-8, and the count is increased from 8RARFi8 to 9.

Therefore, in step (2), the contents of the register specified by 18fLAR-9 are -.

Transferred to Cal Susilage L8, S RA RFil
It is counted up to o.

As shown in the 7th WJ (@), D8RAR&: is X? 7
8 is set in the latter cycle of step (1), and 9 is set in the latter cycle of step (2), but this DII
RAH 9 is not used because it specifies the source register.

In addition,#! Step ■ and Step (Execution of other microinstructions in Figure 6) and Step (Execution of other microinstructions are performed in Figure 6, and no microinstructions are sold to this SL, so Figure 7) (
As shown in O), that one machine cycle is uncontrolled and holds the same value.

In this way, the continuous machine
Fast control is possible if registers are used in numerical order within the z-set.

Building 6 [@, WJ initial value is 8, but depending on the type of instruction, the initial register number used by that instruction is 11.
! Of course you can do that.
Since the required W'Ik register is selected for the instruction from the start of the instruction without setting the constant value to 8mR in the microprogram, there is no performance deterioration due to the RAR setting. Also, each time you select a register using RAR,
Since the contents of RAR count up, one RA
If register numbers are added in the processing order to the R settings, registers can be selected consecutively, which allows RAR
This makes it easier to prevent performance degradation due to constant settings.

By using the above method, it is now possible to indirectly specify registers that were previously specified directly by microinstructions.
, the number of registers that must be directly specified with microinstructions is greatly reduced.

In the embodiment, the 8Y field of the Mitaro instruction is number bit, and the number of registers tf that can be specified is 16 if it is directly specified with one microinstruction, but 4Y = 7).
f) RA By indirectly specifying with R, the number of registers that can be selected with RAR becomes 64 (16 x 4 - nits). If 80 registers t* are specified, 7 bits are required, but in the present invention, #'1R
Since it can be specified using 4 bits using AR, the reduction is 3 bits.

As explained above, according to the present invention, indirect specification of registers is performed using RAR having a counting function.
It is possible to reduce the number of microinstruction bits, increasing the control memory space by reducing the number of bits in the microinstruction. When increasing the number of registers, isolation is possible without changing the number of microinstructions. Furthermore, since the registers specified by the microinstruction are drastically reduced, the decoding by the BomR can be completed in advance, and the simplification of decoding makes it possible to make the machine Suita-kei 111m.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a central processing unit for Mytalo-Proguchi five control, Fig. 2 is a VN diagram of a microinstruction register selection code showing an embodiment of the present invention, and Fig. A block diagram of RAR and its attached circuits showing an embodiment of the invention, and a diagram explaining the bit contents of RAH, FIG. 4 is the R of FIG.
An explanatory diagram of AIL operation, Fig. 6 is an operation time chart of delay RAH, Fig. 6 is a flowchart of a micro busegram showing an embodiment of the present invention, and Fig. 7 is an execution operation time of the micro program in Fig. 6.・It is a chart. 1: Arithmetic unit, 2: Storage control unit, 3 Nisiken control unit, 4: Channel control unit, 5: Local storage (LS), 6: 1IliF calculator,
7: register group, 8=x bus, 9+YA7. ．． 1.0=
E bus x, 11: Z bus, 12 = -r microinstruction, 13:
Register address Φ register (RAR), 14:
Delay RAR (DRAR), 16: Counter, 16:
Initializer, 17: Destination main-sequence decoder, 18: Source decoder, 101: Unit data path. Figure 1 Figure 2 (a) ] 2 Figure 3 17 18 Figure 4 Figure 5 fdl I) RARo o o () () (
)1 ``Qj-Q-! Q--'---6th
Figure ■) Figure 7

Claims (1)

[Claims] In a data processing system that is controlled by a micro program, it is equipped with a register address register IL that indirectly specifies the register used for calculations, and corresponds to the register specified for the register address register. The value to be initialized at the start of instruction execution, or - is during execution i! When the register corresponding to the set value is selected by the immediate purchase program, the above register
A register selection method characterized by counting up or down the value of an address register.