JPS5839404B2 - transistor amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor amplifier circuit, and particularly to a transistor amplifier circuit with improved voltage reduction characteristics.

FM using PLL (phase locked loop)
In a multiplex demodulation circuit or the like, each circuit block making up the circuit has different requirements for the power supply voltage.

For example, in the case of amplifier circuits and demodulation circuits, in order to have a large output dynamic, it is preferable to form a bias voltage according to the power supply voltage when the voltage is reduced.

On the other hand, changing the bias voltage in accordance with the power supply voltage when increasing the voltage increases DC current consumption and should be avoided, especially in semiconductor integrated circuits.

In addition, oscillation circuits need to be operated with a constant voltage power supply in order to obtain a stable oscillation frequency, and logic circuits such as frequency divider circuits cannot be operated with a constant voltage power supply since there is no particular requirement to increase the dynamic range. preferable.

However, in the conventional FM multiplex demodulation circuit using PLL, the above-mentioned considerations were not taken, and therefore the voltage reduction characteristics of the amplifier circuit were poor.

In this circuit, the bias voltage of the amplifier circuit is made constant to prevent an increase in DC current when increasing the voltage.
The load is connected to an unregulated power supply voltage to ensure a wide dynamic range.

For example, an oscillation circuit or the like uses a power supply that is regulated to have a constant voltage with respect to increases and decreases in the power supply voltage within a certain range.

The bias voltage of the amplifier circuit is formed by voltage dividing means from this constant voltage power source.

Therefore, the bias voltage remains constant even if the power supply voltage increases or decreases within a certain range.

In this case, the bias voltage is determined based on the standard power supply voltage.

Therefore, when using an inexpensive power supply or a device with large power fluctuations such as a car radio, etc., where the power supply voltage is lower than the standard voltage, the above bias voltage should be set for a certain range of power supply voltage. Since the voltage is set to a constant voltage, the dynamic range on the power supply voltage side becomes smaller with respect to the bias voltage, the output signal is clipped, and the distortion rate worsens.

This problem also occurs not only in amplifier circuits used in the FM multiplex demodulation circuit as described above but also in transistor amplifier circuits in which the bias voltage is made constant.

The present invention has been made to solve the above problems, and its purpose is to provide a transistor amplifier circuit with improved voltage reduction characteristics.

The basic structure of the present invention for achieving the above object is that in a transistor amplifier circuit that includes at least a bias circuit that forms a constant bias voltage with respect to increases and decreases in the power supply voltage within a certain range, the power supply voltage is amplified. Means for detecting that the voltage has fallen below a standard voltage that is a reference for determining the bias voltage of a transistor, and a bias voltage that is controlled based on the detection result and changes the bias voltage in accordance with a voltage reduction in the power supply voltage. It is characterized by comprising a correction means.

Hereinafter, the present invention will be specifically explained with reference to the drawings along with examples.

FIG. 1 is a circuit diagram of an amplifier circuit showing a basic embodiment of the present invention.

As shown in the figure, the circuit of this embodiment has the following configuration.

1 is an amplification element, which is composed of a transistor Q,
Reference numeral 2 indicates a load means, which is constituted by, for example, a resistor R3.

Reference numeral 3 denotes a bias circuit, which is composed of, for example, a Zener diode DZ and a resistor R that forms a constant bias voltage.

In this way, in a transistor amplifier circuit in which the bias of the amplifier transistor Q is made constant voltage, in order to improve the voltage reduction characteristics when the power supply voltage VOO falls below the standard voltage that is the reference for determining the bias voltage, A voltage comparison circuit 4 for detecting that the power supply voltage Vcc has become lower than the standard voltage, and a variable current sink circuit 5 for changing the bias voltage at the time of the voltage reduction according to the voltage reduction are provided.

The voltage comparator circuit 4 has a power supply voltage ■cc at one input.
Or applying a voltage that changes in proportion to this voltage Vcc,
The standard voltage or the reference voltage "REF" equivalent to this is applied to the other input to compare the two voltages, and when the power supply voltage VOO becomes below the standard voltage, the variable current sink circuit 5 is activated. Then, by passing a current in accordance with the voltage difference between the two (the positive voltage reduction component) through the resistor R2, the pressure at the bottom of the resistor is changed.

Generally, the bias voltage of an amplifier circuit maximizes the output dynamic, so the output midpoint voltage is 1/2 of the power supply voltage VOO.
The voltage value is set so that

Therefore, the amount of change in the bias voltage due to the current (2) of the resistor R2 or the current sinking circuit must be such that the output midpoint potential becomes 1/2 of the power supply voltage VCC at that time.

Note that when the power supply voltage VaC becomes higher than the standard voltage, in other words, when the voltage is increased, the current sink circuit 5 does not operate, and therefore the bias voltage is not changed.

This is to prevent the DC current consumption from increasing when the bias voltage is increased.

The above has shown the principle of the present invention, but this can be understood more concretely by referring to a specific example circuit described below.

FIG. 2 shows a general block diagram of an FM multiplex demodulation circuit using PLL.

Reference numeral 12 indicates a voltage-controlled oscillation circuit, which generates an oscillation frequency of 76 KHz.

13 to 15 are frequency dividing circuits based on the above oscillation frequency, and 38
A switching signal of KH2, 19KHz is formed.

This 38 KHz is supplied to the demodulation circuit 16 as a subcarrier for demodulation.

In addition, 19 KHz is applied to phase comparators 7 and 8, and the phase is compared with the pilot signal (19 KHz) in the composite signal. , is applied to the oscillation circuit to form an accurate 76KHz oscillation frequency, and to improve the separation between both channels, the demodulation subcarrier (38KHz) and the 38KHz in the stereo signal are applied to the demodulation subcarrier (38KHz).
The phase difference θ with the component is maintained at π/2.

Further, the output of the phase comparator 8, that is, the detection output of the pilot signal, is applied to a low-pass filter 1o, and is passed through a lamp driver 17 to perform ramp display when receiving a stereo signal.

A preamplifier section 6 amplifies the composite signal and supplies it to the phase comparators 7 and 8.

Further, this composite signal is applied to a demodulation circuit 16, where it is stereo demodulated to obtain demodulated outputs R for both left and right channels.

Among the FM multiplex demodulation circuits configured as described above, a specific example circuit is shown in FIG. 3 in which the preamplifier section 6 and the demodulation circuit 16, which require a large output dynamic range, are configured as semiconductor integrated circuits. .

In the figure, a portion 26 surrounded by a dashed-dotted line indicates a portion configured within the semiconductor integrated circuit.

Furthermore, portions 18 to 26 surrounded by broken lines indicate the main circuit blocks of this circuit.

A resistor R1, a diode (or a diode-connected transistor, the same applies hereinafter) Qa, Q4, and a Zener diode DZ connected in series between the power supply voltage terminal P6 and the ground terminal 29 constitute a constant voltage circuit 18, and the output constant voltage vR is Darlington connected transistor Ql, Q2
is outputted via an amplifier circuit 22 and a demodulator circuit 2, which will be described later.
It is used as a power source for the bias circuit 21 of No. 4 or as a power source for an oscillation circuit or the like (not shown).

The bias circuit 21 connects the constant voltage vR to a resistor R30.
and R31 to form a constant voltage bias voltage.

Note that the diode Q,0 connected in series with the resistor R30t R3□ is for forming a constant voltage for driving a constant current transistor Q1□ of an amplifier circuit, which will be described later.

Further, the above-mentioned divided voltage is outputted as a bias voltage through an emitter follower circuit including a pnp transistor Q and a resistor R32.

Reference numeral 22 indicates a preamplifier section, and this circuit has an input section including a transistor Q1□, a first-stage emitter follower circuit consisting of a resistor R34, a transistor Q12, a level shift diode Q13 connected to its emitter, and a resistor R3.
A composite signal virpt through the input terminal PIO is applied to the base of the amplification transistor Q14 through the emitter follower circuit according to the amplification transistor Q1.
The collector load of No. 4 is connected to an active load formed by a pnp transistor Q15, and is composed of transistors Q16 and Q17 forming an output circuit.

The load transistor Q15 is a multi-collector transistor, and one collector is connected to its base and also to the collector of the amplification transistor Q14.

Further, the other collector is applied to the base of the output transistor Q+a.

Since this output circuit has a constant current flowing through the transistor Q1□, the difference in current flowing through the output transistor Q16 is obtained as an amplified output signal.

This output signal is guided to the external terminal P1□ via the resistor R39, introduced again to the semiconductor integrated circuit via the coupling capacitor C5, and applied to the phase comparator (not shown).

24 is a demodulation circuit, and transistor Q24 is a common emitter type amplification transistor, to which a composite signal is applied via first-stage emitter follower circuits Q1□ and Q34 of the preamplifier section 22.

Differential pair switching transistors Q2□ and Q28 connected to the collector of transistor Q24 constitute a main switching circuit for stereo demodulation.

The transistor Q23 and the differential pair switching transistors Q25 and Q26 provided at its collector constitute a crosstalk canceling circuit, and the transistor Q
Reference numeral 23 constitutes a common base type amplification transistor, which forms a signal with a phase opposite to that of the amplification transistor Q24, and constitutes a sub-switching circuit. .

The crosstalk component in the demodulated output is canceled through Q26.

A bias voltage formed by the bias circuit 21 is applied to the base of the common base type amplification transistor Q23.
It is applied via an emitter follower circuit composed of transistor Q6 and resistor R7.

The load of this demodulation circuit 24 is composed of external resistors R5□, R52, and capacitors C1, C2.

Note that among the resistor circuits R46 to R+j provided on the emitter side of the amplification transistor Q23 j Q24, the resistor R
48 is preferably an externally adjusted resistor to perform separation control.

Further, 23 is a load resistor R5 of the demodulation circuit.

This is a current supply circuit for reducing the DC current flowing through R52 and increasing the output dynamic range, and the transistor Q2□ to which a bias voltage is applied and the pnp transistors Q18 to Q20 forming a current mirror circuit.
It is composed of

A current corresponding to the collector current of the transistor Q22 is obtained at the collector of the transistor Q19 s Q20, and this current is passed to the amplification transistor Q23 t' of the demodulation circuit.
It shall be poured into the collector of Q24.

Since only a current corresponding to the input base current flows into the collector of the amplification transistor Q23s Q24, the current supplied from the current mirror circuit flows in the opposite direction to the collector current of the amplification transistor.

Therefore, if these two currents are matched, the DC current on the collector side of the amplification transistors Q23s Q24, in other words, the DC current of the load resistors R51t and R52, can be reduced to zero, and the level due to this DC current can be reduced to zero. Since there is no loss, the dynamic range can be increased.

25 is a switching transistor Q of the demodulation circuit 24
25 to Q28, and is composed of a differential transistor Q29°Qao controlled by a 38 KHz subcarrier, a transistor Qa1 serving as an emitter constant current circuit, a resistor R51, and a collector load resistor R4g*R50.

As a power source for this circuit, a constant voltage generated by the constant voltage circuit 18 is passed through an emitter follower circuit composed of transistors Q5-Qa.

In the FM multiplex demodulation circuit configured as described above, the circuit that changes the bias voltage during voltage reduction is the circuit 20 configured by transistors Q7 and Qs.

A resistor R connected in series between the power terminal P6 and the ground terminal 20
The voltage dividing circuit 19 formed by 41R5 is for level shifting the power supply voltage vcc, and includes the transistors Q7,
applied to the emitter of Qs.

Further, the base bias voltage of the amplification transistor Q23 in the demodulation circuit 24 is applied to the bases of these transistors Q7-Qs and used as a reference voltage.

This transistor Q7. Q8 constitutes the voltage comparison means 4 described above using its base-emitter, and its collector is connected to the voltage dividing resistor R3 of the bias circuit.
o J R3□ connection point.

By connecting it to the power supply line of the drive circuit 25, it also functions as the current sink circuit 5 described above.

Said transistor Q7. Q8 operates under the condition of the following equation (1).

Here, vl is the transistor Q formed in the bias circuit.
, and Vf is the base-emitter forward voltage of each of the transistors Q6 to Q8, and these are assumed to be equal.

The above equation (1) can be transformed as shown in the following equation (2).

When the power supply voltage VOO decreases so as to satisfy equation (2), the transistors Q'y-Qs start flowing ONL and current.

By turning on this transistor Q8, the transistor Q9
The degree of conductivity increases and the current flowing through the resistor R32 of the bias circuit increases, causing the bias voltage v1 to decrease.

Further, the voltage of the power supply line of the drive circuit similarly decreases because the current from the transistor Q7 flows through the resistor R8.

In equation (2), the reference voltage (Vl-2Vf) applied to the bases of the transistors Q7-Qs changes because the bias voltage v1 changes.

Therefore, when the power supply voltage vcc is below the standard voltage, it is always stable in a state that satisfies equation (i)) (2).

Bias voltage V when the power supply voltage VOOO is reduced
1 is the output midpoint potential for a preamplifier, for example.
In other words, it is desirable to set the voltage of the output terminal P1□ when there is no signal to be 172 of the power supply voltage VOO at that time. It is also used as a power source for the drive circuit 25 that determines the base DC voltages of the switching transistors Q25 to Q28, and these are also changed in accordance with the reduction in the power supply voltage vccO.

As a result, the output dynamic range of the preamplifier and demodulator circuit at reduced voltage can satisfy the optimum conditions at that voltage, and therefore the reduced voltage characteristics can be significantly improved in proportion to conventional circuits.

Further, in the circuit of this embodiment, the transistor Q7,
By configuring the voltage comparing means and the current sinking means using Qs, the circuit can be extremely simplified.

Note that when the power supply voltage VOO is increased to be higher than the standard voltage, the voltage comparison transistors Q7-Qs are reverse biased between their bases and emitters and are turned off.
The bias voltage V1 is a constant voltage formed by the constant voltage VR, and operates to prevent an increase in DC current when the voltage is increased.

Furthermore, a constant voltage formed by dividing the constant voltage vR may be applied as a reference voltage to the bases of the voltage comparison transistors Q7 and Qs.

The present invention can be widely applied to transistor amplifier circuits.

[Brief explanation of the drawing]

FIG. 1 shows a basic embodiment circuit for explaining the present invention in detail.
FIG. 2 is a block diagram showing an example of an FM multiplex demodulation circuit using PLL, and FIG. 3 shows a concrete implementation circuit in which the present invention is applied to some of the circuits shown in FIG. 1... Amplifying element, 2... Load means, 3
...Bias circuit, 4...Voltage comparison circuit, 5...Current sink circuit, 6...Preamplifier section, 7, 8... Phase comparator, 9, 10・
...Low pass filter, 11...DC amplifier, 12...Oscillation circuit, 13-15...
...Frequency divider circuit, 16...Demodulation circuit, 17...
... Lamp driver 18 ... Constant voltage circuit,
19... Voltage divider circuit, 20... Voltage comparison, current sink circuit, 21... Bias circuit, 22
...Preamplifier, 23 ... Current supply circuit, 24 ... Demodulation circuit, 25 ... Drive circuit, 26 ... Semiconductor integrated circuit .

Claims (1)

[Claims] 1. At least a constant voltage element D for forming a constant bias voltage with respect to increases and decreases in the power supply voltage VOO within a certain range.
In a transistor amplifier circuit comprising a bias circuit 3 having a bias voltage z, a means 4 for detecting that the power supply voltage has become lower than a standard voltage used as a reference for determining the bias voltage of the amplification transistor Q, and a result of this detection. A transistor amplifier circuit comprising bias voltage correction means 5 which is controlled based on the above bias voltage and reduces the bias voltage according to a decrease in power supply voltage. 2. As the voltage detection means 20 described in claim 1, a reference voltage is connected to the base of the transistor Q7-sQ,
Applying a voltage to the emitter that varies based on the supply voltage,
This transistor Q7. Q8 ON. A transistor amplifier circuit characterized in that voltage detection is performed when the transistor is turned off. 3. Transistor Q7 according to claim 2,
A transistor amplifier circuit characterized in that a collector current of Qs is caused to flow through resistor means R8 and Ft9, and this voltage drop is used as a bias correction voltage. 4% Transistor Q as described in claim 3
8 collector with constant voltage vR divided by resistor R3osR3□
A transistor amplifier circuit characterized in that it is connected to a bias connection point that divides the voltage by.