JPS5838997B2 - Signal transmission/reception method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission/reception method for transmitting and receiving various control signals between a parent device and a terminal device by wire, which is suitable for use in a button telephone system.

2. Description of the Related Art Conventionally, there is a button telephone system as a system for transmitting and receiving various control data or control signals between a parent device and a terminal device by wire.

This button telephone system consists of multiple button telephones as terminal equipment, and these multiple button telephones receive control signals such as station line selection signals, extension selection signals, hold signals, and dialing signals, as well as call signals. It consists of a parent device that performs various controls between telephones and between central office lines and extension lines. The tail is connected by three pairs of power supply lines.

Various control data are encoded and transmitted and received between the parent device and each key telephone.

By the way, in a system such as a button telephone system, which transmits and receives various control signals or control data between a parent device and a terminal device, the problem is as follows.
This is a line configuration that connects a parent device and a terminal device.

In other words, if the number of line configurations connecting the parent device and terminal devices increases even by one pair, the terminal devices will have to be installed over a wide range,
In addition, when a large number of cables are installed, the total line length becomes enormous, and a large amount of material and construction costs are required, making the entire system expensive.

In particular, due to factors such as the recent rise in labor and material costs, and from the perspective of reducing construction costs, it is strongly desired to have as few lines as possible.

In particular, in the above-mentioned button telephone system, various research and development efforts have been focused on making the power supply line and the control signal line common as a pair of lines.

Therefore, the present invention has been made to solve such a demand, and its purpose is to transmit and receive various data signals or control signals that can connect a parent device and a terminal device with fewer line configurations. The purpose of the present invention is to provide a system in which the power supply line and the control signal line are commonly used as a pair of lines in a button telephone system, and the parent device and the button telephone are connected by a two-pair line configuration. The purpose of this invention is to provide a signal transmission and reception method that allows for

In order to achieve such objects, the signal transmission/reception system according to the present invention has a voltage level for sending power from a parent device to a terminal device, a voltage level for sending a data signal, and a voltage level for sending a data signal back from the terminal device to the parent device. Each voltage level is set at a unique voltage level, and power is sent from the parent device to the terminal device at these set voltage levels, and data signals are transmitted and received between the parent device and the terminal device in a time-sharing manner, and the data signal is expressed by a change in voltage level based on the set voltage level for data signal transmission and reply, or by a combination of binary voltage levels.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system configuration diagram showing an embodiment in which the signal transmission/reception method according to the present invention is applied to a button telephone system.

In the same figure, L1 to L8 are button telephones, and each of these key telephones L1 to L8 includes a button circuit 1 having a central office line selection button, an extension selection button, a button for inputting dial information, etc. a display circuit 2 consisting of a light emitting diode, etc. for displaying displays corresponding to the operations of various buttons and other necessary instructions; an amplifier circuit 3 for driving a doorbell, a bell, etc.; and a button given from the button circuit 1. A one-chip microcomputer, etc. that encodes various control signals (data signals) caused by operations, decodes display signals corresponding to button operations and data signals from the parent device C, and outputs corresponding display signals and control signals. The control circuit 4 consists of a control circuit 4, an interface 5 that relays data signals between the control circuit 4 and the parent device C, and a communication network 6 that is independent of these control systems. and communication system are connected to the parent device C by a pair of lines 11 and 12, respectively.

On the other hand, the parent device C has an interface 7 that relays data signals between each of the key telephones L1 to L8, and each of the key telephones that is input via this interface 7.
A control circuit 8 decodes the data signal of L8 and provides necessary control signals to the communication path forming circuit 9, and also sends the necessary data signals to each button telephone L1 to L8, and a control circuit 8 which decodes the data signal of L8 and provides the necessary control signal to the communication path forming circuit 9. and a communication path forming circuit 9 that connects the telephone to the office line to form a communication path, and the control circuit 8 transmits and receives data signals between the key telephones L1 to L8 connected in parallel to the interface 7 and the parent device C. Ll,
L2. This is performed cyclically in the order of L3...L8.

Further, in this case, the supply of power to each button telephone set through L8 and the transmission and reception of data signals are performed in a time-division manner within a cyclically selected period.

FIG. 2 is a circuit diagram showing an example of a detailed circuit of the interface 5 and the interface 7, which are the essential parts of the present invention, and shows the connection between the button telephone L1 and the parent device C as a representative.

In the same figure, the interface 7 of the parent device C is roughly divided into two parts: a voltage level VA via a line 11 to a button telephone L1;
A power sending circuit 700 that sends out power at a voltage level VC (48 V) and a voltage level VC (2
A signal sending circuit 720 that sends out a data signal and a clock signal indicated by a change in voltage level with reference to 4V).
and a signal receiving circuit 740 that receives a data signal and a clock signal indicated by a change in voltage level with respect to the voltage level VD (12V) inputted from the button telephone L1 via the line 11.

The power sending circuit 700 has a transistor 701 that becomes conductive when the power sending control signal PC1 outputted from the control circuit 8 becomes "H++ level" and a transistor 701 that becomes conductive due to the conduction of this transistor 701, and the voltage level VA ( 48V) via a diode 703 between terminals 1a' and 1b'.

Further, the signal sending circuit 720 has a voltage level VC (24V
) and a clock signal of voltage level VC1 (21V) indicated by a change in voltage level with respect to voltage level vC
Transistor 72 outputting a data signal of 2 (18V)
1 and a data transmission control signal C output from the control circuit 8.
When NO reaches the Hl+ level, it becomes conductive and the transistor 72
1 is non-conductive, and flilJi
11 The clock signal DLO output from the circuit 8 is “Hu”.
When the level is reached, the transistor 724 becomes conductive and controls the base current of the transistor 721 by the voltage division ratio of the resistor 725 and the resistor 727, and the transistor 724 outputs a clock signal of the voltage level VC1 (21V) from the control circuit 8. When the data signal DHO to be output reaches the UPI level, the transistor 7210 base current is controlled by the voltage division ratio of the resistor 725 and the resistor 726, and the voltage L/to/L/VC2 (18V) is applied to the transistor 721. The output of the transistor 721 is sent to the line 11 via a diode 728.

Note that the parent device C sends a clock signal DL to the key telephone L1.
When transmitting O or data signal DHO, data transmitting control signal CNO is controlled to be at "'L" level, and this data transmitting control signal CNO is "L I+".
The control circuit 8 prevents the clock signal DLO and data signal DHO from becoming the "H1 level" at the same time.
is controlled by.

Further, the signal receiving circuit 740 receives the voltage level VI) (12V) sent from the interface 5 of the button telephone L1.
A transistor 741 that becomes non-conductive when detecting a clock signal at a voltage level vD1 (9V) based on the voltage level ■D2 (6V), and a transistor 742 that becomes non-conductive when a data signal at a voltage level ■D2 (6V) is detected.
1 and VD2 are detected using constant voltage diodes 743°74
It is done in 4.

The constant voltage diode 743 that detects the voltage level VD1 (9V) has a Zener voltage characteristic of 10V.
Further, the constant voltage diode 744 for detecting the voltage level D2 (6V) has a Zener voltage characteristic of 7V.

Therefore, transistor 741 is at voltage level VD2 (6
It also becomes non-conductive when a data signal of V) is input.
These transistors 741 and 742 are connected to terminal 1a'
When the voltage between -1b' is equal to or higher than IOV, it is always in a conductive state.

On the other hand, the interface 5 of the button filling machine Lt can be roughly divided into two parts: it receives the power at the voltage level VA (48V) input from the power transmission circuit 700 of the parent device C via the line 11, and converts it to its own voltage level VD (12V). ) and maintains this voltage for a certain period of time, and the line 1
A signal sending circuit 520 that sends out a data signal and a clock signal indicated by a change in voltage level with reference to voltage level VD (12 V) through a line 11, and a signal sending circuit 520 that sends out a data signal and a clock signal indicated by a change in voltage level with respect to a voltage level VD (12 V) through a line 11, and a voltage level VC (24 V) input through a line 11. In addition to receiving the reference data signal and clock signal, the parent device C
and a signal receiving circuit 540 that detects the end of the transmission period of the data signal and clock signal from.

The power reception circuit 500 has a transistor 501 that becomes conductive when it detects that the voltage between the terminals 1a and 1b is at the power reception level, and a transistor 501 that becomes conductive and is input to the emitter via a diode 502. A transistor 503 that supplies the voltage of the terminal 1a to a regulator 504, a regulator 504 that converts the voltage input at the voltage level VA supplied from the transistor 503 to its own voltage level VD (12V), and a regulator 504 that holds the output of the regulator 504 for a certain period of time. Detection of the power reception level is performed by a constant voltage diode 506.
06 has a Zener voltage characteristic of 25V.

Further, the signal sending circuit 520 receives a clock signal at a voltage level VDI (9V) and a data signal at a voltage level vD2 (6V), which are indicated by a change in voltage level with respect to the voltage level VD (12V) output from the regulator 504. When the output transistor 521 and the clock signal DL1 output from the control circuit 4 reach the 4 (HBy level), the transistor 521 becomes conductive and the base current of the transistor 521 is controlled by the voltage division ratio of the resistor 524 and the resistor 525.
When the data signal DH1 outputted from the control circuit 4 reaches the 1 (H'' level), the transistor 522 is connected to the transistor 21 to send out a clock signal at the voltage level VD1 (9V). 5210 and a transistor 523 for controlling the base current and causing the transistor 521 to send out a data signal of voltage level D2 (6), and the output of the transistor 521 is sent out to the line 1□ via the diode 527.

Note that the clock signal DL□ and the data signal DH1 output from the control circuit 4 do not attain the "'H" level at the same time.

The signal receiving circuit 540 also includes a transistor 541 that becomes non-conductive when it detects a clock signal of a voltage level VC1 (21V) based on the voltage level VC (24V) input via the line 11, and a transistor 541 that becomes non-conductive at a voltage level VC2. (18V
), and a transistor 543 that becomes non-conductive when the period of sending the data signal and clock signal from the parent device C ends and the line voltage Vl becomes 13 V or less. , voltage levels VC1 (21V), VC2 (18V), and detection voltage level V for stopping transmission of data signals and clock signals.
B (12V) is detected by constant voltage diode '544,54
5,546.

The constant voltage diode 544 that detects the voltage level VC1 (21V) has a Zener voltage characteristic of 22V.
Further, the constant voltage diode 545 for detecting the voltage level vC2 (18V) has a Zener voltage characteristic of 19V.

Furthermore, the constant voltage diode 546 for detecting the voltage level VB (12V) is selected to have a Zener voltage characteristic of 13V.

Therefore, the transistors 541, 542, and 543 are all connected because when the parent device C stops sending power, data signals, and clock signals, the voltage between terminals 1a and 1b becomes the output voltage level VD (12V) of the regulator 504. It becomes a non-conducting state.

Note that the resistors 10 and 11 connected to the input terminals of the interfaces 5 and 70 are resistors for matching with the line.

In the above configuration, the data signal and clock signal transmitted and received between the parent device C and the key telephone L1 and the voltage level for power transmission are summarized as follows.
The result will be as shown in the figure.

As is clear from the figure, ■ indicates the voltage level range for power transmission sent from the parent device C to the button telephone L1, and ■ indicates the data signal and clock signal sent from the parent device C to the button telephone L1. 2 indicates the voltage level range of the data signal and clock signal sent from the button telephone L1 to the parent device C.

The operation of the button telephone system with the above configuration will be explained below using the time charts of FIGS. 4 and 5.

First, as shown in the time chart in Figure 4, an equal time T is allocated to each button telephone L1 to L8 during the data transmission and reception period between the key telephones L1 to L8 and the parent device C. Time T is Ll, L2. L3...
...Changes cyclically in the order of L8.

The signal corresponding to the data transmission/reception period for the button telephone L1 is the power transmission control signal PC1 outputted by the control circuit 8.
The power transmission control signals PC2 to PC2 shown in FIG. 4 b-h are
PC8 is a signal corresponding to the data transmission/reception period for the key telephones L2 to L8.

Therefore, the power sending circuit 70 corresponding to the button telephone L1
0 transmits power at the voltage level VA (48V) to the key telephone L1 when the power transmission signal PC1 is at the "H" level, that is, when the period is other than the data transmission/reception period (time T).

The same applies to button telephones L2 to L8.

The transmission and reception of data signals between the key telephone L1 and the parent device C will be described below as a representative example.

First, when the control circuit 8 outputs the power transmission control signal PC, ("L" level) with a time width of T as shown in FIG. 5g,
Power sending circuit 700 stops sending power at voltage level VA (48V) to button telephone L1.

At this time, the data transmission control signal CNO output from the control circuit 8 is at the Ll+ level as shown in FIG. It shows.

Therefore, when the data transmission control signal CNO is at the "L" level,
Moreover, while both the clock signal DLO and the data signal DHO are at the "H1+ level", the signal sending circuit 720 has the transistor 721 conductive and the voltage level VC (24V).
is sending out the output of

For this reason, power sending circuit 700 is at voltage level VA (48
When the power transmission of V) is stopped, the line voltage V of the line 11
1 becomes the VC level (24V) as shown in FIG. 5g.

Then, when the control circuit 8 outputs the lock signal DLO as shown in FIG. 5C, the clock signal DLO becomes "'H".
While at the level, the transistor 7 of the signal sending circuit 720
21 has its base current reduced by conduction of transistor 724, and sends out a clock signal at voltage level VC1 (21V).

On the other hand, the interface 5 of the button telephone
1 line voltage V1 is 25 V or more (voltage diode 50
60 Zener voltage or higher), the transistors 501 and 503 of the power receiving circuit 500 conduct, and the line voltage Vl is reduced to the voltage level VD (12 V) by the regulator 504.
), and this voltage level VD (12V) is held in capacitor 505.

The holding time Q by this capacitor 505 is set longer than the data transmission/reception period T with the parent device C assigned to each of the key telephones L1 to L8.

Then, the power transmission period by the power transmission circuit 700 of the interface 7 ends, and the line voltage Vl reaches the voltage level VC(
24V), the transistors 501 and 503 of the power receiving circuit 500 become non-conductive, and the regulator 504 stops outputting the voltage level VD (12V).

However, the voltage at voltage level VD (12V) is maintained by capacitor 505 for tv time.

The voltage held by the capacitor 5 (12V) is supplied to the signal sending circuit 520 and the signal receiving circuit 540 as an operating power source.

Therefore, when the power sending period by the power sending circuit 700 ends and the signal sending circuit 720 sends out a clock signal of voltage level VCI (21V), the transistor of the signal receiving circuit 540 becomes non-conductive.

As a result, a received clock signal CK1 as shown in FIG. 5g indicating that the transistor 541 has received a clock signal from the parent device C is outputted to the control circuit 4.

Then, when the control circuit 8 of the parent device C outputs a 4-bit serial data signal DLO of "0100" as shown in FIG. 5C in synchronization with the clock signal DLO, the data signal DL
While O is at the "Hn level" (1 level), the signal sending circuit 720 sends out a data signal at a voltage level of C2 (18).

As a result, the signal receiving circuit 54 of the button telephone L1
0 transistor 542 has a line voltage Vl of 19V or less (
4 of "oioo" as shown in Figure 5j.
The bit series signal is outputted to the control circuit 4 as a received data signal DT□.

In this case, the signal sending circuit 720 of the parent device C does not send out a clock signal at the sending timing of “1” among the 4-bit serial data signals, but the signal receiving circuit 54
Since the clock signal identification level of 0 is 22V, the transistor 541 becomes non-conductive even when a data signal of voltage level V C2 (18V) is sent.

Therefore, the data signal “
'o i o o' is output to the control circuit 4 in synchronization with the clock signal CK1.

When the transmission of the 4-bit serial data signal DLO from the parent device C to the button telephone L1 is completed in this manner, the control circuit 8 sets the data transmission control signal CNO to the "H" level.

While this data exit control signal CNO is at the "Hn level," this indicates that it is a period for transmitting data signals from the key telephone L1 to the parent device C.

When this data transmission control signal CNO becomes "'H" level, the transistor 722 of the signal transmission circuit 720 of the parent device C becomes conductive, and accordingly, the transistor 721
becomes non-conducting.

Therefore, the signal sending circuit 720 is at voltage level VC (24
V) output is stopped.

As a result, the line voltage Vl is the voltage held by the capacitor 505 of the power receiving circuit 500, that is, the voltage level VD(
12V).

As the line voltage Vl reaches the voltage level VD (12V), the transistor 543 of the signal receiving circuit 540 becomes non-conductive, and this is a period in which the key telephone L1 sends out data signals and clock signals as shown in Figure 5. A data transmission control signal CN1 indicating this is output to the control circuit 4.

Upon receiving this data transmission control signal CN1, the control circuit 4 transmits the data signal DH to the parent device C.
1 and the clock signal DL1 are outputted as shown at l in FIG.

Then, the signal sending circuit 520 receives this clock signal DL.
1 and the data signal DH1, the voltage level VD(
12V) as a reference voltage level #vI)1 (
9V) clock signal and voltage level VD2 (6V)
The data signal is sent to the parent device C via the line 11.

Therefore, the line voltage Vl during the period when the data signal and clock signal are sent from the button telephone L1 is as shown in FIG. 5g.

In this way, the data signal (in this example, a 4-bit serial data signal of "0100") and the clock signal sent from the button telephone L1 to the parent device C are received by the signal receiving circuit 740 of the interface 7. .

That is, the signal sending circuit 520 has a voltage level VD1 (
9V), the signal receiving circuit 74
0 transistor 741 becomes non-conductive and outputs a signal as shown in FIG. 5e to the control circuit 8 as the reception clock signal CKO.

Similarly, the signal sending circuit 520 is at voltage level VD2 (6V
), the transistor 742 of the signal receiving circuit 740 becomes non-conductive and outputs a signal as shown in FIG. 5f to the control circuit 8 as the received data signal DTO.

The control circuit 8 monitors the reception clock signal CKO, and when a predetermined number of reception clock signals CKO are input, sets the data transmission control signal CNO to "L9 level".

When the data transmission control signal CNO becomes the "L tl level," the transistor 722 of the signal transmission circuit 720 becomes non-conductive, and the signal transmission circuit 720 changes to the voltage level VC (
24V) is sent to line 11.

Then, after a slight delay, the power transmission control signal PC1 is changed to “HD”.
level, and the voltage level VA (4
8V) power is sent out.

Then, the control circuit 8 sets the power output control signal PC2 to the button telephone L2 to the L'' level for a time T, and performs data transmission and reception with the button telephone L2.

As described above, when the signal transmission/reception method according to the present invention is applied to a button telephone system, the parent device and the button telephone can be connected by two pairs of lines, which is extremely effective economically.

In addition, in this embodiment, the power supplied from the parent device is not directly used on the button telephone side, but is converted to its own voltage level and held for a certain period of time, and this holding voltage is used to send signals from the key telephone to the parent device. Since the reference voltage is set to , it has the advantage that necessary signal transmission and reception can be performed with less power.

In addition, since the current flowing through the line during the signal sending period is only the base current of the transistor of the signal receiving circuit, it is very small, which reduces the voltage drop caused by the line resistance RL, and makes it easier to identify the voltage level of the signal. There is.

Further, since signals are cyclically transmitted and received between a plurality of key telephones and the parent device, there is an advantage that the parallel conversion processing circuit or program for serial data signals can be used in common in the parent device.

Although this embodiment has been explained using a button telephone as an example of a terminal device, the present invention is not limited to this, and can be applied to various devices as long as they transmit and receive signals with a parent device. It is possible.

Further, although the signal transmission and reception between the plurality of button telephones and the parent device is carried out cyclically, it may be carried out only when necessary.

As explained above, according to the present invention, the parent device and the terminal equipment can be connected with a small number of line configurations, and especially when applied to a button telephone system, the parent device and the button telephone can be connected with two pairs of lines, which is economical. It has extremely good effects.

In addition, the power supplied from the parent device is not used as is on the terminal device side, but is converted to its own voltage level and held, and this holding voltage is used, allowing the necessary signal transmission and reception with less power. There are advantages to being able to do so.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing an embodiment in which the signal transmission and reception method according to the present invention is applied to a button telephone system;
Figure 2 is a circuit diagram showing the details of the interface in the system configuration diagram of Figure 1, Figure 3 is a diagram showing the voltage and level setting values for power transmission and signal transmission and reception, and Figure 4 is a diagram showing the signal of multiple button telephones. FIG. 5 is a time chart showing the allocation of transmission and reception periods. FIG. 5 is a time chart for explaining the operation of the embodiment shown in FIGS. 1 and 2. L1-L8...Push-button telephone, C...
Parent device, 1...Button circuit, 2...Display circuit, 3...Amplification circuit, 4, 8...
Control circuit, 5, 7... Interface, 6...
...Telephone circuit network, 9...Telephone path formation circuit,
500...Power receiving circuit, 520,720...
... Signal sending circuit, 540, 740... Signal receiving circuit, 700... Power sending circuit.

Claims (1)

[Claims] 1 In a signal transmission/reception method in which various control signals are transmitted and received between a parent device and a terminal device by wire, power is sent from the parent device to the terminal device at a first voltage level for power transmission, and this first The terminal device receives power from the voltage level, converts it to its own second voltage level, and holds it for a certain period of time.
The signal transmission and reception is characterized in that a signal based on the second voltage level is transmitted from the terminal device to the parent device within a certain period of time following the power transmission period at the first voltage level. method.