JPS5838993A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control device, and particularly to a display control device which is suitable for use in a graphic display device.

In addition to the functions of the character display, the Ray device in Darafi and Kudis can display figures, and can also use a light pen to indicate the displayed content, and can move the displayed figures in relation to the software.・Rotate/Enlarge/Reduce・
The so-called graphics of deleted cicadas, ri!・There are various types of display data such as letters, dots, lines, and circles in -1, and these are combined by two programmers to create one meaningful data. generated.

As Birdo and A, each generator has its own generator to generate the A turn, but the software that operates them is a series of Q that all have the same format.
It is made up of commands consisting of N and T configurations.

FIG. 1 shows an example of the configuration of a conventional general DARRAQUICK DISGray device O, in which 1 is a figure generation circuit;
is a display memory, 3 is a display unit including a display monitor and a monitor control system, and in the figure, DADIL is a display mail address, DDAT is display data, RDAT is display memory read data, and C0NT is a monitor control signal. The 0-figure generating circuit 1, which indicates each signal (synchronization signal, video signal, etc.), is a circuit for generating circles and figures (straight line/circle 4%) according to commands, and includes a function generator and the like. microphone a
7' Use a sessa? In contrast to the 6-figure generation circuit that outputs the memory address DADR and write data DDAT to write the figure information, there is a 0-display memory 2 that outputs the memory address DADR and write data DDAT. %Nita top)
Contains information to be displayed. (There is also 4 which I remember from the door tonnage analogy) Display section゛
J is used to display the contents stored in the display memory 9JK, and displays according to the monitor control signal C0NTK.Actually, a circuit for controlling the address to display the data from the display memory 2 is also required. There is, but it is omitted in ζζ.

With the conventional graphics and Kudisgray device mentioned above, there are only a few problems when writing figures sequentially, but once he displayed a complicated figure and wanted to erase part of it, the following problem occurred. . That is, when a figure to be erased overlaps with another figure, the figures are erased at the same time because the distortion cannot be detected. This situation is shown in Figure 2 aebt.
As shown in Figure 2 (&),
Suppose that three straight lines are displayed. 2 of these
When trying to erase the straight line, the intersection point disappears as shown in Figure 2(b).This is not always the case with the conventional Daraffy-Kdiss Ray device with the configuration shown in Figure 1. This is a phenomenon that occurs and has traditionally been viewed as a problem. In addition, there is a method using software control to prevent necessary parts from being erased at the same time when partially erasing a figure, but if you try to implement this, the processing time will be affected by 1, making it inefficient. It was.

The present invention has been made in view of the above-mentioned drawbacks.The present invention has been made in view of the above-mentioned drawbacks of the conventional graphic display device, which has a memory separate from the display memory and a small amount of peripheral circuitry. It is an object of the present invention to provide a display control device that can easily restore simultaneous erasure of other national shapes that occur during erasure, and that improves overall arm strength.

Hereinafter, the present invention will be explained in detail using FIG. 3.

3. In FIG. 0, which is an fp and evening diagram showing an embodiment of the display control device of the present invention, 1 is a graphic generation circuit, 2 is a display memory, and 3 is a display section, which is the conventional example of FIG. Since it has the same function as ``a'', its explanation here will be omitted. Reference numeral 11 denotes a memory provided separately from the display memory 2. This memory 11 stores a plurality of bytes of data in accordance with the configuration of the display memory 2, with one storage unit (i4 ite) having a number of bits equal to the number of address Vt and the number of data bits. 12 is a memory control circuit. This memory control 1 circuit 12 has a built-in register (not shown) for storing the memory address in the memory 110, and the address value to be referenced externally is set and sequentially updated. 11 is an input data buffer, 14 is an output data buffer, and 4. has the function of stopping counting when it reaches 9. It is Fa.

The input data Δ, 771B temporarily stores information obtained as a set of the display memory rear address DADR obtained from the graphic generation circuit 1 and the read data RDAT obtained from the display memory 2, and sends it to 11 as a write data consideration. supply The output data buffer 14 temporarily stores information obtained from the message 11, and supplies the address MADIL and time T as a set to the selector 15.

In addition, a display memory address DADRfi obtained from the graphic generation circuit 1 and display write data DDm to the display memory 1 are supplied to the selector 1j as a set. One of the above two sets is selected, and its address A
DH and data DAT are supplied to the display screen 1. The operation of the present invention will be explained in detail below.

During normal operation, the selector 15 selects the display memory address DADR and data DDAT, which are output more than the graphic generation N path 1.
The set is enabled. Therefore, when the address DADR is outputted from the figure generation circuit 1 to the υ display memory 2,
The 0-figure generating circuit 1 from which the data RDAT is read from the display memory 2 creates write data in response to each command based on the read data RDAT and outputs it as display write data DDAT. Then, by repeating the six or more steps of supplying the final write data DAT to the display memory 2 via the selector 15, the content desired to be graphically displayed is written into the display memory 2.

During execution of the above operations, the following operations are also executed.The display memory address DADR is output from the 0 figure generation circuit 1.
The entertainment data RDAT obtained from the display memory 2 is input to the input data pad 77JJK. These pieces of information (DADR and RDAT) are separately prepared and stored as memory write data. As described above, the memory address MEM_AD]l specified at this time is specified by a register built into the memory control circuit 12.

The memory control circuit 12 receives signals from the graphic generation circuit 1 to start and end the operation, and then accesses the memory 11 with a 1711# (access) - start number of address? +il 7i and end address are also memorized and stored. By repeating the above operation, the new graphic information specified by the graphic generating circuit 1 is stored in the display memory 2, and the display section 3 is displayed through. The memory 11 stores the changed address of the display memory 2 and the data previously stored in the display memory 2 at that address.

Now, the operation during modification will be explained here. When the t% figure generation circuit IK tries to erase a specified figure, etc., the memory control circuit 12 outputs the address at the start of operation again as MEM ADH. do. This Jin and Nyoru,
A data trace is obtained from the memory 11 and is sent to the output data file 14. Output data/child, set to Fa 14.

The read data is stored at memory address MADR and data 'I'.
The data are divided into MDATs and output. Also, at this time, the selector 15 is set to a punch that makes the address MADR and data MDAT valid. Therefore, address MADR and data MDAT read from memory 11 are sequentially written into display memory 2. The above operation is repeated until the counter built into the memory control circuit 12 is updated to the end address. When the above operation is completed, the display memory 2 returns to the state it was in before receiving the designation from the graphic generation circuit 1. This means that it has become. This is the same as deleting the figure.

Note that, regardless of the configuration (number of bits) of the display memory 2, the present invention has a wide range of applications because the memory 11 and its peripheral circuits can be arbitrarily set accordingly.

As explained above, according to the present invention, it is possible to erase or modify figures reliably and in a short time.

Also, the internal control when performing partial deletion etc. is simpler than before! In a display terminal device disguised as Iku4Glosse, Su, etc., there is also the derivative effect that the 7'a-gram is simplified.

In the embodiments of the present invention, only graphic display devices have been described, but the present invention can be applied to all display devices including other character displays. or,
The present invention can also be applied to a terminal device having a memory.
It can be effectively used to improve efficiency or accuracy when modifying memory contents. Further, in the present invention, an example has been shown in which an address and data are stored in the memory as a set of O information, but if they are treated the same (the address is the same), they may be stored as separate data.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of the configuration of a conventional general graphics and Kudisgray device, Figures 2 (a) and (b) are diagrams showing an example of the image wIi displayed by a conventional graphics display device, and Figure 3 is FIG. 4 is a diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Graphic generation circuit, 2-Display memory, 3...Display part, 11...Memory, 12-Memory control circuit, JJ-
・・Input data path, F, 14-・Output data path, F, 15-・Selector, ・Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 (a) (b)

Claims (1)

[Claims] In a display system that displays display information such as characters and figures stored in a display screen via a display section, a memory that stores the number of address bits and the number of data as one unit according to the configuration in the display memory. and a control unit that sets a reference address for this memory, updates it sequentially, and stops the operation when it reaches a certain predetermined value, and applies an address specified by the second control unit to the memory. In particular, a first circuit means for inputting information (addresser data) obtained by the above-mentioned memory, and at the same time inputting information into the display memory from the above-mentioned memory, the address and data obtained by the above-mentioned first circuit means are 5. A display control device comprising: second circuit means for inputting information.