JPS5838087A - Composition video signal processing circuit - Google Patents

Abstract

PURPOSE:To output a composite video signal that contains a synchronizing signal with a proper amplitude by amplifying an input composite video signal by a variable gain amplifier circuit and applying amplitude stretching process only to the synchronizing signal. CONSTITUTION:A transistor TRTR2 is brought into on-state for a period TS of synchronizing signal Sync of input video signal SCIN applied through a signal input terminal 20A in a composite video processing circuit 20. A variable gain type amplifier circuit 22 has gain G determined by resistances R1, R2 and R3 between the signal input terminal 20A and grounding, and the gain G is changed and controlled by on and off of TRTR2 of a synchronizing signal detecting circuit 21. When TRTR2 is in off-state the gain G1=(R2+R3)/(R1+R2+R3), and when TRTR2 is in on-state, gain G2=R2/(R1+R2). By this way, the amplitude stretching process is applied to output signal SCOUT by synchronizing signal Sync in the signal SCIN.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite video signal processing circuit applied to various image devices such as television receivers and video tape recorders that handle composite video signals, that is, video signals on which synchronization signals are superimposed.

In general, various types of imaging equipment that handle composite video signals perform various signal processing and operation controls based on the synchronization signal in the composite video signal, so it is necessary to ensure a synchronization signal with an appropriate amplitude. . For example, in a television receiver, the synchronization signal in the composite video signal is
The structure is such that the images will not be synchronized even if they are reduced to about 0 dB. However, if the synchronization signal is compressed in a general television receiver, even if no synchronization flow occurs in the image, synchronization jitter due to video signal components and the like occurs in the synchronization circuit system, which tends to distort the image.

Furthermore, in a video tape recorder, if the synchronization signal in the input composite video signal is compressed, the drive servo systems such as the rotating magnetic head device and the tape running system are likely to be disturbed.

By the way, in local relay stations installed in television broadcasting networks and television systems with communal reception methods, the synchronization signal in the composite video signal may not be normal due to the operating characteristics of the relay amplifiers used. In many cases, the amplitude is smaller than the amplitude of . Therefore, in various image devices such as television receivers and video tape recorders used in the above-mentioned communal reception television system, etc., it is necessary to take measures against the shrinkage of the synchronization signal in the composite video signal.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a composite video signal processing circuit that performs amplitude expansion processing only on the synchronization signal in the composite video signal to compensate for the shrinkage of the synchronization signal.

Hereinafter, a composite video signal processing circuit according to the present invention will be described in detail with reference to the drawings showing embodiments.

The first embodiment shown in FIGS. 1 and 2 shows a specific example of compensating for the compression of the synchronization signal of a composite video signal obtained by an integrated circuit 10 for a video intermediate frequency circuit manufactured by It is.

In this embodiment, an integrated circuit 10 for a video intermediate frequency circuit is used.
A composite video signal is supplied to a composite video signal processing circuit 20 according to the present invention. The above-mentioned integrated circuit 10 is a general type that has been widely used in the past, and includes the first to third video intermediate frequency amplifiers 11, 12, 13, video detection circuit 14, AGC circuit 15, etc. as an integrated circuit. A composite video signal is reproduced by amplifying a video intermediate frequency signal supplied from a tuner block that is not connected to the video intermediate frequency signal by each of the video intermediate frequency amplifiers 11, 12, and 13, and then subjecting it to, for example, synchronous detection in the video detection circuit 14. Note that the first and second video intermediate frequency amplifiers 11 and 12 are connected to the video detection circuit 14.
The detection output from the video detection circuit 14 is fed back as a gain control signal via the AGC circuit 15, so that even if the signal level of the input video intermediate frequency signal changes, the detection output from the video detection circuit 14, that is, the signal level of the composite video signal, is always maintained. Automatic gain control is applied to each to keep it constant. Even if the integrated circuit 10 for the video intermediate frequency circuit equipped with such an automatic gain control function is used, if only the synchronization signal of the received television signal is shrunk, the video detection circuit 14 The synchronization signal in the composite video signal obtained as well logging output is in a compressed state. Note that if the automatic gain control is performed so that the amplitude of the synchronization signal in the composite video signal outputted from the video detection circuit 14 always has a normal width, the synchronization signal will be shrunk. When receiving a television signal, each intermediate frequency amplifier 1
Since gain control is performed to increase the gain by 1.12, the signal level of the entire composite video signal output from the video detection circuit 14 becomes extremely high. Therefore, it is extremely inconvenient that the synchronization system circuit block and the video processing system circuit block provided on the downstream side of the integrated circuit 10 malfunction due to the influence of the excessive input that exceeds their dynamic range.

Therefore, in this embodiment, the composite video signal processing circuit 20 according to the present invention deals with the composite video signal of a constant signal level output from the integrated circuit 10 for the video intermediate frequency circuit.
By performing amplitude expansion processing only on the synchronization signal, a composite video signal having a synchronization signal with an appropriate amplitude is obtained.

The composite video signal processing circuit 20, as shown in FIG. and a variable gain amplifier circuit 22 whose gain is controlled based on the detection output of. In this specific example, the variable gain amplifier circuit 22 is configured with an emitter follower amplifier using an NPN transistor TR, and the base of the NPN transistor TR+ is connected to the signal input terminal 20A via an input resistor R1. and are connected via two dividing resistors R2 and Rs. Note that a frequency correction circuit 23 formed by connecting a coil L and a capacitor C in series is connected in parallel to the input resistor R1.

Further, the collector of the NPN) transistor TR1 is connected to the positive power supply terminal 20B, and further,
Its emitter is connected to the signal output terminal 20C and grounded via a resistor R4.

Then, the variable gain amplifier circuit 22 is
The connection point of the two dividing resistors Rz and FLs connected in series between the base of the transistor TRs and the ground is connected to the emitter of the PNP transistor TR,2 of the synchronization signal detection circuit 21.

Still, the synchronization signal detection circuit 21 is a PNP transistor T.
Rz, a capacitor C2 connected to the base of the PNP transistor TR2, and a resistor Rs, and a resistor R6 connected in series between the signal input terminal 20A and ground.
The input composite video signal is supplied through a low-pass filter 24 consisting of a capacitor C3 and a capacitor C3.

That is, the base of the PNP transistor TR2 is grounded via a resistor R5, and is also connected via a capacitor C2 to the connection point between the resistor R6 and the capacitor C3.

In the composite video signal processing circuit 20 configured as described above,
The synchronization signal detection circuit 21 is a PNP transistor T R2
The time constant of capacitor C2 and resistor 'Rs connected to the base of is set corresponding to the pulse width of synchronization signal sync included in input composite video signal 5CrN, and is supplied through signal input terminal 20A. For example, the synchronization signal 8 of the input composite video signal SCIN has a waveform as shown in FIG. 3A.
The above PNP transistor TR only for the period Ts of ync.
, 2 are in the ON operating state. Further, the variable gain amplifier circuit 22 has a gain G determined by the resistance ratio of three resistors R+, Rz, and FLx connected in series between the signal input terminal 20A and the ground, and the synchronous signal detection circuit 21 PNP) transistor TR2, which constitutes PNP, is turned on.

The resistance ratio, that is, the gain G is switched and controlled by the OFF operation. Here, when the above-mentioned PNP transistor TR2 is in the off operation state, Gt for Q is expressed by the first equation: R2+R5 Gl=□... Song/Song First equation % equation % Also, the above PNP The gain G2 when the transistor TR2 is in the ON state can be expressed by the second equation: 2 G2 = □ 2 R1 + R2.

Therefore, as shown in FIG. 3B, the output composite video signal S Cout obtained at the signal output terminal 20C via the variable gain amplifier circuit 22 is the input composite video signal 5CIN shown in FIG. 3A. The amplitude expansion process is applied only to the synchronization signal 8y41c.

That is, assuming that the video signal level of the input composite video signal 5CIN is El, the pedestal level is E2, and the synchronization signal level is E3, the video signal level E+ of the output composite video signal SCOUT is Et=01·El.

Also, the pedestal level E2 is E4 = C3,t・
E2, and furthermore, the synchronization signal level E3 is Ez=(h・E3
Therefore, the ratio of the amplitude Ex-Bs of the synchronizing signal 8ync to the amplitude EI-Ex of the video signal Sv, the so-called 2/゛S ratio, is smaller than the V/S ratio of the input composite video signal 8Ctpt.

Next, a second embodiment shown in FIGS. 4 and 5 shows a specific example in which the entire video signal processing system circuit to which the present invention is applied is integrated.

In this embodiment, first to third video intermediate frequency amplifiers 31, 32, and 33' amplify video intermediate frequency signals supplied from a tuner block (not shown), and reproduce a composite video signal from the amplified video intermediate frequency signals. The video detection circuit 34 performs gain control of each of the video intermediate frequency amplifiers 31-, 32, and the like. The signal processing circuit 40 is integrated.

In FIG. 5 showing a specific circuit configuration of the signal processing circuit 40 that constitutes the main part of the present invention in this embodiment, the collector is connected to the power supply line Vcc, and the emitter is grounded via the first transistor TRo1. The second transistor TRO2 forms an input buffer circuit, and the composite video signal obtained by the video detection circuit 34 is input to its base. Also, each emitter is a third NPN
The fourth and fifth NPN transistors TRO4 and TRoa, which are commonly grounded via the transistor TRoz, form a first differential amplifier circuit, and the fourth NPN
PNI - the above second NP at the base of transistor TRoa
N) Composite video signal 5CIN via transistor TRO2
is supplied, and its fifth NPN) transistor TR
The first to third resistance nodes at the base of the OS.

A first reference voltage EA obtained by a voltage dividing circuit using Rb and RC is applied. Then, a fifth NPN) transistor T forming this first differential amplifier circuit
The output signal obtained at the collector of Ros is fed back through the AGC circuit 35 to the first and second video intermediate frequency amplifiers 31 and 32 as a gain control signal. Furthermore, the seventh and eighth NPN) transistors TRO7°TRos, each of whose emitters are commonly grounded via the sixth NPN) transistor TRoa, form a second differential amplifier circuit; Seventh NPN transistor TRO
? A composite video signal is supplied from the emitter of the second NPK transistor TRO2 to the base of the transistor TRO2 via the 4.5 MHz trap circuit 41, and a composite video signal is supplied to the base of the eighth NPN transistor TRoa by the voltage dividing circuit. The obtained second reference voltage Ea is applied.

Then, the output signal obtained at the collector of the eighth NPNI-transistor TRos forming the second differential amplifier circuit is used as the synchronization detection output signal of the first PNP).
It is supplied to the base of transistor TRzt. That is, the seventh and eighth NPN transistors TRoy
, TR68 and the first (7) PNP) transistor TRz
t constitutes a synchronizing signal detection circuit 42.

Here, the first to third resistors Ra, Rh, and Rc forming the voltage dividing circuit are connected in series between the power supply line and the collector of the ninth NPN transistor TRos. Ninth NPN transistor T
It is grounded via Ros.

This ninth NPN) transistor TRoe has its base and collector connected, and functions as a constant current source. In addition, the above 1. 3rd, 6th and 9th NPN) transistors TRol.

TFLO3, TRoa; Each base of TR09 is commonly connected, and each NPNI-transistor TRos,
T'FLos.

TRog acts as a current mirror with respect to the ninth NPN transistor TR,09, and each acts as a constant current source. In addition, the above 4.5MHz
The trap circuit 41 is for blocking the audio signal component contained in the composite video signal 5CIN obtained by the video detection circuit 34, and is connected to an external connection terminal 40a provided in the integrated signal processing circuit 40. , 40b.

Further, the first PNP transistor TR21 functions as a switching element for gain control, and its emitter is connected to the power supply line, and its collector is connected to the series resistors RA and Re via the resistor Rc. Connected to the connection midpoint.

a second PNP transistor TR2 whose emitter is connected to the power supply line via the series resistors RA and Rs;
2, the composite video signal 8CIN is supplied to its base via the trap circuit 41. This second PNP transistor TRu forms a variable gain amplifier circuit 43, and its collector is connected to the tenth NPN transistor TRu.
It is grounded via R1o and connected to the bases of the tenth and eleventh NPN transistors TR10 and TR1t. The load resistor RD connected between the power supply line and the collector of the eleventh NPN transistor T Rr1 is the eleventh NPN transistor).
It is grounded via transistor TRII.

In the signal processing circuit 40 configured as described above, when a positive power supply voltage +Vcc is applied through the power supply line,
By the ninth NPN l-transistor ↑R109 working as a constant current source, the first to third resistors Ra,
Reference voltages Eh and EB with the relationship EA<EB are obtained at the connection midpoints of Rb and Rc. and a fifth NPN to which the first reference voltage EA is applied to the base)
The first video intermediate frequency amplifier 31.
By performing the automatic gain control of 32, the composite video signal SCIN obtained by the video detection circuit 34 is
As shown in the figure, the first reference voltage EA is held at a synchronizing level, for example, I Vp-p.

Therefore, the composite video signal 8CIN obtained by the video detection circuit 34 is supplied from the second NPN transistor TRot to the base of the seventh NPN transistor TR, 0? via the trap circuit 41. The second
In the differential amplifier circuit, the eighth NPN transistor TRo
When the base level of the seventh NPN transistor TRO7 becomes lower than the second reference voltage BB applied to the base of s, that is, the first reference voltage E
During the period Ts of the synchronization signal Sync whose synchronization level is ^, the eighth NPN transistor TRos enters an OFF operating state, and the seventh NPNI transistor TRO7 enters an ON operating state. Therefore, the seventh NPN transistor TKO? The collector of the first one is connected to the base.
PNP) transistor T R2t receives the synchronization signal 5y.
It is in the ON operation state only during the period Ts of nc.

That is, the seventh and eighth NPN) transistors T
RO? , TRos and the first PNP) transistor T
R11 operates as a synchronization signal detection circuit 42.

Further, the variable gain amplifier circuit 43 formed by the second PNP) transistor TR22 to which the composite video signal 5CIN is supplied to the base operates during the period when the first PNP) transistor T'FLzx is in the OFF state. Among them, the resistance value RA+R due to the series resistors RA and RB connected to the emitter side of the second PNP transistor TR22,
Current flows through the second PNP transistor TRZ2 with B as a load, and current flows through the first PNP transistor TRZ2 as a load.
21 is in the on operation state, that is, the synchronization signal S'y
During the period Ts of ne, the resistor Rz in series with the resistor Rc
, RB and the second PN with the resistance value 8A+R, c+RB as the load.
Current flows through the PI-transistor TR22. and 10th and 11th NPNs whose respective bases are commonly connected to the collector of the above-mentioned second PNP transistor TRzz.
Since the transistors TR+o and TRII act as current mirrors and have equal collector currents flowing through them, the load resistor Rn connected to the collector side of the eleventh NPN transistor TR11 and the load R of the first PNP transistor TR21, A composite video signal amplified with gains GA and Gn determined by the ratio of A-R'c to RA+RB or RA+RC+RB is obtained from the collector of the 11th NPN) run raster TR. That is, this variable gain amplifier circuit 43 amplifies signal components other than the synchronizing signal 5ync with a gain Gm, and only the synchronizing signal 3ync with a gain GB. Also, regarding the composite video signal 5CIH obtained by the video detection circuit 34, it is impossible to apply amplitude expansion processing to only the synchronization signal 5ync at a fixed ratio.

As is clear from the description of each embodiment as described above, according to the present invention, there is provided a synchronization signal detection circuit that detects a synchronization signal in an input composite video signal, and a variable gain control based on the detection output from the synchronization signal detection circuit. and a variable gain amplifier circuit in which the input composite video signal is amplified by the variable gain amplifier circuit to output a composite video signal in which only the synchronization signal is subjected to amplitude expansion processing. By doing so, it is possible to always secure a synchronization signal with a predetermined amplitude or more, and there is no risk of exceeding the dynamic register of various signal processing systems installed in the subsequent stage, making it a highly practical composite video signal processing circuit. can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a composite video signal processing circuit according to the present invention. FIG. 2 is a circuit diagram showing a specific circuit configuration of the signal processing circuit in the first embodiment. 3A and 3B are waveform diagrams for explaining the operation of the first embodiment, FIG. 3A shows an input composite video signal, and FIG. 3B shows an output composite video signal. It shows. FIG. 4 is a block diagram showing a second embodiment of the composite video signal processing circuit according to the present invention. FIG. 5 is a block diagram showing a specific circuit configuration of the signal processing circuit in the second embodiment. FIG. 6 is a waveform diagram of a composite video signal obtained by the video detection circuit in the above embodiment. 11.12,13,31.32,33 ・・・・・・・・・Eirin intermediate frequency intensifier 14・3
4......Video detection circuit 15.35 Song AGC circuit 20.40......Signal processing circuit 21
．． 42...... Synchronous signal detection circuit 22
．． 43・・・・・・・・・・・・Variable gain amplifier circuit patent applicant Sony Corporation representative Patent attorney Kodo Koike 1) Sakae Mura - 1st m1 side 211th 61I Ov-1--- −−−−−−−−− Procedural amendment (voluntary) 56 11 14 Showari Nenkigetsu Tsukiguchi, Commissioner of the Patent Office Shima 1) Haruki 1, Indication of the case 1982 Patent Application No. 135773 2, Invention Name Composite video signal processing 5 circuit 3, relationship with the case of the person making the correction Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Store Name (21
8) Name of Sony Corporation) Representative: Kazuo Iwama 4, Agent: 105 Address: 11th Floor, 11 Mori Building, 2-6-4 Toranomon, Minato-ku, Tokyo (508) 8266 (Representative) 6, Amendment The "Detailed Description of the Invention" column of the subject specification, Drawing 7, and the contents of the amendment (7-1) In the first embodiment, "manufactured" is replaced with "first
The example is corrected to "off-the-shelf." (7-2) "Detection output car" written on page 4, line 14 of the specification is corrected to "detection output." (7-3) Correct the drawings attached to the application by adding them to the attached sheet. 4th ■

Claims (1)

[Claims] comprising a synchronization signal detection circuit that detects a synchronization signal in an input composite video signal, and a variable gain amplifier circuit whose gain is variable controlled by the detection output from the synchronization signal detection circuit,
A composite video signal processing circuit characterized in that the input composite video signal is amplified by the variable gain amplifier circuit to output a composite video signal in which only the synchronization signal is subjected to amplitude expansion processing.