JPS5838028B2 - signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied to a color imaging device employing a phase separation method using a solid-state imaging body such as a CCD (charge-coupled device) as an imaging element to provide a suitable signal processing circuit.

When two information signals having different information contents are multiplexed and a phase separation method is adopted as a separation method, vertical correlation becomes a problem.

That is, although this separation method requires a strong vertical correlation, in some cases the vertical correlation may be weak or not present at all.

Therefore, in such cases where the correlation is weak, it is not possible to completely separate the two information signals, and the other signal multiplexed into one signal component remains, and this residual component is the content of the other signal. may have an adverse effect on

A suitable example of this is a color imaging signal obtained by an imaging device.

On the other hand, when using a solid-state image sensor such as a CCD as an image sensor, a color image signal in which a color component exists in a multiplexed state in a luminance component is obtained, as will be described later.
When separating the luminance component and the color component, the same phenomenon as described above may occur.

This will be explained with reference to the drawings, but as a solid-state image sensor, as mentioned above, let us take as an example a CCD, particularly a CCD that uses a frame shift method.

FIG. 1 is a schematic diagram of a COD that adopts this frame shift method, in which one person is an imaging unit onto which a desired subject is projected, and a desired number of picture elements are placed in the horizontal and vertical directions. is formed by forming an array.

Reference numeral 1B denotes an accumulation section for accumulating carriers for each frame (or field) according to the input light information of the subject obtained by the imaging section 1A, and is configured similarly to the imaging section 1A.

1C is a read register, and IH (H
The carriers for one horizontal scanning period are serially read out.

Note that 3 is a channel stopper.

Further, 4 indicates an output terminal.

FIG. 2 shows an example of the color filter 5 arranged in front of this CCDI.

This color filter 5 has a transmission area divided into a plurality of parts corresponding to the area of the picture element 2, and a transmission area with one button that blocks light in the horizontal scanning direction a so that the transmission area forms a checkered pattern. be done.

The light-shielding regions are formed to be shifted by an array bit τH between adjacent horizontal scanning lines.

For example, as shown in the figure, each of the primary color lights of R, G, and B is selected as the light transmitted through the transmission areas arranged in a checkered pattern, and these primary color lights are obtained with opposite phases in adjacent horizontal scanning sections. It will be selected by

When a subject is projected and imaged using the color filter 5 formed in a checkered pattern as described above, the output terminal 4
A color image signal So as shown in FIG. 3 is obtained.

In other words, since the input light information corresponding to the image of the subject to be imaged is sampled for each pixel and converted into an electrical signal, the color imaging signal So becomes a luminance signal as shown in FIG. 3A. In addition to the modulation component (DC component) SDO, a sideband component (AC component) SM is obtained.

In this case, the modulation component SDO and the sampling frequency fcl
(-1/3rHl), it is possible to prevent the sideband component sM from being mixed in the modulation component SDO as shown in the figure.
The bandwidth of the modulation component SDO may have to be narrowed, or conversely, the bandwidth of the modulation component SDO may have to be narrowed, for example, 3.5.
If it is selected to be about MHz, the sampling frequency fc/ will be increased accordingly, and the number of picture elements N in the horizontal scanning direction will need to be increased, which is not practical.

Therefore, in general, the signal S where both components SDOtSM overlap
Obtained as o.

Here, the phases of the R and B color components constituting the sideband component sM are obtained with a phase difference of 1,200 degrees, but the color filter 5 is arranged so that the phases are opposite in adjacent horizontal scanning sections. 3, the phase relationships among the color components are as shown in FIGS. 3A and 3B.

Therefore, the vertical phase relationship can be used to separate each modulation component into the luminance component and the sideband component, that is, the color component.

According to the example in the figure, the signal S obtained in adjacent horizontal scanning periods
By adding o and Sol, only the luminance component SDO (hereinafter referred to as sy) is obtained, and by subtracting only the color component sM (hereinafter referred to as So).

However, this behavior only holds true when the vertical correlation is strong, even if it is only 1, and in other cases it is always incomplete separation.
The color component So remains in the luminance component SY.

The influence of residual components on images will be explained with reference to FIG. 4 and subsequent figures.

For convenience of explanation, as shown in FIG. 4, as the subject 7, we will consider a subject 7R with only red color and a subject 7B with only blue color.

Now, if a horizontal scanning line is imagined to include the boundary line 8 between the subjects 7R and 7B as shown by the dashed line, (N-
By scanning each horizontal scanning position from 1) to (N+2)t, signals SO1 to S04 shown in FIGS. 5A to 5D are obtained.

When the above-mentioned signal processing is applied to separate the luminance Sy and color components Sc from these signals SO1 to SO4, N
Since the signal processing for the −1 line and the N line and the N+1 and N+2 lines are vertically correlated, complete separation is performed, but the color component So is not separated between the N and N+1 lines including the boundary line 8. If complete, the color component So remains within the luminance SY band as shown schematically in Figure 6, and therefore, when the image is reproduced, the residual component becomes a bright spot as shown in Figure 7. It appears on the boundary line 8.

Therefore, when an image of a strip-shaped object extending horizontally as shown in FIG. 8A is captured, the horizontal boundary portion is reproduced in a jagged manner (FIG. 8B), resulting in deterioration of image quality.

This drawback is especially true at frequencies f o. This is noticeable when / is low.

In FIG. 7, n, n+1, . . . indicate horizontal scanning lines after vertical correlation for convenience.

The circuit of the present invention proposes a signal processing circuit in which no color signal remains in the luminance signal.

The present invention will be described below with reference to the drawings, but in this example, it is applied to a color imaging device as described above.

Therefore, the two input signals used are an IH-delayed signal (luminance fraction) and a non-delayed signal.

FIG. 9 is a system diagram showing an example of a color imaging device to which the signal processing circuit according to the present invention is applied, in which a subject 7 is projected onto a CCD 1 via an optical lens system 9 and a color filter 5, respectively. The obtained color imaging signal So is supplied to an addition circuit 12 and a subtraction circuit 13 together with an output via a delay circuit 11 which separates the multiplexed signals.

Therefore, the brightness component Sy is obtained from the addition circuit 12, and the color component So is obtained from the subtraction circuit 13.

Of course, the separated luminance component SY may include residual components due to incomplete separation as shown in FIG. 6 depending on the content of the subject 7, but in the present invention, the luminance component S
y is separated into a reduced component and a Takagi component where at least a color component exists, and if a residual component exists, the luminance component from which the Takagi portion is removed is used as the luminance Sy.

Therefore, the unselected luminance component Sy is filtered by the low-pass filter 14.
After only the desired low-frequency component SDL is extracted, the low-frequency component SDL is supplied to the adder 15, and this low-frequency component SDL is
is supplied to the subtracter 16 and processed, so that
A high frequency component SDR of the luminance component Sy is obtained.

The high frequency component SDH is supplied to the IH delay circuit 17, and then supplied to the signal processing circuit 20 together with the non-delayed output, and an output sH related to the presence or absence of the residual component is extracted.

Although the operation of the circuit 20 will be described later, the output SH of the circuit 20 is combined with the above-mentioned low frequency component in the adder circuit 15, and this combined output is used as the luminance component S Y / in subsequent circuit processing. .

Therefore, if this luminance component is supplied to the matrix circuit 21 together with the demodulated output of the color component, the output terminals 21a to 21
Desired color video signals from c, for example, NTSC luminance signal Y and color difference signals (R-Y), (B-Y)
This is something that can be obtained.

In the figure, 22 is a delay circuit for compensating for the time delay caused by the intervention of the filter 4.

The delay circuit 23 interposed on the transmission path of the color component So is also used to compensate for time delay.

Also, 24.24 is a demodulation circuit with a different demodulation axis, and this is G+
For example, two color components (B-G) and (R-) are demodulated.

By the way, whether a residual component exists or not can be determined by considering the luminance component after vertical correlation processing.

In other words, if the image quality is degraded by the residual components, it should be applied to the n line and n+1 line after correlation processing, so that only the low frequency components can be obtained from the n line, and up to the Takagi component can be obtained from the n + 1 line. Only when this relationship exists, bright spots appear and the image quality deteriorates.

Here, each terminal 20A of the residual component signal processing circuit 2o,
If we classify the relationship between the signal components input to 20B,
It can be classified into four groups as shown in FIGS. 10A to 10D.

The figure shows a signal after correlation of signals obtained in adjacent horizontal scanning periods, and therefore a composite output SY of the adder circuit 12,
The signal relationship starts when the outputs Sy obtained from the n and n + 1 lines are both low frequency only (A in the same figure), and when both include high frequencies (B in the same figure), only one of them contains the high frequency. Cases (C and D in the same figure) can be considered.

Among these types, image quality deterioration occurs only in the case shown in FIG. If the composite output SY/ is made up of only the low-frequency component SDL, bright spots due to residual components will not occur, and deterioration of image quality (deterioration of resolution) can be prevented5. Therefore, the signal processing circuit 20 Terminal 20A,
The output sH is obtained only when the Takagi component supplied to 20B is present, and the circuit is configured as a circuit that performs a logical operation such that the level of the output sH depends on the level of the input signal, which has a small level.

FIG. 11 shows the basic circuit configuration of this processing circuit 20, which is configured to logically output two outputs SDH and SDHO which are in phase with each other.

Therefore, two logic circuits 25A and 25B are provided, and signal polarity determination circuits 26A and 26B are provided, respectively.
is provided.

In this example, the discrimination circuit 26A,
26B is constructed, and logic circuits 25A and 25B are constructed of a pair of diodes 28a to 28d connected with opposite polarities.

Then, one logic circuit 25A performs positive logic, and the other logic circuit 25B performs negative logic,
These logical outputs SA and SB obtained by performing logic separately are combined in an AND-configured circuit 30 and then supplied to the subsequent combining circuit 15 as the output shH of the processing circuit 20.

FIG. 12 shows another example of the processing circuit 20, which is the 11th
This is a further simplified version of the circuit shown in the figure, which has four diodes D1 to D4 in a bridge configuration, and a logic circuit consisting of a Zener diode 34a and a resistor 34b between the connection point a and the power supply terminal 33. A series circuit 34 for operation is connected.

A series circuit 35 having a similar configuration is also connected between the connection point C and the ground.

Then, from the connection point PUtPL, output terminals 31a and 3lb
is derived.

Note that 36at36b is a resistor provided for discharging.

Signals SDRy SDR' are supplied to connection points b and d, respectively, and the voltage of power supply voltage VOOO1 is superimposed on these signals.

2. The operation of the signal processing circuit 20 configured as described above will be explained, and in this example, the embodiment shown in FIG. 12 will be additionally described.

However, the circuit conditions are determined as follows.

The Zener diode 34a, 35a has the same characteristics, its Zener voltage is Vz, and the current is IZ1 resistor 34b, 35.
It is assumed that the value of b is RO, the value of the resistors 36a and 36b is RD, and the forward voltage drop of the diodes D1 to D4 is Vf.

Therefore, the voltage between the terminal 33 and the connection point b is given by vb1*.

Since the voltage vb2 between the connection point b and the ground is also given by C and equation (1), the following relational expression holds true.

On the other hand, when the signals SDH and SDI4/ are both zero, a voltage of +VOO is applied between the connection point b and the ground, so based on these conditions, the diode bridge is balanced and the outputs SA and SB are zero. be.

That is, when signals SDRjSDR' are not input together, the logic output becomes zero.

If the operation of the circuit 20 including this logical operation is organized, it will be as shown in Table 1.

Next, let's explain some typical logical operations.

1. When only the positive signal SDR' is input, the diode D4 is turned on and a current according to the signal SDR' flows, and the current IZ increases through the Zener diode 35a, but the Zener diode 35a In order to maintain a reverse bias state, the voltage Vz between its terminals is constant.

That is, even if current Iz flows, no output is obtained at terminal 31a, which is the same as a no-input state.

The same applies to the case where the positive signal SDH is supplied only to the terminal 20A, so the explanation thereof will be omitted.

Contrary to the above, when a negative signal SDR' is supplied to the terminal 20B, the diode D3 is turned on;
Although current Iz flows through 4a, since point pU is pulled to the negative side, the reverse bias of Zener diode 34a only becomes deeper, and the output does not change.

Therefore, the output sA is zero. In this way, the signal SDH
There is no change in the output even if either one of tSDH' is input.

The same holds true even when the signal SDH*SDH' of opposite polarity is supplied.

For example, considering the case where a negative signal SDR is supplied to the terminal 20A and a positive signal SDn/' 75 is supplied to the other terminal, in this case, the signal SDR causes the diode D1 to be switched on, and the arrival of the other signal SDR' causes the diode D4 to be switched on. Although each of these is turned on, the Zener diode 34a,
Since the operation is in the direction in which 35a is reverse biased, the outputs sA and sB are both zero based on the above-mentioned reason.

When the signal SDH t SDH/ is input in the same phase state, the following output is obtained.

1. When both positive signals SDH and SDR' are input, diode D4 turns on in the case of SDR <SDR', and since the potential at point b is lower than the potential at point d, diode D1 will turn on.

Therefore, as mentioned above, the output sB does not change when the diode D4 is turned on, but as a result of the diode D1 being turned on, the potential at point a increases, and this causes no forward voltage to the diode 34a. - Since Ias is applied, the Zener effect of the diode 34a is lost.

Therefore, the potential at point PU changes in accordance with the level change of signal SDR, and thus output sA corresponding to signal SDR is obtained.

When SDH'<SDR, the output sA based on the signal SDR'
is obtained.

When the signals SDH t SDH/ are both negative, the diodes D2 and D4 are turned on, and the output S A psB corresponding to the signals SDH and SDHl is generated based on the turning on of the diode D2.
It is easy to understand what can be obtained.

FIG. 13 is a diagram for explaining the operation described above in the simplest manner, and shows the case where the signals SDH and SDHl are replaced with Huo sine waves.

Therefore, it is shown that the output sH shown by diagonal lines is obtained from the circuit 20.

As described above, the signal processing circuit 20 for the residual component is configured to produce an output only when the in-phase signals S DH t S DH' are input together, that is, only when the input relationship shown in FIG. 10B is satisfied. logical operations are performed.

Therefore, if the residual component exists on the Takagi side of the luminance signal Sy, an output can be obtained in which the residual component is effectively removed.

Note that the example explained in the past and present section is a consideration of a model-like object 7 as shown in Figure 4. Even if the subject shown in FIGS. 14 and 15 is imaged instead of using such a simplified pattern, the present invention can effectively remove residual components and prevent image deterioration. It can be prevented.

To explain from the example of FIG. 14, that is, the vertical stripe subject, when signals corresponding to the n line and the n + 1 line are input to the processing circuit 20, sH=o as described above. Therefore, the luminance component SYI becomes only the low-frequency component, and in the case of the n + 1 line and the n + 2 line, both include the Takagi component, so the output sH is obtained, and therefore the luminance component SY/ is included in the high frequency component 1.

The same applies to lines after the n+3 line.

Therefore, in the first contour map of a vertically correlated object (a striped pattern), only the edge existing between lines n and n + 1 is not reproduced, but thereafter it is completely reproduced. There is no problem at all even if such signal processing is applied.

Next (in the case of a subject with a diagonal pattern as shown in Fig. 15, the vertical correlation is weak, but even if such a subject is imaged, for the same reason as mentioned above, the n line and n +
Only the outline between one line is not reproduced, and the reproduced image is not affected at all.

Therefore, no matter what pattern the object 7 has, it is possible to remove jaggedness that occurs in the horizontal contour.

As explained above, the present invention has a logic circuit that performs a special logic operation, that is, the signal processing circuit is configured so that an input with a small absolute value is output only when the input is in the same mode. Therefore, the circuit of the present invention is extremely suitable for application to the signal processing circuit of the color imaging device mentioned at the beginning.

In other words, if the circuit of the present invention is applied, even when capturing an image of an object including a boundary part (pattern, etc.) extending in the horizontal direction,
Since residual components can be reliably removed, there is no deterioration in image quality, and the device has a great feature of being able to always reproduce high-quality images.

This is only one example of the structure of the color filter 5 shown in FIG. 2, and the selection of transmitted light etc. is arbitrary.

Since the imaging apparatus can be constructed using not only one CCD 1 but more than one CCD 1, it can of course be used in this case as well.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a solid-state image sensor used as an image sensor, Fig. 2 is a partially enlarged plan view of a color filter, and Fig. 3 is an example of a color image signal including the phase relationship of color components. The frequency spectrum diagram shown in Figure 4 is a diagram of a model object.
Figure 5 is a frequency spectrum diagram of the color image signal obtained by imaging the subject in Figure 4, Figure 6 is a frequency spectrum diagram of part of the signal after signal processing, and Figure 7 is the reproduced image of Figure 4. 8 is a diagram for explaining general signal processing, FIG. 9 is a system diagram of main parts showing an example of applying the circuit of the present invention to a color imaging device, and FIG. 10 is a diagram showing vertical correlation processing. The later frequency spectrum diagram, Figures 11 and 12 are connection diagrams showing an example of a signal processing circuit, Figure 13 is a diagram for explaining its operation, and Figures 14 and 15 are other examples of subject patterns. FIG. 1 is a solid-state image sensor, 5 is a color filter, 20 is a signal processing circuit, 17 is a delay circuit, 21 is a matrix circuit, 24A,
24B is a color demodulation circuit, 34.35 is a series circuit, D is a bridge, and 30 is a synthesis circuit.

Claims (1)

[Claims] 1. Separate the luminance signal obtained from the color solid-state image sensor into a low frequency signal and a high frequency signal including the sampling frequency,
The levels of this Takagi signal and a signal obtained by delaying this Takagi signal by at least one horizontal scanning period are compared, and only when both exist, the above-mentioned high-frequency signal is added to the above-mentioned low-frequency signal to form a luminance signal. signal processing circuit.