JPS5837897A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease the number of component elements and bit lines, by constituting a memory cell with a storage node, an MOS transistor which selects an address between data lines, a data holding MOS transistor which is controlled by an MOS inverter, etc. CONSTITUTION:A work line WL is set at a high level (''1''), and an MOS transistor TRQ3n of an address selecting E type n channel is turned on. A storage node N is set at a high level when a data line BL is set at a high level. The output of a CMOS inverter I provided with E type p and n channel MOS TRQ2p and Q2n which use the node N as the input is inverted to a low level. Thus a data holding MOS TRQ1p of E type p channel is kept on even after the TRQ2n is turned off. Then ''1'' is stored in the node N by the 1st reference potential VDD. In the same way, ''0'' is stored. Thus 4 MOS TRs and a data line can form a memory cell with a reduction of both the component elements and bit lines. As a result, the density is increased for an RAM, etc.

Description

[Detailed description of the invention] Akira Hongo is in charge of semiconductor storage devices ζ at Mob@.

Especially static lid random access memo 9 (1A
M) regarding the memory cell structure.

The memory cell of the conventionally known state-refiRAM is usually composed of six Mo1) transistors as shown in the first example, one Mo8 transistor and one storage carrier. Dynamic [RAM
The number of transistors is large (required and 2
The disadvantage is that it requires several bit lines.

The present invention provides a suftic type semiconductor memory device having a memory cell structure that overcomes the above-mentioned drawbacks and enables higher density.

The memory cell in the present invention is composed of four MOI transistors and one resistor, and has a data line (bit line).
The configuration is such that only one piece is required.

That is, the storage node is connected to the first reference potential via the data holding MO8 transistor and to the second reference potential via the resistor, and is connected to the MO51 inverter Δ-input which serves as the storage node input in parentheses. 1. M08 for data retention
A memory cell is constructed by connecting an address selection MO8) transistor controlled by a selection line (word line) between a storage node and a data line. Therefore, according to the present invention, since the number of constituent elements of the memory cell is small and the number of bit lines is reduced to one, it is possible to achieve high density opening of the static type RAM.

The present invention will be explained in detail below. FIG. 2 shows a memory cell of one embodiment, in which a storage node N is a memory cell for overnight storage.
The lid Pf is connected to the positive power supply potential VDD which is the first reference potential via the transistor Q1p, and is connected to the ground magnetic potential Was which is the second reference potential via the resistor R. Then, the potential of the storage node f-N is changed to a CMO8in Δ-
It is inverted by the transistor I to control the M08 transistors Q and p. Also, memory no PN and bit line B
A 1li1 channel MO8) run star Qsn for address selection is connected between L and R, and its r-) is controlled by a word line WL.

The operation of the memory cell configured as described above will be explained as follows.

First, when writing 11'' (high level) to memory node PM, bit line BL'4: 'l't: word line WL is
1g&d. At this time, MO8) Ranjimeta 93 is turned on and the storage node N becomes 111, and this storage node N
The output of the CMO8 inverter 1 which inputs 1 is 101. Therefore, MO8) transistor Q s W is turned on, and the positive current [i4
The 111 state of storage node N is maintained by VDD.

Further, when writing 601 to the storage node N, the bit line BL is set to 101 and the word line WL is set to 111. At this time, the memory node PN becomes 601 and the output of the CMO8 inverter I becomes 111, so the MO8 transistor Qtp turns off and the g8 node N becomes 1 from the positive power supply potential VDD.
On the other hand, the voltage is maintained at 10 lb by the resistor R. A read operation can be performed by connecting the pit @BL to the sense circuit and setting the word line WL to 11''.

As described in 1 below, 11 static type goosenecks M according to this embodiment
This memory cell has a small number of components and does not require two bit lines like conventional memory cells.
Very suitable for high-density integration. Note that by using, for example, a polycrystalline V9 film as the resistor R, the small surface WI
Although it is possible to achieve a sufficiently high resistance, it is also advisable to use a closed ta channel M08 transistor.

FIG. 3 shows a memory cell according to another embodiment of the present invention, and the difference from FIG. 2 is that the first reference potential is set to the ground potential V.
1% The second reference potential is set as a positive in potential VDD, and the data retention Mo5) is used as a lanzo star for m2 double channel MO8)
It uses Lanzosta Q and Maro. In this embodiment, the bit line Bl is 11'' and the word line WL is 11''.
When 11@ is looked at the storage node N as , the transistor Qi is turned off and the moment is held, and the C
Connect the cut line BL to 101. When 01 is written with the word condensed milk as 111, transistors Q and a are turned on and the data is held as well. This embodiment also provides the same effects as the previous embodiment.

In the above embodiments, a CMOS inverter is used as an inverter, but an I/DMO II inverter, for example, may also be used. Figure 4 shows the CMO8 input Δ-input I in Figure 3.
The part of 1ro I channel M08 transistor Q snow n and D
B/ consisting of type n-channel MO8 transistor Q*1'
This is an example in which the DMOS input Δ-I' is replaced. According to this embodiment, not only the same effects as in FIGS. 2 and 3 can be obtained, but also higher density integration is possible because all the constituent elements are blind channels.

As described above, according to the present invention, the number of constituent elements of a memory cell is small, and only one bit line is required, so that it is possible to achieve high density RAM.

[Brief explanation of drawings]

FIG. 1 shows a memory cell of a conventionally known static type RAM, FIG. 2 shows a memory cell of one embodiment of the present invention, and FIG. 3 shows a memory cell of another embodiment. 184 is a diagram showing a memory cell of still another embodiment. N...Storage node sQ@p...WfiP channel M
O8 topunzoster (for data retention), l...resistance, work...CMO8 (amperta, Q, m...B fi
n-channel MO8) transistor (for address translation), WL-
°°Word line (selection line), BL...bit *Cy″-
1i1i), VDD...Positive power supply potential, ■ss...
Ground potential mQ1''...E-type n-channel M08 transistor (for data retention), II...B/DM O8 inno-doctor. Applicant's agent: Takehiko Suzue, patent attorney! Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) A data holding Mo8 transistor and a resistor connected between the storage node and the first and second reference potentials, and the data holding Mo8F transistor whose input end is connected to the nth memory node and whose output end is the data holding Mo8F transistor. a connected Mol inverter, and an address selection M connected between the storage node and the data line and controlled by a selection line.
1. A semiconductor memory device comprising a memory cell configured with an O8 transistor. (2) The first reference potential is the positive power supply potential, the second reference potential is the ground potential, the Mo8F transistor for data retention is a molded P channel, and the M08F transistor for address selection is lil.
fJ * channel and Mo8 (y park is 0 MO
The semiconductor memory device according to claim 1, which is an 8 inverter. (3) The first reference potential is the ground potential, the second reference potential is the positive power supply potential, the Mo8 transistor for data retention and the Mo8 transistor for address selection are l1ls channels, and 1 MO8 in Δ-1 is a CMOB Mol inverter patent. A semiconductor memory device according to claim 1.