JPS5836550B2 - bangumiyoyakuuchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic program reservation device having a storage device,
In particular, the present invention relates to a program reservation device that can select in advance whether or not a program in a storage device should be automatically deleted after the program is executed.

Program reservation devices include mechanical devices that set switches or pinboards based on the desired program;
There is an electronic type that has a writable storage device and a program is written into this storage device by inputting a switch.

In any case, the program once entered is not necessarily needed every day.

Rather, it would be very convenient if you could input programs that are scheduled at a fixed time every day, and programs that are only for that day.

In this respect, mechanical devices are suitable for once-set programs and for repeatedly watching the same program every day, but it is difficult to input a program only once.

In the electronic type, it is possible to easily perform a one-time program by erasing the program in the storage device after execution.

The present invention provides a program reservation device in which it is possible to select whether or not to erase a program in a storage device after execution when inputting a program.

The following description will be made regarding a television receiver program reservation device as an example.

Hereinafter, the present invention will be referred to as a television receiver (hereinafter simply T.V.).
An embodiment applied to a program reservation device (hereinafter referred to as "the present invention") will be described in detail with reference to the drawings.

What is a program reservation device? V. automatically selects a channel, etc. according to a predetermined program, or tunes a program such as T. V. It controls the operation of the

In particular, the program reservation device of this embodiment is an all-electronic device.

First, the operating method and outline of this device will be explained.

FIG. 1 shows a T. V.
The screen and channel control section are shown.

15 is a switch to turn on and off the power of this set (
The switch is hereinafter simply referred to as SW), and now this power supply S
W1 5 PULI, -ONL, 1 channel human power S
When W■ is pressed, channel 6 is received and the image is displayed on the screen 16.

This normal image receiving state is called Normal mode (hereinafter simply referred to as N mode), and is a general electronic selection mode.
V. As with the set, by pressing and inputting a desired channel from one channel group, the desired channel is selected and imaged.

17 is in N mode, and the time of a clock device (hereinafter simply referred to as a clock), which will be described later, and the selected channel position number (
(hereinafter simply referred to as channel number or channel) is displayed in white on the screen.

This display is controlled by the Display SW 3 so that it is displayed and erased cyclically.

4 is a Program SW which specifies a program mode.

When SW4 is pressed, the N mode switches to the program mode (hereinafter simply referred to as P mode), the device is set to accept programs, the video signal is cut off, only internally generated character signals are displayed, and the contents of the program are displayed on the screen. You can program while viewing the screen.

At this time, the S which had the function of channel selection in N mode
W group 1 is switched to function as a program data SW.

SW group 1 has common input and output in N mode (■/0 common)
The designated channel is held and selected by feedback, but in modes other than N mode, this feedback loop is cut off and only input is accepted.

The program input method is performed by sequentially inputting the SW group 1 arranged in a circle in correspondence with the clock face.

For example, if you first press ■, the 2 o'clock data will be input and only "2:" will be displayed on the screen, then when you press ■, 30 minutes will be input and the display will become J2: 30J, and the third input will be specified. For example, if you press ■, channel 8 will be input and "2:30-8J" will be displayed on the screen, and one program will be completed.

The program content of "2:30-8" means that when the clock time, which will be described later, reaches 2:30, the comparison circuit, which will be described later, will operate and automatically receive the image of channel 8 based on its operation signal. .

This automatic switching of channels according to the program content is simply called program execution.

As mentioned above, program input is performed by cyclic input of hours, minutes, and channel numbers in ternary format.
One program has been completed and the designation for the next program is St.
This is done by changing the writing position on the screen using the ep SW6.

This writing position is specified by displaying a "-" symbol on the screen.

FIG. 2 shows an example of a programmed screen.

As shown in the figure, the number of programs for this device is AD1, AD2, . . . AD16, taking into account the range of the display screen.

The symbol "1" is displayed at AD1, indicating that program input is possible at this position, and -2: is displayed when ■ is pressed from SW group 1 in FIG.

If you want to change the input of the program, use the Era button in Figure 1.
Clear the memory of the address specified in step 1 with se SW7 (nothing is displayed), and enter the new hours, minutes, and channel number in that order, or use the cyclical input order. You may rewrite while looking at the display.

The OFF channel number indicated by AD7 in Figure 2 is the first
This does not mean turning off the power to the set shown in FIG. 15, but simply means turning off when the set is in a preheated state, and is input using the OFFSW shown in FIG. 1 and FIG.

The AD display shows a timer program for turning on the VTR, etc., and is input by pressing Timer SW 1 8 in the same way as the channel number in FIG.

This timer information is T. V, channel program AD
, , AD2..., etc., and are handled separately from T. V se'
,/} Information for turning on and off the external SW.

AD,6 shows an example of a timer OFF time program.

Note that the time display of this device is a 12-hour display, and the morning and afternoon times can be specified as shown in Figure 1 AMSW1 1, PMSWI.
Specified by 2.

The display of the program contents in the P mode and the time display of the clock shown in FIG. 219 are performed using predetermined colors for morning and afternoon.

The program is executed by comparing the input program time data with the time of the clock that counts the reference clock. Unless there is a program input at the same time, such as AD1, AD4, AD, o in Figure 2, etc. , the order of execution is not specified depending on the display position.

Note that incomplete program input, such as a program without channel designation, will be ignored and not executed.

Regarding the programs displayed on the screen (see Figure 2), this device will execute the programs programmed in the left side AD, ~AD8 of the screen (hereinafter simply referred to as the left program) every day unless the program is changed. The circuit is configured in such a way that it is predetermined in advance that the programs programmed on the right side AD, -AD, 6 of the screen (hereinafter simply referred to as right programs) will be erased after execution, although they will not be erased.

The processing of a plurality of program inputs at the same time is prioritized by determining the order of execution in advance.

In other words, when programs are input at the same time on the left and right sides, the program on the left side takes priority, and when programs at the same time on the right side only are input at the same time, the program at the top of the screen takes priority.
Similarly, for program input only on the right side, it is determined that the program located at the bottom of the screen has priority.

Next, when the clock is set in N mode, T
By pressing the ime Set/Start SW9, the mode is switched to the time set mode (hereinafter simply referred to as TS mode).

When the N mode is switched to the TS mode, the LED indicating the TS mode (stop state of the clock circuit) shown in Figure 18 lights up, and at the same time the video signal is cut off and the time, that is, 19 in Figure 2, lights up.
only will be displayed.

In this TS mode, SW group 1 in Figure 1 is switched to the function of the time input data SW as in the P mode, and the time is set by pressing the SWs in the order of hours and minutes. This is done by cyclic input.

For example, if you specify either morning or afternoon using SW11 or SW12 and press ■1■, "l:j - "1:1
It will be displayed in color 5j.

Once the time has been set, the time for starting the clock is started by pressing SW9 in FIG. 1 again.

The transition to the start state can be performed in two ways: directly from the TS mode, or after returning from the TS mode to the N mode.

Although the outline has been explained above, the SW used in this device is
Except for the System SW for specifying whether or not to perform the program execution operation shown in FIG. 13, push-button SW structures were used.

This device is a C-M electronic circuit, excluding external accessories such as SW.
This is realized with a single-chip LSI OS.

Therefore, the system structure has been designed in consideration of a reduction in the number of elements, higher integration, and reduction in power consumption.

Due to the degree of integration, the circuit configuration of the counter etc. is mainly considered to be a dynamic configuration, and the clock system is a clock system from a clock circuit, a T. V. Two systems of clock systems, such as synchronization signals, are used, which are asynchronous to each other.

Also, when the TV set is powered on, the LSI is powered by the set's AC power supply, and when the set is powered off, the clock and program memory are kept running using the DC battery power, while the transistors in other parts are inactive. It is structured like this.

That is, the two power sources are automatically switched and used by turning the power ON and OFF.

This system and its operation will be described in detail below with reference to block diagrams and specific circuit diagrams.

In the following explanation, we will focus on FIG. 1 and FIG. 3, which is a block diagram of the entire LSI system.
The explanation is based mainly on negative logic.

FIG. 3 is a block diagram showing the overall structure of this system.

In the figure, 58 is a switching circuit for each mode described above, and 6
1 is a normal feedback circuit, and a specific circuit thereof is shown in FIG.

When the Normal SW5 in Fig. 1 is pressed, a pulse signal is generated and the Normal
a l is sent to the feedback circuit 61, and further connected to the connection line 6
0 to the mode switching circuit 58.

At this time, the N output of the mode switching circuit 58 has a logic "'".
An N signal of i''vss level (L level) is obtained, and this signal is fed back to the base of the P-channel transistor 27' of the mode switching circuit 61 via the connection line 59 as shown in FIG. ’ is turned ON.

Therefore, the Normal I/O common line 27 has the logic "'0".
“The level becomes VDD level (H level) and N mode is maintained.

Next, use the Program SW in Figure 1 to program.
When 4 is pressed, a signal of ``0'' is generated on the connection line 28 in FIG. 3, and an output of ``I n'' is obtained at the P output in FIG. 4.

At this time, the N output becomes "0" at the same time.

Therefore, the transistor 27' is turned off and the output line 27 becomes "1".
'', and the N mode is switched to the P mode.

To switch from P mode to the next mode, see Nom in Figure 1.
This is performed after once returning to N mode by al SW 5.

That is, for example, when transitioning from P mode to TS mode, the mode is returned to N mode once, and then the transition is made to TS mode.

To shift from N mode to TS mode, by pressing SW9 in FIG. 1, a signal is supplied by the trigger pulse generation circuit 52 via the signal line 26 in FIG. 3 to generate a trigger pulse, and the connection line 57 is This is done by sending the trigger pulse to the mode switching circuit 58 via the mode switching circuit 58.

Figure 4 57' is a binary flip-flop circuit that receives a trigger pulse when P = 46 1 11 and operates with that pulse. When the output Q becomes ``1'', it enters the TS mode and at the timing of g1, N = ( I Q ?+.

The setting is completed using the clock time setting method described above,
To start the clock, the SW shown in FIG. 1 is pressed again to generate a trigger pulse and the flip-flop is inverted again. At this time, the clock becomes TS21" and the clock circuit starts.

As is clear from Figure 4, this switching to the start can be done directly from the TS mode, or by switching once to the N mode, checking the time displayed from the video signal on the screen that is receiving the image, and performing the start operation in accordance with the time. It is structured like this.

The signal gs + g2 in FIG. 4 is a timing signal that is used by taking out appropriate signals with mutually different phases from the clock timing generation circuit 45 in FIG. be.

Fig. 3 163 [Signal that becomes “0” in rs mode,
This signal lights up the LED 8 in FIG. 1 to notify that the clock has stopped operating.

When the clock starts, the signal 163 in FIG. 3 becomes "'1" and the LED goes out, indicating that the clock is running.

Ini 1 in FIG. 4 is T. V. Set PULL-ON
This is an initial condition setting signal for setting the circuit to a predetermined state when the SW is turned from OFF to ON.

This Ini 1 signal is A when PULL-ONSW is ON.
"'1" several msec later than the stop of the C'iJ source
This is the signal.

When the Ini 1 is turned on, the mode is automatically set to N mode and the clock is set to the start state.

In addition, the broken line in FIG. 4 indicates the N mode I/O in FIG.
This shows the feedback circuit of the O terminal.

SW group 1 in Fig. 1 is in N mode for channel selection sw, p.
It becomes a data manual SW in mode and TS mode.

FIGS. 3 29 to 33 show I/O buses corresponding to the SW groups, and FIG. 3 62 shows a feedback circuit for each channel common to I/O in N mode.

FIG. 5 is a detailed circuit diagram of this feedback circuit 62 and latch circuit 66.

Feedback circuit 62 includes two P-channel FETs 250 and 25 between each I/O bus 29 to 33 and ground.
It has an AND circuit formed by connecting 1 in series.

An N signal is supplied from the mode switching circuit 58 to the gate of one FET 250 of each AND circuit,
A feedback signal is supplied to the gate of one of the FETs 251 from a channel decoder 72, which will be described later.

That is, each AND circuit ANDs the N signal and the feedback signal.

Assume that the SW in FIG. 1 is pressed in N mode and one channel is being received.

At this time, the flip-flop R of the latch circuit 66 in FIG.
-81 Q becomes 41 1 11, R-82, ~R,
-813's Q outputs are all "0".

The output bus 67 of this latch circuit 66 is as shown in the figure.
1], [2]...[13], and serves as an input to the encoding circuit (hereinafter simply referred to as encoder) 68 shown in FIG.
encoded into bits.

Encode output is 69. and channel register 70
is input and its 4 bits are held.

4-bit signal 71 held in channel register γ0
is a channel decoding circuit (hereinafter simply referred to as a decoder) 7
2 and is decoded.

The decoded output is fed back to the AND circuit of each channel via the bus 73 as feedback signals IF, 2f, . . . , 13f shown in FIG.

That is, due to the Q="1" signal of R-81, only 1f becomes "1" in the decode output bus 73, an AND circuit is established, and its feedback loop is established, and I C!
The H terminal holds "0" and one channel is selected.

Next, when ■ in FIG. 1 is pressed, R-82 in FIG. 5 is set and its output (2t75i' becomes "1").

At this time, the 11th ma is still "'1".

[1] of the latch outputs of the latch circuit output bus 67
, [2] become "1", and the two channels are pressed.

This latch circuit output bus 67 is connected to the exclusive logic circuit 7 in FIG.
It also serves as the input for 4.

This discharging logic circuit 74 is a circuit that detects when two or more channels are pressed, and if two or more latch outputs 67 are "1", a reset signal 7 is sent to the latch circuit 66.
Generates 5.

The latch circuit 66 is completely reset by this reset signal 75, and as described above, the latch circuit 66 is sent to the feedback bus via the bus 67, encoder 68, bus 69, channel registration register 70, and bus 7L7' coder 72 shown in FIG. 1f in 73 becomes "0" and the 1 channel previously held is cut off.

This operation is instantaneous, and normally the SW in FIG. 1 is still pressed at the end of this operation.

Therefore, among the outputs of the latches that have all been reset once, ['s. That is, only 2f of the channel decoder output bus 73 becomes +1 1 11, and even if SW is removed, the I/O common line 30 of 20H still becomes "0" and 2 channels are maintained and imaged.

Note that OFF is treated as a 13-channel signal for convenience, and 13f of the output bus 73 serves as a feedback signal to the OFF channel.

This OFF channel is T. V. O in the preheat state of
This becomes a signal indicating FF.

For channels selected in N mode, the I/O common terminal is “
'0'' and holds the channel, but this channel terminal is coupled to a signal receiving transistor and a tuning variable resistor to control the electronic tuner.

Therefore, selecting a channel actually means selecting the channel position S-W, and the image received on that channel is the image of the channel preset-tuned by the variable resistor.

FIG. 6 shows a detailed circuit diagram of the encoder 68, channel register 70, and write register 85 shown in FIG.

In the figure, [1], [2]...[13] are latch outputs of the bus 67 in FIG. 3, and N is a signal indicating the N mode, which is "1".

CI and EP are each “t O
The signal 91 is t+ 14 1 11, and CI=1"EP"0" except during execution.

Reference numeral 100 in FIG. 6 indicates 4 bits of channel information among program data sent at read timing, which will be described later.

For manual tuning in N mode, encoder 68 output 4 bi
t 5 9 is read and held in the static registers 70a to 70d at σ in the timing signal diagram, and the output 4-bit bus 71 of the register is sent to the channel decoder 72 in FIG.
The predetermined channel is held and selected as described above.

This 4-bit circuit 70a to 70d is the channel register 70 in FIG.

Note that 70e is a register for indicating whether the band is UHF band or VHF band, and is for displaying N mode.

Automatic channel selection by executing the program is described in C.
Program channel information 3rd by I/EP signal
Figure 1 0 0 4 bits in this channel register 7
This is done by writing to 0.

The program is read out using a read address, which will be described later, and a comparator circuit compares the clock time and time data of the program, and if they match, a match pulse is generated.

This coincidence pulse takes about 30μs due to the comparison timing.
Since it is only an ec pulse, it is impossible to write channel information to the channel register 70 and switch channels using this pulse due to the time constant of channel input.

Therefore, this coincidence pulse generates an EP with a pulse width of approximately 950 μsec until the next comparison timing, and a CI signal with a length of approximately 15 mSec to ensure sufficient time for the channel to switch and stabilize. Create something.

A coincidence pulse control circuit 90 shown in FIG. 3 is a circuit that generates CI and EP signals based on the coincidence pulse from the time comparison circuit 93.

When a coincidence pulse is now generated from the comparator circuit 93, the coincidence pulse control circuit 90 outputs CI=0 "EP1" at the above-mentioned time.
1” occurs.

As shown in FIG. 6, the encode input to the channel register 70 from the encoder output bus 69 is stopped by this CI signal, and 4 bits 100 of program channel information are input to this register at the timing of the EP signal.

At this time, the channel register 70 holds program channel information, and its output bus 71 is input to the decoder 72 and fed back to that channel of the input feedback circuit 62 to hold the channel selection.

If the channel selected by executing the program differs from the channel selected before executing the program, the feedback signal of the previous channel is cut off and becomes "0", so the I/O terminal of that channel has a certain time constant. “l
” and that channel will be posted.

On the other hand, by executing the program, the channel register 70
The channel written to is still held, and when CI goes to ``1'' after being ``0'' long enough for the previous channel to turn off, the executed channel is written back to register 70 from encode 68 and the file is A completed back loop is established, and that channel is held and selected.

Let's assume that channel 3 is now being received.

At this time, when this N mode is switched to P mode or TS mode for programming or time setting, the feedback circuit 62 shown in FIG.
The feedback signal of is turned off and the I/O terminals, which do not hold any channel, are set to only accept data.

However, the channel register 70 still stores and holds the three channels in the N mode, and only the output 73 of the channel decoder 72 has 3f as "1".

When switching from P mode or TS mode to N mode again, the three channels stored in channel register 70 will be received.

Next, data writing in P mode and TS mode is done using Program SW4 and Time
This is done by pressing Set/Start SW 9 and using the SW group in FIG. 1 as the data input SW.

When the P mode or TS mode is selected, the N signal in FIG.
/O common state) is turned off.

Therefore, no channel selection operation is performed, and the circuit is set to receive input data such as programs and time settings.

If you press, for example, ■ from among the SW group in FIG. .

The trigger pulse generation circuit 64 includes an OR of the input bus 63, a chattering prevention circuit, a trigger pulse generation circuit, and the like.

If two or more input SWs are considered to have been pressed at the same time, the output 7 of the discharging logic circuit 74 is
5 resets the trigger pulse generation circuit 64 and the launch circuit 66 and stops the generation of trigger pulses from the trigger pulse generator 64, so that it is assumed that no data is input and the data is controlled not to be written.

The main time chart of data writing in P mode is shown in Fig. 7, and the respective timings are based on the basic clocks φ1 and φ.
It operates as a signal synchronized with 2.

The first area shown in FIG. 7 is an area in which time data of program contents is written.

Now, if SW ■ in FIG. 1 is pressed, the OR circuit of the trigger pulse generator 64 generates an output shown at 7th 64'. A trigger pulse is output.

This trigger pulse 65 is supplied to a timing pulse generator 82 in FIG.

The timing pulse generator 82 obtains the trigger pulse 65 and the synchronizing pulse 166 from the memory timing generator of the jet pulse generator 89 to generate write timing pulses 83, 162 and the Set 1 pulse 84 (Set pulse 184 is It is input to the write register 85 together with the output 69 of the write encoder 68 .

The 4-bit output of the write encoder 68 is "0001" in order from the high-order bit.

As shown in Figure 6, the 4-bit data is
At one pulse timing, write register 85a,
85b, 85c, and 85d.

In the case of time information, AM/PM information is written into the register 85e from the flip-flop circuit 46 of FIG. 3 through the output line 47.

Overall, 5 bits of time information is the write timing pulse WP8 generated by the timing pulse generation circuit 82.
3 is outputted to the output line 86 as serial data at a predetermined read timing, and the data write circuit 8 of FIG.
7.

Write data from write register 85 to write circuit 87
The timing to write to is Timing Pu in Figure 6.
lse, and is specified by a digit pulse, which will be described later.

When the reading of time information from the write register 85 is completed during the "1" period of the write pulse WP84 shown in FIG. 7, the pulse shown in FIG. 7 162 is generated in the ternary counter 76 of FIG. The state of the advance counter 76 is switched from the hour writing state T to the minute writing state M "1" as shown in FIG. 77.

Next, minute information is written from the encoder 68 to the write register 85 at the timing of the Set 1 pulse 84, and serially read out to the data write circuit 87 at the timing of WP84.

Furthermore, at this time, the ternary counter 76 is switched to the channel write state OH "1", and the channel information from the encoder 68 is similarly read out to the data write circuit 87 via the write register 85.

The data read by the data write circuit 87 is written into the program memory 171 by the write/read ROM 1 69 shown in FIG.

Although its operation will be described in detail, the program memory 17
The time data is written to M1, and the counter 76 becomes M1 “1”.
When set to ``, the contents of the program memory in which the time has been written are displayed in color on the TV screen as ``1:''.

Although omitted in Fig. 6, the time 12 o'clock is displayed as 0 o'clock, so when @ in Fig. 1 is pressed, the high-order 2 bits of 85a and 85b in the figure are changed to "'" for hour and minute information. o o
” and input the data by essentially converting it to “o o o o”.

Further, in the second area of FIG. 7, minute information is serially read out from the write register 85 during the write pulse WP period, and when writing of the minute data to the program memory 171 is completed, the third area enters a state where channel information is accepted. However, in this case, the display becomes l-1:10J.

Furthermore, when the channel information is written into the program memory 171, "1:10-3" is displayed.

At this time, the counter will move to the first area,
This ternary T. M. The OH state changes cyclically in accordance with the number of inputs, and data are input one after another.

As described above, the SW group in FIG. 1 corresponds to the dial of a clock, and minute information is input in units of 5 minutes.

Looking at this amount of information input, for example, when the input data of SW ■ is encoded by an encoder and converted into 4 bits, it becomes "0101" in order from the high-order bit.

Separate these 4 bits into 3 bits and 1 bit, and
1 0 ", '1", and the lowest I bit corresponds to 0 minute and 5 minute in 5 minute units.

When this lbit is ``1'', it is considered as 5 minutes, and when ``'0'' is considered as 0 minutes, the first 3 bits are the information of the 10th place of the minute, ``010'' = 2
As a result, the input of ■ is separated into 2 and 5, and the display is 2.
Minutes are represented as 5.

Similarly, if we take SW input as an example, 8-“' 1000”
Therefore, it can be treated as 40 minutes by considering "io o" and "'0".

In this way, it is possible to input 2-digit minute information simply with 4 bits without the need for any other conversion.

The channel input data is 4 bits, but like the AM/PM at the time of time input, a signal indicating whether it is a UHF band or a VHF band is obtained from an electronic tuner, inputted as FIG. Add 5b
Treated as IT.

The channel display is “-3” and “12” in the VHF band.
", and for UHF channels, "U5
” and “U11” are displayed.

This added lbit sets the signal shown in Figure 6.
It is written to the write register 85e at timing l.

Reading from the write register 85 is carried out in correspondence with each digit of information, and the data is serially output as 86 in FIG. 3 starting from the l-th bit of the register.

This register 85 is a parallel-in/parallel-serial-out register, and a specific 1-bit ROM circuit structure is shown in FIG. 8a.

Note that these R and OM circuits are equivalent to the logic circuit shown in FIG.

The parallel output 175 of this resistor is not used in the P mode, and is data for setting the time of the clock.

As explained in detail above, this write register 85
is basically composed of 4 bits which input the encoder output, and for data added to these 4 bits that do not use this encoder circuit, another pit register is provided after the previous 4 bits.

This includes the AM/PM data and U/V data of this device, and if that information exists, 4 bits
+ 1 bit structure, and 5 bits can be handled as one news data, ■ digit.

As will be described later, when writing to the program memory, time and channels are treated as 1 digit and 5 bits.

Of course, 4bi is used for information that does not require additional bits.
Treat t as an l digit.

This method is an effective means in terms of circuitry because it can always read from the first bit of the 4 bits at a predetermined read timing.

FIG. 9 shows the bit structure of one program memory of this device and the digit structure corresponding to data.

FIG. 10 shows the digit pulse generator 89 of FIG. 3.

This digit pulse generator 89 is the program memory 1
A 5-bit timing pulse is generated.

FIG. 11 shows the digit pulse D of FIG. D2 + D
The waveform of 3rD4 is shown.

It is determined from the bit structure shown in FIG. 9 or the method of the write register 85 described above.

In this figure, the timer lbit is inputted by the SW18 in FIG.

In the program AD1 in Figure 2, the channel information is ignored during execution and the timer output is turned on.
In the program a, it means turning off the timer output.

As can be easily understood from FIG. 11 and FIG. 7, the read pulse of the write register 85 shown in FIG.
D2+OH-D3.

The encoder 68, channel register 70, mode switching circuit 58, etc. shown in FIG. 3 are implemented in an actual LSI by using a ROM structure or a clock synchronization gate to improve the degree of integration.

FIG. 12 shows a specific circuit of the data write circuit 87 shown in FIG.

Each input represents the timing signal and data input shown in FIGS. 6, 7, and 11 above.

The E input in the figure is a program memory erase signal inputted by the Erase SW7 in FIG. 1 and output from the chattering prevention circuit 50 in FIG. 3.

This erase signal completely clears the program memory at the address specified by "1", and is essentially 15b.
With the signal that writes "1" to the it memory, the display is erased and nothing is displayed at that position.

The meaning of essentially writing 41 1 97 is when viewed from the 173 signal in Fig. 13, which will be described later.
1 1”, this is cleared and “l
" has been written" means that "1111...1" has been written.

In other words, when erased, as shown in FIG. 13, the 15 bits of the memory cycle with all "0"s, but the signals read out and treated as actual data are all "0"s with 173 bits.
1″.

86 in FIG. 12 is the Timing Pu shown in FIG.
6 shows the serial data input read from the register by lse (see FIG. 6).

The outputs α and γ in Figure 12 are the data writing circuit 87 in Figure 3.
The output signal 88 is a write data signal for writing predetermined data in synchronization with the program memory lJi71.

As previously mentioned, the data 86 from the write register 85 is read by the time write state T. of the signal 97 shown in FIG. Each period 1 of minute write state M and channel write state CH
Digit pulse DI-D shown in FIG. 11 at 4 1 jl
4 and a write pulse WP are supplied, and written to the write circuit 87 at the timing of these pulses.

That is, when the digit pulse D1 is first supplied in the time write state T=“1 tt, the AND gate 871 of the write circuit shown in FIG. When time data 86 is inputted, this time data 86 appears at output α through AND gate 871 and OR gate 872.

This output α is used for writing and reading R, OM16, which will be described later.
9 to the program memory 171.

On the other hand, at this time, the pulse T. D, AND-4873 with WP as input is established, and its output is OR-4873.
- Appears on the output γ through the inverter 875.

That is, the output γ is generated during the period D. during which the 5-bit time data is written. It is 11 09+.

This γ1''0''' is the time data α as described later.
It serves to stop the circulation of data in the memory while it is being written to the program memory 171.

Next, when digit pulse D2 is supplied, the
8 7 1 is not established, but digit pulse D2,
An OR game 1876 with inputs D3 and D4 is established, and its output is an AND gate 877 and an OR game 87.
2 and appears in the output α.

The same holds true when digit pulses D3 and D4 are supplied, so the output α is always ``1'' during the period from digit pulses D2 to D4.

On the other hand, the output γ becomes "1" because the AND gates 873, 878, 879, and 880 all fail during the period of the digit pulses D2 to D4.

Therefore, in the period of digit pulses D2 to D4, the output α
, γ become "'1", and the program memory 1 has 5 bits of time data written during this period as will be described later.
Substantially, the code "1" is written into all the remaining 10 bits of 71.

This writing method is related to the display method, and has the purpose of erasing all data after the minute data when time data is written, so that it is no longer displayed on the display screen.

Next, when switching to the minute write state M, all the gates of the write circuit are inactive during the period of digit Hals D, so the outputs α are “0” and γ is “1”, and data is written in rows. However, in the period of the digit pulse D2, the AND gate 881 is established, and the input data at this time is passed through the AND gate 881 and the OR gate 881.
-872 and appears on the output α.

Also, at this time, the AND gate 879 with pulses M, D2, and WP as inputs is established, and γ=“0”.

Therefore, as in the case of time data, the circulation of data in program memory 171 is stopped and minute data is written into program memory 171.

This write is performed by converting the bits corresponding to the minute data in the program memory into which all "'1" has been previously written to the above minute data α.
This is done by rewriting .

After that, in the digit pulse D3 + D4 period, α=“
1'', r=“1”′, and all bits other than the time data are set to u I I+ and are not displayed on the screen.

Furthermore, in the channel write state OH, only when the digit pulse D3 is supplied is the AND gate 8
82 is established, and the channel data appears at the output α.

At this time, the AND gate 878 is set and γ=“0”, so the channel data is stored in the program memory 17 in the same way.
Written to 1.

As mentioned above, this input method is done in ternary, but now,
When inputting by pressing SW of 1SW group in Figure 1) and ■SW three or more times in succession, rl:J - {1:05'' → ``l:
05-IJ→"1:"→... will be displayed repeatedly, and the memory will be written accordingly.

As shown in FIG. 12, the write data for time channel information is written at α, but the timer data is written at γ based on the Tmr signal.

Therefore, the input of the timer is substantially input by a "0" signal.

As a result, this 15-bit memory is synchronized with the timing of WP, each digit is synchronized with WP, and the data written in each digit is written into the memory at a predetermined timing.

Note that this data write circuit 87 is constructed and realized by a ROM in order to improve the degree of integration in an actual LSI.

The clock device of this device is a general electronic clock that basically consists of a counter inside an LSI.

35 is an oscillator that generates a reference clock for a watch, and is composed of an external crystal.

The output 36 of the oscillator is counted by a pinary counter 37 consisting of multiple stages.

Figure 3 40 shows the basic clocks φ1 and φ for dynamic operation.
This is a clock generation circuit that generates 2 clocks.

Clock φ generated from the clock generation circuit 40 of this device
1, φ2 has a frequency of 32KHz, and the φ.
The phase relationship of φ2 is shown in FIG.

The output 38 of the counter 3T in FIG. 3 is input to a binary counter 41 and further counted down.

The output 42 of the counter 41 is a time for counting hours, minutes, etc.
It is supplied to the minute count circuit 43.

158 in FIG. 3 is a time store circuit, and the time data 176 which is the output of the hour and minute counter circuit 43 is sent to the output line 158.
The data is read and temporarily stored at the timing of the time read pulse supplied through the bus 159, and is output to the bus 159.

The time data output to the bus 159 is used for comparison and display with program time data.

The clock timing generation circuit 45 in FIG.
This circuit generates necessary timing pulses such as t+g2, and the output bus 44 of the hour/minute counter circuit 43 is used as an input.

The clock time is set in the TS mode, using the SW in Figure 1.
Group 1 switches to the time data manual SW.

In the TS mode, the counter 76 is a binary counter, and the data input SW group is regarded as a clock face, and data is input cyclically by inputting the time and minutes twice.

The data flow when setting the time is the same as the time and minute information input described above using the program input method.
The data of the parallel output 175 of the write register shown in the figure is input to the hour and minute counting circuit 43.

On the other hand, T. M. A cyclic signal (in this case, there is no OH) is input to this counter circuit 43 as 77 in FIG.
is input.

The hour and minute counter circuit 43 inputs data 175 to a presettable counter depending on the state of TM, and starts counting when the data input is completed and the clock starts.

Actually, first press 98W in Fig. 1 to set the TS mode (at this time, LED 8 lights up, indicating that it is in the TS mode) and turn off the video signal. Only the current time will be displayed on the V screen, and the clock circuit will stop measuring time.

Select either morning or afternoon using the SW shown in FIG. 11 and 12, and input the desired time.

If you press ■SW in FIG. 1 and input the time, "1:" will be displayed in the previously specified colors for AM and PM, indicating that the time has been input.

Next, press SW ■ to enter the minutes, and the result is “1:10.
J will be displayed and time setting is complete.

Now, if the above input of 1:lO is incorrect and you want to set the time to 2:15, then switch SW ■ and SW in Figure 1 1.
This is done by pressing ■ and inputting.

Switching to the start state is performed by pressing SW9 in Fig. 1 again, but once it is returned to N mode with SW5 in Fig. 1 (at this time, LED 8 in Fig. 1 is still lit, and the TS mode (clock circuit has stopped)
), if there is a time transmitted from the transmitter in the video, compare that time with the time set on this device on the screen, and at the moment the two match, switch SW9.
You can also start the watch by pressing .As this watch is powered by a DC battery, the T. V. It operates even when the set power is OFF, and if the reference clock is stable, there is no need to set the time frequently.
By pressing A adjustment SW1 0, 30
For a delay of less than a second, the minute is carried forward and the second or less is set to 0, and for a delay of less than 30 seconds, the minute is not carried forward and the second or less is set to O.

For example, if you compare the time display on this device with the time displayed in the video, and if the display on this device is slightly different (several seconds),
Second at the moment the time displayed in the video changes.
Pressing the Adjust SW will automatically correct the device.

This second correction is performed by the signal 179 in FIG.

The method for writing/reading the 16 program memory of this device according to the writing/reading address and erasing the program during program execution will be explained below.

This reading and erasing is performed by T, V. Since this is done using an address corresponding to the position on the screen, the timing etc. will be explained in detail later.

FIG. 13 shows the ROM (169 in FIG. 3) and program memory (171 in FIG. 3) for reading and writing data according to each address.

The basic circuit of the ROM used is shown in FIG.

In this figure, it goes without saying that the contents of the ROM are equivalent to the contents of the gate circuit.

As shown in FIG. 13, the program memory 171 has 16 storage units (shift registers) 171a...171d.
..., of which eight storage units 171a, 17lb
,... is the left AD of the television screen shown in Figure 2.
, ~AD8, and the remaining eight storage units 171C, 17
1d... corresponds to AD9 to AD,6 on the right side of the screen.

Therefore, the storage section 1 corresponding to the right side of the screen AD, ~AD, 6
The program data stored in 71C, 171d, etc. is automatically erased after the program is executed, and the program data stored in the storage units 171a, 17lb, . . . corresponding to AD1 to AD6 on the left side of the screen.
The program data stored in ... will not be erased and will remain as is even after the program is executed.

The memory of 15 bits per program is constituted by a dynamic shift register and operates at the timing of clocks φ1 and φ2, and data circulates through 172a in FIG. 13.

In Figure 3, 172 shows the circulation loop, and the 13th
In the figure, 1γ2a, 172b=172c...

Circulation of data and writing, reading, and erasing of data in the program memory 171 are performed by the aforementioned α, γ, the write address bus 79, the address bus 129 that specifies reading and erasing, and the erase pulse EP292, a pulse B that controls EP2.

128, read pulse Rpl68, initialz
e 2. Writing and reading of data is performed by the ROM 169 using the circular data (for example, 172a) of the memory as an input signal.

This ROM 169 consists of a plurality of ROM gates.

That is, in the figure, the R, OM gate 200 is a gate that returns the output data of the storage section 171a to the input terminal, and the ROM gate group 201 is a write address ROM to which a write address designation signal 79 that designates writing data to the storage section 171a is supplied. Gate group and ROM gate 202
is a gate that writes data to the storage section 171a at the timing of the signal when a write address designation signal is supplied to the write address ROM gate group 201 described below.

Further, the ROM gate 203 is a gate that closes the ROM gate 200 when data is written to the storage section 171a and prevents the output of the storage section from being fed back.
R opens the ROM gate 200 when no addressing signal is supplied to the R
, OM gate group.

On the other hand, the ROM gate group 205 is a read address group to which a read address designation signal for specifying read data of the storage section 171a is supplied, and the ROM gate 206 is connected in series with the read address R and the OM gate group 205, and is Rp.
The gate to which the signal is supplied, and the ROM gate 207
is a gate that reads the output data of the storage section 171a to the read line 175 when the read address designation signal is supplied to the read address ROM gate group 205 and the Rp signal is supplied to the ROM gate 206.

The above ROM configuration is the storage unit 171b..., 171 of the pond.
A similar arrangement is also provided for C, 171d, . . . .

Further, each of the storage units 171C, 171d, . . . is provided with a ROM gate group 208 for erasing program data after program execution.

This erase ROM gate group 208 has an erase pulse EP2 and a control pulse B.

When supplied, the program data stored in the storage units 171c, 171d, . . . is erased.

On the other hand, initialize2 is this 1 when the DC power is turned on.
This is an initial setting signal that remains "1" for a period sufficient to clear the 5-bit memory and then becomes "0".

In this initialize 2, all 16 programs are set to the all "1" state by the output signal of the all clear 173 when the DC power is turned on.

At this time, the memory data is not displayed at all.

The write designation is input to the address counter 7 in FIG. 3 using Step SW6 in FIG.
Decide on the bit.

This corresponds to changing the position of "1" on the screen display.

This 4-bit address is 79 in Figure 13, and data is written at α and γ to the address specified by these 4 bits, 1 7 1 a , 1 7 l b , 171
It will be stored in the memory represented by c, 171d.

Writing using α and γ was described a little earlier, but first, when time data is input, α is output at the predetermined timing mentioned above, ANDed with write address 19, and as a result, the NAND output is used to store data in the memory. is input.

During time data writing, D and γ are "0". For example, if Memo! J171a is selected by the address signal 79, the ROM gate 203 causes the circular data
a is stopped and time data is written into memory 171a via ROM gate 202.

After the time data is written, both α and γ become “1” as described above.

Therefore, the circulating data 172a starts circulating again, but at this time, α="1" is set as a memo through the ROM gate 202.
J 1 7 1 a, so the memory 171a
All bits after the bit corresponding to the minute data are coded “1”.
will be written.

When writing the minute data, since α=“1” and γ=“0” at the timing of the digit pulse D2 as described above, the circulation data 172a is similarly stopped and the minute data is written.

With this data, the code "1" previously written in the memo ') 1 7 1 a will be rewritten.

Similarly, when writing channel data, γ becomes "0" during the channel data writing period D3, and data is written starting from α.

Since writing is performed cyclically, when time data is input again, the same operation as the time data writing described above is repeated.

Note that the timer data is processed by writing "1" into the memory by setting r to "0" at the predetermined timing D4.

Program 1 Read every 5 bits using bus 129
According to the 3-bit read address outputted by , the data is serially read out through two output lines 173 corresponding to the left and right sides of the screen display.

The timing of the address is determined by the display position on the screen, and the read pulse generation circuit 167 generates a read pulse Rpl68 from the read command signal RG125 synchronized with the address, and supplies this Rp168 to the write/read ROM1 69 to generate 15bi
Read the data of t.

This read 15-bit data is used for comparison with the clock time, converted into a character pattern, and displayed.

The address signal output from this bus 129 and the R, G and T. V. FIG. 14 shows the relationship between the vertical synchronizing signal VI/o and the vertical synchronizing signal VI/o.

In this figure, MG is a signal representing a display period in which the contents of 16 programs are displayed in an interval of "1".

Bl s B2 * B3 is the 3-bit address.
In Figure 15, T. V. It shows the timing of RG synchronized with the clock system and Rp synchronized with the clock system of the clock.

R and P are signals created by extracting the change point from ``0'' to ``1'' of the R and G signals, and a detailed block diagram of generating Rp once for each change point of RG is shown below. It is shown in FIG.

This FIG. 16 represents the circuit of the read pulse generation circuit 167 of FIG. 3.

In the figure, reference numeral 165D4 is the timing signal shown in FIG. 11, which provides timing for reading the read pulse RpI68 from the program memory.

In FIG. 16, reference numerals 167a and 167b respectively represent a clock generator and a gate circuit which take out the changing points of the R and G signals 125 in circuit terms and output Rp.

The timings of D4 and RG have different clocks and are considered to be completely asynchronous.

Therefore, D4 at any timing with respect to the RG signal
Since the cycle is 15 bits x φ2 = approximately 470 μsec, the width of “1” for R and G must be 2×D4 or more, and is actually 960 μsec.

Naturally, the width of Rp is the program memo IJ-15bi.
Needless to say, it has a width of t, and the phase is set at a timing that just includes D1 to D4.

The timing is shown in FIG.

As shown in Fig. 13, the memory read is B,...
This is performed by ANDing the 3-bit addresses B2 and B3, the read pulse Rp, and the circulation signal.

By implementing this readout method using an R, OM structure, a signal is obtained as a wire FOR of each ROM output, and the left and right program outputs are respectively taken out by one wire.

These two output lines are 173 in FIG. 3, and the read data is serially output and stored in the buffer register 174 in FIG. 3 for the display period of the program corresponding to the program output on the left and right sides of the screen. be done.

FIG. 17 shows a specific configuration of this buffer register 174.

Looking at the program register on the left side of the screen, the left program data output 173 is the static register 174 with a 15-bit serial in-parallel output.
The parallel output of the register 174a input to the register 174a is transferred to the buffer register 174c at the timing of the timing pulse 174e (see FIG. 25) and stored for the display period.

Here, as shown in the figure, the timing at which data is serially written into the buffer register 174a is Rpφ1.

Program data for the right program is stored in the buffer register 174d in exactly the same manner.

The output buses of the buffer registers 174c and 174d are shown at 97 in FIG. 3, and the output buses are separated into left and right programs and input to the check circuit 96 in FIG. 3 as 97L and 97B.

The buffer resistor 174 in FIG. 3 is constructed from the circuit described above, but as shown in FIG. 14, the timings of the read command signal RG and the signal MG representing the display section are shifted by one address.

This means that while the output of the buffer register 174c is displayed, the buffer register 1
This is caused by inputting the next display data to 74a, and is a method taken from the temporal relationship between display and program reading.

That is, considering the read address as a reference, if the address is B3 + B2 + Bl as shown in FIG. 14, the data read at address "111'" is ""
o o o” address, then address “1”
While the data read out at address "1 1" is being displayed, the data at address "' o o o" is read out and input into the buffer registers 174a and 174b.

At the same time as moving to the next "001" address, data is transferred to buffer registers 174c and 174d by timing pulse 174e and displayed.

In other words, the read address and display address of one program memory data are shifted by one address.

On the other hand, the display of "1" which specifies the program writing position is the output bus 129 of the vertical timing signal generation circuit 122.
This is done when the address of the read address signal supplied through the output bus 79 of the write address counter 78 matches the address of the write address signal supplied through the output bus 79 of the write address counter 78.

FIG. 3 80 shows an address comparator that compares the two.

FIG. 18 shows the correspondence of this comparison address.

In this figure, 2°, 21, 22, and 23 are the output buses γ of each counter of the write address counter 78 in FIG.
9 is shown.

One input is to add 1 bit of the signal RH shown in FIG. 21, which indicates the left and right sides of the screen, to the 3-bit read address of Bl p B2 s B3.

These R and H are signals that become "0" on the left side of the screen and "1" on the right side of the screen in one horizontal scanning period.

81 in FIGS. 3 and 18 is an address match signal.

This match signal causes "1" to be displayed, so when the write address is successively changed using the Step SW in Figure 1, the display position for "1" will be as shown in Figure 2, corresponding to that address. ADl~AD, , AD, o-AD, 6
, AD1 and so on.

A match signal indicating "1" is obtained by matching both addresses, and as described above, the read address and the display address are shifted by one address.

The 1 bit corresponding to 23 of the output bus 79 of the write address counter is simply considered to be the bit for R and H corresponding to the right part of the screen center in the horizontal period and is set to "0".
'' indicates the left program, and u 1 tt indicates the right program, so the screen position specification is 2° 21 .
22 3 bits is a good read address゛o o
The write address of the program memory for "o" is "0 0 1".

In other words, if reading is performed at the address "ooo", the read program will be displayed at the address "o o i", and since the write address of this Durham is "001", the read address "0" will be displayed.
``1'' will be displayed in place of ``0 1''.

Similarly, when considering the read address as a reference, the same can be said about the erase address during program execution.

In this device, the only program to be erased is the right program, so looking at the program memory at 171c in FIG.
The time data of the program and the time data of the clock at '001' are compared in the comparison circuit 93 in FIG. This control circuit 90 outputs an erase pulse El)2 through an output line 92.

The timing of this comparison will be described later along with this coincidence pulse, but it is generated approximately 90 μsec after the address becomes "00l" and EI)2 is output.

Therefore, after execution of the program read at "' o o o", erasure is performed at address "00l".

That is, it can be seen that the read address and the erase address are shifted by one address, similar to the relationship between the read address and the write address described above.

In the ROM shown in FIG. 13, B is input in series to the ROM to be erased.

The signal 128 in FIG. 3 gives the timing of time comparison to the left and right programs; when Bo="0", the time of the left program is compared, and when Bo="1", the time of the right program is compared.

Furthermore, B. The details will be described later. 174 in FIG. 3 is the buffer register explained in FIG. 17, and its output bus is shown in 97 in FIG.

The left and right output buses of this program are used for display in P mode and for time comparison in N mode.

The check circuit 96 is composed of a data switching circuit based on the timing of display and time comparison, and a data check circuit.

FIG. 19 shows the main timing signals of this switching check circuit.

FIG. 20 shows the flow of data signals to be switched and the configuration of a check circuit.

S in Figure 20 indicates the character display timing of the horizontal pulses s, s2s...s, lsto required to display one character, and indicates the timing chart of this S signal and the horizontal synchronizing signal H. Figure 21 shows this.

The LH and RH signals are display timing signals that determine the left and right sides that are "1" when the left half and right half in the horizontal direction are displayed, respectively.

Figure 22 shows the timing of S and L for the displayed character.
The correspondence relationship between H and RH is shown.

It is clear from this figure that 81 to 810 provide timing pulses that can display 10 characters each on the left and right sides of the screen.

FIG. 19 shows the display timing in the vertical direction with respect to the vertical synchronization signal VI/o, and in the figure, TCG is a timing signal that indicates the clock time and the display section of the channel number.
BO is a signal that performs time comparison, which will be described later, controls the input data of the channel register in the event of a match, and controls the program erase signal Ep2, and is the output of a counter that changes at the rising edge of MG.

FIG. 20 shows the signal flow for explanation.
97L and 97R are the data output buses for the left and right programs of the buffer register shown in FIG. As shown, AND is performed, the output is ORed for each bit, and AND is performed with S according to the display timing shown in FIGS. 21 and 22.

As described above, each data is switched at a predetermined timing and input to the check circuit.

On the other hand, since the time channel display is displayed on the right side during the TOG period, the channel register output bus 157 and time data bus 159 in FIG.
and RH are ANDed, and the output data is output for each character in the order of display at S timing according to the display and input to the check circuit.

The time AM/PM signal is decoded and output as 160 in FIG.

The check circuit is one that displays the input data at a predetermined timing S with symbols such as OFF, U, T, 1, etc., one that outputs numerical data to the decoder, and one that displays the data input at a predetermined timing S, and one that outputs numerical data to the decoder.
It is checked at a predetermined timing, and if it is not displayed on the screen, it is selected to output a signal specifying the display system (goods) on the screen.

This check circuit is a type of decoder circuit, and outputs symbol output to bus 111 in FIG. 3, numerical data to bus 99 in FIG. 3, and display control designating signals to bus 98 in FIG. 3.

For example, a part of this check circuit checks at 86 timings whether 1 bit of information in the 1st digit of program data is "'0" or "1", and if it is "'0", it is set to 0;
If it is "'1'", the bus 111 is outputted as a symbol instead of a numerical value so as to display 5.

Alternatively, it is checked at timing 810 whether or not there is a timer input, and if it is present, it is output to the bus 111 to display T.

The AM/PM output signal 160 is input to an output control circuit 110 in FIG. 3, which will be described later, and is used at this output section to display the displayed characters in color.

FIG. 3 102 is a STOP circuit which receives the check output bus 98 as an input and generates a STOP 2 signal for inhibiting display, and FIG. 23 shows the detailed circuit.

The circuit configuration of this output control stop circuit is related to the program input method described above, and is realized by determining in advance what data is to be erased.

In other words, we focused on the fact that the input data of the program is that there are no numerical inputs of 12 or more for time information, that there are no inputs of 6 or more for 10th place information of minutes, and that there are no inputs of 14 or more for channel number information. Erasure data has been input.

In the Stop circuit, by checking the above conditions, S
This determines whether or not to output the top 2 output.

(m(7) In FIG. 23, the signal 98a is a signal that becomes "1" if the time 4 bits of the program data are "110o" or more, that is, the numerical value 12 or more is input, and 98b
is a signal that becomes "1" if 3 bits of the tenth place are "1 1 0" or more, that is, a value of 6 or more is input, and 98c is a signal that becomes "1" if the 4 bits of channel number information are "'1110" or more.
``If a value greater than or equal to 14 is entered,'''
This is a signal that becomes 1''.

Each 98a, 98b, 98c input is s2, s,
, s7, through the AND gate 231 and the OR gate 2 3 2 Inverter 23 3
, -S serves as a set input for the flip-flop 234.

Reset is S1, and S top is set by set input.
2 FIG. 3 103 is output.

As mentioned in the program data input method, program erasure (non-display) data is essentially all 1
”, but out of this all “1” data, s
At timing 2, the highest 2b of the 4 bits of time data
If it is checked and it is "' 1 1", the data is 12 or more, so the signal 98a in FIG. 23 becomes "1" and Stop2 is output at the S2 timing, that is, the display output is gated so that no display is performed.

When writing the time data, the minute or less was written as "'1", but the specified bit of this 10 minute information is checked with S, and as mentioned above, "1" is output to 98b, so this S,
Output S top 2 at the appropriate timing.

Only the time data is displayed in this program, and nothing is displayed even if the following data is erased.

Next, when the minute information is input, S
top2 is output and the channel is not displayed.

In this way, the display on the screen can be controlled simply by detecting the sign of the high-order bit among the digits of each information, and there is no need to check all bits.Furthermore, it is possible to hide an entire line by detecting only 2 bits out of 15 bits. It can be realized and the circuit is very simple.

According to this method, there is no need to add a separate bit for specifying display/non-display on the screen, and it is very advantageous in terms of reducing the circuit size, especially when implementing LSI.

By associating and displaying the program's input method and display as described above, the program can
This allows you to understand at a glance what information to enter next.

Furthermore, since the channel number is not displayed in the TS mode and the P mode, the signal 98C is also a signal that becomes "1" at the timing of the TCG in this mode.

FIG. 3 93 shows a comparator for time comparison.

FIG. 3 101 shows the time and minute channel information of the program data for this comparison.
It is input to the comparison circuit 93 in FIG. 3 as the signal 101 in the figure.

The other input of this comparator circuit is the hour and minute information 1 of the clock.
It is 59.

Another input signal of the comparison circuit 93 is a comparison timing signal for both pieces of information.

FIG. 24 shows the configuration of the comparison circuit. Figure 3, Figure 249
4 is the output of the comparison circuit, which outputs a coincidence pulse when a coincidence is established in the comparison timing signal 93a.

Also, as shown in the figure, the comparison data is B.

Gated by B. - When Bo is "0", the left program is compared; when Bo is "1", the right program is compared.

91L' in FIG. 24 indicates the hour and minute information of the left program among the 101 signal buses shown in FIG.
” indicates the channel information of the program on the left.

Similarly, the hour and minute information of the right program is indicated by 97R',
Channel information is indicated by 91''.

As shown in Figure 24, 97L"97R" is 97L'
, 97R'.

and is output as a channel data bus 100.

This channel data bus 100 is a data bus for writing this channel information into the channel register γ0 using a coincidence pulse 94.

The coincidence pulse control circuit 90 in FIG. 3 generates an erase signal EP292 during program execution using the coincidence pulse 94, and
Signal 128 determines the priority of execution of the left and right programs.

The phase of the timing signal 93a shown in FIG.
FIG. 26 shows timing pulses 174e shown in FIG. 17, and timing signals 93b,
93c gives the timing for comparing the left and right programs.

The width of "1" of the timing signal 93a determined from the timing signals 93b and 93C is LH and RH, which is about 30 μSee.

The actual comparison timing signal 93a consists of the following logic.

N. ω． M.G. 2H. (Bo.LH+B.

RH) logic, N is a signal that becomes ``1'' when in N mode.

ω becomes "1" when the 138yst SW in FIG. 1 is ON, lighting up the LED in FIG. 14, indicating that the program is ready to be executed.

The 2H signal is a signal that remains "1" during the IH (one water period) following the 174e pulse.

That is, the output of the coincidence pulse is generated at the above-mentioned timing with a width of 30 .mu.See for LH or RH due to the establishment of the above logic and the establishment of coincidence of the time data.

EP2 shown in FIG. 25 is a signal for erasing the matched right program according to a predetermined address, and is the output of the R-S flip-flop which is set by the match pulse 94 and reset by 174e shown in FIGS. 17 and 26. It is output with a width of approximately 1 mSec, which is sufficient to erase 15 bits of the program.

In the figure, CI and EP are signals for writing the channel data 100 in the channel register 70 and switching the channel when executing the program described above, but since the left program is not erased even if it is executed coincidentally, the left program at the same time If there is a program input, the channel will be in an oscillating state for 5 minutes and the channel will not be determined.

Therefore, for the execution of the left program, the coincidence signal is controlled so as not to output the EP signal for 5 minutes after the coincidence pulse is output and executed.

Naturally, manual channel selection is possible during this 5 minute period as well.

The coincidence signal is controlled by the 5-minute control signal shown in FIG.

In the figure, 91a and 9lb are circuits that create 1, EP with the width necessary to ensure automatic channel switching and selection during program execution, and are a type of time constant circuit using a clock. be.

113 in Fig. 3 is a timer output control circuit, and its human power 95
is the coincidence pulse for the timer program and the third
It can be considered to be the same as FIG. 94.

The signal supplied through the input bus 135 in FIG. 3 is a signal indicating whether or not timer information is present at the time of a match, or if timer information is present, whether it is ON information or OFF information from check circuit 96. Output.

When the coincidence pulse is generated, a timer is present, and if it is ON information, the flip-flop is set, and if it is OFF information, it is reset, and the output signal is output to the output line 114 as Timer Out.

The time output bus of the clock is shown in Fig. 3 159, and the time is the time read out by the signal shown in Fig. 3 124, and is stored in the Fig. 3 time store circuit 158 until the next readout signal comes. be.

This read signal 124 is a clock time read signal generated after the MG signal ends in one vertical period.

In this time reading method, since the time comparison is performed in the MG period, the time read signal 124 is created after the MG, and the time data bus 1590) prevents changes in time data from occurring during the MG comparison. It is something.

The signal bus 99 in FIG. 3 is a display data bus that is transmitted in a time-sharing manner according to the display using the S signal, and the data path is checked again by the check circuit 96 in FIG. This is the bus that outputs .

In other words, the hour digit, ten minute digit, channel number of program data display in P mode, time in N mode, hour digit, ten minute digit, one minute digit, and channel number in case of channel display, etc. It is a maximum 4-bit data bus.

, 104 in FIG. 3 is a display decoder circuit.

As mentioned above, there are displayed times up to 11 and channel numbers up to 12, and since channel number 13 is displayed as OFF, it is not necessary to decode it with this decoder, but it is checked in advance by the check circuit 96. ing.

Taking this into consideration, FIG. 27 shows a detailed display decoder circuit used in this device.

In this figure, a 4-bit signal d.

, d1, d2, and d3 are the output buses 99 in FIG. 3, and each bit is binary information 2°, 21, 22, 23
It corresponds to

This decoder circuit is constructed with the display of input data in mind first.

First, check whether the 4-bit input is a number greater than or equal to 10.
04d and 104e outputs, and if the number is 10 or more, the 4 bits of data are switched and converted to bits that are the first digit of the number, and input to the next decoder.

The next decoder inputs the converted 4-bit data and decodes the first-place number.

The display of the 10th place is the timing of 82, S8 as shown in FIG.

Therefore, S2, S where the 10th output is present in 104e
It is outputted to 104b at timing 8, and then outputted to 1>.

At this time, the first decoder is controlled by 104a at timings S2 and S6 (D).

The signal that controls this first decoder is 1043,
During periods when the decoder is not in use, a gate is applied to set the decoder to a state in which there is no output.

This signal is S1+S2+S4+S7+S8+S1o and 1
04C, and is a signal for which the display format shown in FIG. 22 is determined.

If this control signal is not used, a certain numerical value will be output from this decoder during this control signal period, and that output will be displayed as is.

Signal 104C has channel information 13 on the program display.
It is output at that timing, and the symbol OFF is selected for output from the check circuit 96 and displayed.

<O'> in Fig. 27 is an OR input signal for the two, since the O minute display for 1 minute in the program display and the display for 0 in the OFF display are the same, and at the predetermined timing "0"
” is entered.

Similarly, <101> is the input of 5 in the 1 minute digit of the program.

Note that this decoder output <0><1>...9> is the decoder output of the first numerical value and the above-mentioned 0,
The numbers 1, 5 and symbols are obtained as the OR output, and the selected numerical signal is obtained as the "1" output.

The output bus of the decoder circuit 104 is input to the segment decoder circuit 106 in FIG. 3 105 along with the non-numeric symbol output 111 and the output 81 of the address comparator.

The segment decoder circuit 106 selects display segments of numerical values and symbols (hereinafter referred to as characters) output at predetermined timing.

The character display of this device is an 8-segment display as shown in FIG.

A segment is selected according to the character input to the segment decoder circuit 106, and its output bus is
FIG. 107.

Using this character output bus 107 as input, the character generator 108 converts the selected segment into a character display pattern.

This character generator 108 is composed of a gate circuit that takes a predetermined AND of each segment output, a character's vertical direction pulse 134, and a character's horizontal direction component pulse 146, and converts the character into a display pattern. Serial output line 1 of the character
Output on 09.

Naturally, this converted character pattern is T. V. Output in synchronization with scanning.

FIG. 3 110 shows an output control circuit for controlling character display, including display control signals in N mode (FIG. 3 55), AM/PM signals 160 and S indicating AM and PM of the time data.
A circuit that receives the top 2 signal 103, the horizontal display control signal 150, the vertical control signal 123, and the character output 109, and outputs color designation signals AMG and PMG for displaying character colors in P mode and TS mode. It consists of a circuit that gates areas other than the predetermined display area of the screen and turns off the display, and a sword).

The 112 output bus of this output control circuit 110 has an output for displaying a display character pattern on the screen, such as character output, AMG for specifying the morning, and PM for specifying the color for the afternoon.
Each output of G is taken out, and each output of T. V. Controls the color output of the system.

The 28th diagram shows a specific circuit of the output control circuit 110.
It is a diagram.

In the figure, signals 150 and 123 are signals that are "1" in a predetermined display area and "O" in other areas.

Looking at the display decoder in FIG. 27, d in areas other than the display area.

, d1, d2, and d3 are all "0", and <0> is output to the output bus 105, and O is displayed on an unnecessary part of the screen.

The signal for erasing the O display is shown in FIG.
1 23.

The output control circuit shown in the figure outputs a character pattern and color designation signals of AMG and PMG in the P mode and TS mode, and consists of an AM/PM 160 and a gate circuit using the gates of FIG. 21 and the N mode signal.

This S1 timing signal is a "1" timing signal for displaying the "-1" color indicating the program write position in the P mode as an independent color different from the time color.

If the time channel number display in the N mode is displayed in white, the color designation signals for AMG and PMG are 'O', and only the character pattern output is output.

The predetermined signals such as the read address and display mentioned above are provided by T.
V. Although it has been mentioned that it is generated and output by the clock system, an outline of that part will be described below.

Each component in the horizontal direction of the screen is the horizontal synchronization signal H138 in Figure 3.
It is obtained by counting the output clock CP of the gated oscillator 139, which is gated and oscillated by the gated oscillator 139.

The oscillation frequency of the gated oscillator 139 is approximately 4.5MH
z, and its output CP140 becomes the input of the counter 141 in FIG.

T. of this device. V. All clock system counters use shift register type dynamic counters due to the demand for increased integration of LSIs.

The count 141 in FIG. 3 is an octal count, and when the television receiver is in the ON state, a horizontal synchronization signal (horizontal flyback signal) H is supplied via the signal line 138, the input switching circuit 136 described later, and the signal line 13γ. The clock CP is counted in synchronization with.

The output bus of this counter 141 is 142.

Further, 143 in FIG. 3 is a gate circuit, which inputs the octal counter output 142 and supplies necessary clocks to each part, and generates the horizontal component pulse 146 of the character mentioned above. Output bus 1
44, the clock generator 145 generates clocks φC1, φ.
Generates C2.

Clock φC1 and φC2 are 1/8 CP, or approximately 500K.
It operates at a frequency of Hz.

147 in FIG. 3 is the second counter in the horizontal direction, φC1, φC
It is a 40-decimal counter that counts 2.

This counter 147 also performs a counting operation in synchronization with the horizontal synchronizing signal H when the television receiver is on.

The output bus of each part of the 40-decimal counter 147 is 148, which is 14.
The signal is input to the gate circuit No. 9.

The gate circuit 149 outputs each timing signal to the horizontal direction display control signal line 150 and the horizontal direction timing pulse bus 151 in response to the S timing pulse generation LH and RH signal generation circuits shown in FIG. .

Gate circuit 149 also provides signal 1 to clock generator 154.
Outputs 52.

The clock generator 154 is a clock generating circuit of CP, CP2, and the frequency of CP2 is set to be the same as the frequency of the horizontal synchronizing signal H when the television receiver is on.

These clocks CP1 and CP2 are clocks for dynamically operating the next vertical direction counter.

In Figure 29, N. OFF at [13], that is, in N mode
The relationship between the H input and CP1 and CP2 is shown in the other cases, and in K[13], that is, in N mode and OFF.

As shown, N. In the case of [13], a pulse corresponding to H is created.

CP1 shown in the figure is a read pulse, CP2 is a read pulse, and serves as a clock for the counters 130 and 119 in FIG. 3 which generate the next vertical component timing signals.

N413] That is, when OFF in N mode, T. V. Although there is no H input in the preheat state, the device still has to continue to compare times and execute the program.

Therefore, it is necessary to generate the necessary timing signal mentioned above, and the H input is eliminated. The clock pulses of CP2 and CP2 are obtained from the output of the gate circuit 149.

The counter 130 is a hexadecimal counter using CPI and CP2 as clocks, and outputs 131 from each section are input to a gate circuit 132.

The gate circuit 132 generates 1/16 CP as the character vertical component pulse 134 in FIG. 3 and 133 in FIG.
Generates 2 pulses, etc.

This hexadecimal counter comes from the fact that one line of character display consists of a width of 16H.

The counter 119 is a 262-decimal counter whose clocks are the same <CPI, CP2, and this counter generates the timing for vertical character display positioning, read address generation, etc.

The reason why we used two sets of counters 130 and 119 for the vertical direction is because the counters are dynamic counters of shift registers, so it is easier to use two counters than to create signals such as the vertical direction pulse 134 of the character with a gate circuit. This is because the number of gate circuits is considerably reduced and the degree of integration is improved as a result.

121 in FIG. 3 is a vertical timing generation circuit consisting of an output bus of each part of the 262-bin counter 119, a 122/d'f''-to circuit, an R-S flip-flop circuit, etc.

The output of this vertical timing generation circuit 122 is the vertical direction signals MG, RG, read address B1,
Signal buses such as B2, B3, comparison timing signal, Bo, etc. 123, 124, 125, 126, 127,
It is output as 128 and 129.

116 in FIG. 3 is an input control circuit, which is a 262-digit counter 119.
Reset generation circuit, vertical synchronization signal input/output common signal V
It consists of an I/0 switching gate circuit.

N. In the state of [13], T. V.
The vertical flyback pulse 117 in FIG. 3 resets the 262-digit counter 119.

For P mode and TS mode, when inputting data, please refer to Figure 1.1.
When an empty channel is selected by , the video signal is cut off in order to eliminate disturbances in horizontal and vertical synchronization due to lack of synchronization signals or noise, etc., and to provide a synchronously stable display, and the vertical timing generation circuit 122 generates pseudo vertical synchronization. signal 156
T. V. Trigger the vertical oscillator and use it as a synchronization signal.

The output 155 of the vertical timing generation circuit is a reset signal for the counter 119 at this time, and the input control circuit 116,
It is supplied to a counter 119 via a signal line 117.

N. [13] In other words, the same operation is performed in the case of OFF.

Output 120 of H.262 count 119 is a reset signal for synchronizing hex counter 130 with H.262 count 119.

The circuit shown in FIG. 3 136 is composed of a reset signal switching circuit for the octal counter 141 and the 40-decimal counter 147, and a horizontal flyback pulse 138H (7) control circuit in FIG.

N. [13] That is, in the case of OFF, since there is no input 138H in FIG. 3, the 153 signal produced by the 149 gate circuit is used as the reset signal 137.

N. [13], this H Fig. 3 138 is used as the reset signal 137, but when N. [13] to N. [13
] The switching of the state to N. [13] Signal COFF
This reset signal 137 can be switched from H to the reset signal 153 created by the gate circuit using the N. [13] to N. When the state changes to [13], that is? When a channel is turned on from an FF, the generation of H takes a long time from when it is turned on until H is generated, and the generated H is quite unstable at first.

Therefore, if you turn on and use H as it is, 16
It is possible that the binary counter 13026 and the binary counter 119 make a miscount.

In order to prevent this malfunction at the time of ON, a 136-person power switching circuit as shown in FIG. 3 was devised, and the detailed circuit is shown in FIG.

As shown in the figure, this circuit consists of a gate circuit that switches a predetermined signal based on the output of an R-S flip-flop.

The reset of the R-S flip-flop is N. [13] The internally generated output 153 is reset by the signal 1.
Output as 37.

On the other hand, the CP2 is generated internally as shown in FIG.

N. When [13] is reached, the Vi/O signal shown at 118 in FIG. 3 is generated and set, and the flip-flop continues to operate in the previous state until it is inverted.

When the vertical flyback pulse v/o signal is generated and the flip-flop is inverted, the internally generated 153 becomes H1.
38 to reset the input switching circuit 137, output H to the output 178 of the input switching circuit 136, switch CP2 to H, and set the N. The state becomes [13].

The V/0 signal mentioned above is T. V. This is the synchronization signal input of
．． V. Horizontal signal H13 is generated from set to
8. The oscillation output is considered to be stable.

This device has been described in detail, but as mentioned above, this device realizes the entire electronic circuit by implementing one chip LSI.

Therefore, the gate circuit configuration in the drawings used in the explanation was done for the sake of ease of explanation, and in actual LSIs, maximum ROM and gates are implemented as clock gates. Ta.

As explained above, according to the present invention, a program memory for storing program data is provided with a storage section configured such that the program data is erased after program execution;
It is configured with a memory section configured so that the program data is not erased and remains as it is even after the program is executed, and when data is stored in each of these memory sections, this program data is displayed on the display screen by the display device. Since it is displayed in a specific position that corresponds one-to-one with each memory section, when programming, by selecting the display position on the display screen, the memory section in which the data should be stored can be indirectly selected. By simply selecting this display position, it is possible to distinguish between data to be erased after program execution and data to be left without being erased.

Therefore, the program operation becomes very simple.

[Brief explanation of drawings]

FIG. 1 is a front view of a television receiver incorporating a program reservation device according to an embodiment of the present invention, and FIG. 2 is an example of program input for a television incorporating a program reservation device according to an embodiment of the present invention. 3 is an overall block diagram of a program reservation device according to an embodiment of the present invention, FIG. 4 is a specific circuit diagram of the mode switching circuit 58 and normal feedback circuit 61, and FIG. 5 is an input feedback circuit. 62, a specific circuit diagram of the latch circuit 66, FIG. 6 shows the encoder 68
, a specific circuit diagram of the channel register 70 and the write register 85, FIG. 7 is a diagram showing a timing chart during programming, FIG. 8a is a diagram showing a 1-bit ROM circuit configuration of the write register 85, and FIG. b is this RO
Logic circuit diagram equivalent to M circuit, Figure 9 is one program b
10 is a specific circuit diagram of the digit pulse generator 89, FIG. 11 is a time chart diagram of each part of the digit pulse generator in FIG. 10, and FIG. 12 is a specific circuit diagram of the data writing circuit 87. 13 is a specific circuit diagram of the write/read ROM 169 and program memory 171, FIG. 14 is a time chart of read addresses, FIG. 15 is a time chart of read command signals and read pulses, and FIG. FIG. 17 is a block diagram explaining the buffer register 174, FIG. 18 is a diagram explaining the address comparator 80, and FIG. 19 is a vertical time chart used for the explanation. 20 is a block diagram explaining the flow of data signals supplied to the check circuit 96, FIG. 21 is a horizontal time chart used for explanation, and FIG. 22 shows the correspondence between display characters and S signals. 23 is a specific circuit diagram of the display control Stop2 circuit 102, FIG. 24 is a block diagram explaining the time comparison circuit 93, FIG. 25 is a block diagram explaining the coincidence pulse control circuit 90, and FIG. 27 is a specific circuit diagram of the display decoder 104, FIG. 28 is a circuit diagram explaining the output control circuit 110, and FIG. 29 is a time chart diagram of the clock used in the explanation. , FIG. 30 is a specific circuit diagram of the input switching circuit 136. 1...Tuning switch group, 2...OFF
Switch, 3...Display switch, 4
・・・・・・Program switch, 5・・・・・・
Normal switch, 6...Step switch, 7...Erase switch, 8...
...LED, 9-Time Set, Start switch, 10...Second Ad jus
t switch, 11...AM switch, 12.
...PM switch, 13...System
m switch, 14...LED, 15...
・T. V. Set ON/OFF switch, 16...
...T. V. Screen, 17...Time, channel display, 18...'I71mer input switch,
19... Time display, 35... Crystal oscillator, 37, 41... Clock counter circuit, 40.
...Clock generation circuit, 43...Time...
Minute counter circuit, 45...Clock timing generation circuit, 46...Flip-flop circuit, 4
8...Timer input circuit, 50...Erase input circuit, 52...Trigger pulse generation circuit, 5
4... Pinary flip-flop circuit, 58...
...Mode switching circuit, 61...No
rmal feedback circuit, 62... Input feedback circuit, 64... Trigger pulse generation circuit, 66... Latch circuit, 68...
...Encoder, 70...Channel register, 74...Exclusive logic circuit, 16...
Ternary, binary counter, 78...Write address counter, 80...Address comparator, 82.
...Timing pulse generator, 85...
Write register, 87... Data write circuit, 89... Digit pulse generator, 90...
... Coincidence pulse control circuit, 93 ... Time comparison circuit, 96 ... Check circuit, 102 ...
...Display control S top2 circuit, 104...
Display decoder, 106...Segment decoder, 108...Character generator, 11
0... Output control circuit, 113... Timer output circuit, 116... Input control circuit, 119
262 binary counter, 122 vertical timing generation circuit, 130 hexadecimal counter, 132 gate circuit, 136
...Input switching circuit, 139...Gated oscillator, 141...Octal counter, 143...
... Gate circuit, 145 ... Clock generator, 147 ... 40-decimal count, 149 ...
...Gate circuit, 154...Clock generator, 158...Time store circuit, 167...
... Read pulse generation circuit, 169 ... Write and read ROM, 171 ... Program memory, 174 ... Buffer register.

Claims (1)

[Claims] 1. A program input device that inputs program data consisting of time information and channel information, a storage device that stores this input program data, a read circuit that reads this stored data, and a display that displays this read data. A display device that measures time based on a reference signal, a clock device that measures time using a reference signal, and a comparison device that compares the time of this clock device with time information in the data read out by the readout circuit and generates a match signal when they match. circuit and
and a channel selection device that selects a channel based on the channel information stored together with the time information in response to a coincidence signal from the comparison circuit, and the storage device erases the program data when the channel selection operation is performed. and a storage section that retains program data even after the channel selection operation, and the display device transfers data read from each storage section of the storage device to each storage section on the display screen. A program reservation device characterized in that the program is configured to be displayed at a specific position in one-to-one correspondence.