JPS5835642A - Data processing device handling undefined length instruction - Google Patents

Abstract

PURPOSE:To use an operand designator commonly for plural operands to be processed, by processing instruction when it is detected that operand end information is set. CONSTITUTION:The signal on a signal line 203 or the like indicating an operand end flag is inputted to a decode processing end byte number detector 65, and the addition value of a DP register 69 is outputted to a signal line 214 for the purpose of indicating the address of the next operand designator. If the end flag of the operand is set to 1, the processing for this instruction is terminated, and contents of the register 69 are counted up to indicate the start of the next instruction. If the end flag is not set to 1 and the stop bit of the operand designator is not set, value -1 is added. Meanwhile, if the stop bit of the operand designator is set, 0 is outputted. Thus, the same operand designator is used for the next operand processing, and the same operand is used repeatedly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that handles undefined length instructions in which an operand specifier that specifies the addressing mode of an operand is independent of an opcode portion that specifies the type of processing and the number of operands. .

The length of the operand specifier changes arbitrarily depending on the addressing mode, and since the length of the instruction is variable, such an instruction is sometimes called a variable length instruction.

There is no particular difference in meaning between "undefined length instructions" and "variable length instructions," and even if the term "undefined length instructions" is replaced with the term "variable length instructions," they have the same meaning. However, here, for convenience, the instructions handled by the present invention are referred to as indefinite length instructions, and the conventional instructions are referred to as variable length instructions.

Two typical examples of well-known instruction systems having variable-length operand specifiers are shown below.

One is Burroughs Corporation.
ation calculator B1700 to C0BOL/RP
This is the instruction format for G-oriented architecture, and this is rB1700 C0BOL/RPG
-8-Language, 1058823-015.
Copyright1973, 13urroughs
CorporationJ.

Another example is DEC (1) digital Equi.
pmentCorporation) CR) It is an instruction system with variable length operand specifiers that the computer VAXI l/780 architecture has.
ndbook, (:opyright 1g7g
J and USPA 4,236,206.

The two conventional instruction systems shown here are characterized in that the part that specifies the operand format and addressing mode is defined by a variable-length operand specifier and is independent of the opcode.

However, in conventional variable-length instructions, there is a one-to-one correspondence between the number of operands to be processed and the operand specifier that specifies the addressing mode of the operands to be processed. For example, A0B → B A0B → It was necessary to allocate two opcodes to two operations (C).

In other words, in the process A0B→B, it is necessary to specifically specify in the opcode that two operands are processed and the second operand is used twice. .

If the number of operands is 3 and three operand specifiers are prepared in the process A0B-)B, there is no need to be aware of the distinction between A+B→B and A0B-)C, but A -1
-B-+B processing requires two identical operand specifiers, which reduces memory implementation efficiency when the operand specifier itself takes multiple bytes (generally long ones are 7 bytes). It is markedly lowered and is not desirable.

In the first place, the process of A+B-)B and A+B-)C was distinguished in order to improve memory implementation efficiency. (In A1B-+B, only two operand specifiers are required.) In this way, in the conventional method, processes that use the same operand multiple times are distinguished from other processes with the same function. There was a limit to the number of operations that could be specified using the opcode.

I explained using the example of A+B→B, but this is A-B-)
The same goes for the process B, and applies to all examples in which operations are performed on A and B and the results are stored in B.

Generally, this is expressed as AOB→B.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that handles undefined length instructions that can share operand specifiers for a plurality of operands to be processed.

In other words, the above example is intended to provide a data processing device that handles an indefinite length instruction that can distinguish and process two processes using one instruction code.

A feature of the present invention is that operand specifier end information (hereinafter referred to as a flag) is added to each operand specifier that specifies the addressing mode of the operand, and an end flag is added to the final operand specifier. 1”
, and if it is detected that this end flag is set to ``1'', it is determined that one instruction is formed including the operand specifier, and processing is performed. .

Specifically, as will be described later, before the operation code decoding means outputs a signal indicating that it is the last of the operands,
In this case, if the end flag is found set, the same operand specified in the opcode would be used again (if the operand specifier in question indicates that it is the last). The final operand is used many times until the number of operands is reached.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a basic conceptual diagram of seven data processing systems to which the present invention is applied.

A memory device 1 and a plurality of central processing units 2 are connected by a common bus 3, and information can be exchanged between them via the common bus 3.

The memory device 1 includes a memory unit 11 that stores instructions and operands handled by the instructions, and a memory control unit 12 that controls reading and writing of the instructions and operands.
connected with.

Regarding the operation of the memory device 1, please refer to Japanese Patent Application No. 55-160.
Since it is described in detail in the specification of No. 758, and is not directly related to the main part of the present invention, a detailed explanation of this part will be omitted.

A plurality of central processing units 2 can be connected to the world bus 3, and each of them (two in the figure) accesses instructions and operands from the memory device 1 and processes the November instructions.

Here, in order to increase speed, the instruction cache 21 (high-speed buffer memory) and operand cache 22 (high-speed buffer memory) that copy the instructions and operands that have been read once are used.
an I unit 23 which has a high-speed buffer memory) and performs fetch decoding of instructions and operand address operations;
This example shows an example of how to use the instruction cache and operand cache, or how to use the instruction cache and operand cache, or ■ unit and E unit. It is well known that pipeline processing is performed.

Now, FIG. 2 shows the format of the indefinite-length life table handled by the central processing unit 2.

One instruction consists of an operation code (commonly called an opcode) OF consisting of 1 to several bytes, and an operand specifier of 1 to am bytes with an end flag S O81゜082...・・O20
It consists of

The operation code OP describes the processing content of the instruction (processing type), the number of operands required for processing, and the operand attributes (data length, read/write distinction, data type:
fixed-footed point/floating point, etc.) are shown.

After the opcode OPO, an operand specifier (081,0
82...) is shown, and constitutes one instruction (formally, an instruction word).

The operand specifier is the first operand specifier used in the relevant instruction, and only the last operand specifier is
The end flag S is set to "1". If the number of operand specifiers is less than the number of operands specified by the opcode OP, the operand corresponding to the last operand specifier is used repeatedly.

There are various ways to use the same operand repeatedly, but the most desirable method is to use the last operand specifier repeatedly, which will be discussed in detail later.

An example in which the number of operands specified by the operation code OP and the number of operand specifiers do not match will be described next.

For example, if the opcode OP is an addition operation, the function is A+B-C, which requires three operands, but if there is one operand specifier, A + A-)A, and if there are two, A Processing B-+B is possible with the same opcode.

A specific example of the operand specifier is shown in FIG. 2 [F]).

Here, examples of flats 1 to A24 are shown, and their formats and corresponding operands are shown in a 1:1 correspondence.

In FIG. 2 (E3), the parentheses of the operand indicate the contents of the memory whose address is the address in the parentheses.

Further, during formatting, DISP indicates displacement, IM indicates immediate (data direct), and the subscript indicates the size in terms of the number of pits.

Furthermore, Rx represents an index register, Ra represents a general register, and L represents the size of the operand in bytes.

Although the relationship between the format and the operands in the second drawing can be understood to a certain degree, a brief explanation will be provided below.

In the addressing of A11d and lz registers, the general register itself indicated by R becomes a direct operand.

2 and below all use memory as an operand,
The address calculation is performed in the form shown in the operand column.

A2 is indirect addressing, in which the contents of the general register indicated by Rfi become the address of the operand.

In A3, 5.7, the value indicated by DISP is added to the contents of the general register indicated by all, and this becomes the address of the operand.

In case 4, 6.8, the contents of the memory at the address determined in case 3, 5.7 become the address of the operand.

A9~llI'i, A is -diet data, I I
The values of 'vi++, I M+a, and I Ms□ are themselves operands.

A12-17 differ from A3-8 only in that the program counter PC is used for one cycle instead of the general register R4. The PC holds the address next to the operand specifier to decode.

7; 18 to 24 are different in that the value of index register R8 is further added to notifications 3 to 8, and the value of index register Riko is added by a value multiplied by the data length of the operand.

This is necessary processing in order to be able to set the value of index register R0 as a displacement from the beginning, regardless of the data length.

In other words, by multiplying by L (indicating the data length), the index register ratio may contain a value indicating the number of data from the beginning, regardless of the data length.

For example, if the index register Hiko contains "lO", this is the 10th data from the beginning, and its address is 10 if it is a byte (L=1), and 20 if it is a word. (L=2), long word responsibility LOr
1g Word), 40 is automatically added to L = 4.
), the user can set the value of the index register ratio regardless of the data length.

FIG. 3 is a more specific block diagram of the central processing unit 2 shown in FIG. 1.

The unit 23 in FIG. 1 is the instruction fetch unit (FU) 25 and the aligner (ALI) in FIG.
G) 26, decode unit (DU) 27 and address calculation unit (AU) 28 correspond to this, and E unit 24 has an operand fetch unit (OFU).
29, and the execution unit (EtJ) 30 corresponds.

In FIG. 1, it was mentioned that the unit 23 and the E unit 24 perform pipeline processing, but each unit further includes an instruction fetch unit IFtJ2 as shown in FIG.
5, a decode unit DU27, an address calculation unit AU28, an operand fetch unit 0FU29, and an execution unit) 30, each of which performs pipeline processing.

However, since the gist of the present invention is not directly related to such pipeline processing itself, a detailed explanation of pipeline processing is omitted. Incidentally, the pipeline processing itself is well known, but it is described in USP 4.
No. 025.771 shows a pipelined high speed signal processor.

By the way, in FIG. 3, the instruction fetch unit 25
The program counter 50 has a program counter 50 for fetching instructions in advance, and performs a process of reading an instruction that will be executed next from the instruction cache 21 in advance.

The address to be read is sent to the instruction cache 21 via the address line 100, and the corresponding 4 bytes of the instruction are sent to the instruction cache 21 via the data line 101.
Sent on 25th.

If there is no corresponding instruction in the instruction cache 21, the corresponding instruction is read from the memory 1 via the common path 3, and this instruction is stored in the instruction cache 21.

of the cache, is well known to the head 1, for example, l'
A GUIde to Tne IB&fSyst
em/37Q Model 168j.

When four bytes of instructions are sent to the instruction fetch unit 25, the program counter 50 is incremented by four (+4), and a request for sending the next instruction is output to the instruction cache 21.

This operation continues until a buffer (not shown) in the instruction fetch unit IFU 25 becomes full.

From the instruction fetch unit IPU25, )(S103
The command read out in advance is sent to the aligner (ALIG) 26 via the aligner (ALIG) 26.

The aligner 26 performs the shift processing by the number of bytes specified by the signal [102] from the decoding unit DU27,
The corresponding command is sent to the bus 104.

By appropriately manipulating the value of the signal line 102, the bus 104
As shown in Figure 5, when processing the first operand specifier of an instruction, the operation code OP is placed at the left end, followed by the first operand specifier, and when processing the second and subsequent operand specifiers, the operation code OP is placed at the left end. Operand specifiers are placed and output with dummy bytes.

The above books will be explained in detail later.

Decode unit (DU) 27a, aligner 26 (A
It decodes the opcode and operand specifier sent from LIG) and sends the following information to address calculation unit AU28.

(1) Send the addressing mode via the lotus 105.

The addressing mode includes the following (a) as explained above.
) to (h), one of which is specified.

(a) Direct register...A1(b) R
,...A2 (C) a, +DIsP type...A3,5
．． 7(d) l't, +DIsP indirect type...Ban 4,6.8 (e) Immediate...A9. I
O, l 1(f) PC+DISP type...
・・Flat size 12, 14.16 (g) PC+DISP indirect type・・・・・・・・・A13, 15.1
7 (h) (b) - w (d) with Intex type.
...A18-24 The numbers 1-24 correspond to the numbers 1-24 of the operand specifier format shown in Fig. 2, et al.

(2) Send DISP or IoT data in 32 bits via bus 106; .

(3) Send the address of general register R4 via bus 107.

(4) The address of the index register R is sent via the bus 108, and (5) the value of the program counter used for address calculation is sent via the bus 116.

Address calculation unit AU28H, according to the addressing mode indicated by bus 105, the above (a),
In cases other than (e), calculate the address of the operand,
The calculated address is sent to the bus 309.

On the other hand, in the case of (a), the contents of the bus 107 are sent to the bus 113, and in the case of (e), the contents of the bus 106 are sent to the bus 109.

Operand fetch unit 0FU29ij, above (a
), (e), the contents of the bus 109 indicating the sent address are sent to the bus 110, and when the operand is read, a read process is requested to the operand cache 22.

When the read operand is sent from the operand cache 22 to the bus 111, the operand fetch unit 0FU29 sends the read operand to the execution unit Eu2 via the bus 112.
Sends the read operands to O, and notifies O that the operands are complete.

When the operand is written, the operand fetch unit 0FLI29 continues to send the address to the bus 110 until the write data from the execution unit EU30 is output to the bus 111.

On the other hand, for (a) above, the operand fetch unit 0FU29 accesses its own general register (not shown) using the register address 113 sent from the address calculation unit AU28.

The only difference from (a) is whether memory is accessed or registers are accessed.

For (e), the contents of the bus 109 are sent as they are to the bus 111, and the execution unit () Eu2O is notified that the operands are complete. In addition, the execution unit EU30 is connected to the operation code bus 114 from the decode unit DU27.
It receives the start address of the microprogram sent via the microprogram, uses the operands on the bus 112 when reading, and outputs the operands (data) to the bus 111 when writing, and sequentially processes instructions.

Furthermore, if the instruction is a branch instruction, the bus 115 is used to
The new program counter value is sent to the instruction fetch unit I.
At the same time, it is set in the program counter 50 of the FU 25 and the DP register 69 in the DU 27 (decode unit (to be described later)), and at the same time, the processing results in each unit of the operands that were previously processed in the nocturnal line processing are canceled.

The above is an outline of the processing for one operand specifier, and each unit (25 to 30) is processed by one pipeline,
Processing of sequential operand specifiers is performed in parallel.

Next, the decoding unit 27 related to the gist of the present invention will be described in detail with reference to a specific example.

FIG. 4 is a block diagram showing a specific embodiment of the decoding unit DU 27 shown in FIG. 3.

The DP register 69 indicates the beginning of the instruction to be decoded by the decode unit DU27, and when decoding the first operand specifier, the address of the opcode is
When decoding the th and below, it indicates the first address of the corresponding operand specifier.

Since the above address is sent to the aligner ALIG 26 and instruction fetch unit IFU 25 shown in FIG. 3 via the bus 102, the first byte contains the first operand as shown in FIG. In the case of reading the specifier, as shown in the figure below, in the case of reading the operation code OP1 and below the second operand specifier, as shown in (B), dummy data, and the end flag S is stored in the second byte. The first byte of the operand specifier containing
Other information of the operand specifier is output from the 7th byte to the 7th byte.

The bus 204 is information indicating which operand is being processed, and when this information indicates that all operands have been processed, the first byte of the bus 104 is set in the operation code register 64.

The output of the operation code register 64 is sent to the operation code decoding unit 61 which obtains the start address of the microprogram of the execution unit EU30 of the corresponding naming, and the operand information R,0 having information about the operand of the corresponding instruction.
Sent to M63.

The output result 201 of the ROM 61 is the start address register 6
2 and, via opcode path 114, the first
At the same time that the operand is passed from OFU29 to Eu2O,
Sent to 2O.

The ROM 63 has the configuration shown in Fig. 6, in which information as shown in Fig. 6 is input in advance, and the information on the operation code and the number of the operand to be processed is stored in the address. It is read as .

In other words, when the first value is set in the operation code register 64, the selector 5EL81 selects the bus 20.
Since the 0 side is crawled, information regarding the first operand is read using the opcode as an address.

The information read out includes: (1) Attributes of the operand, that is, information R/W on whether it is a read operand or a write operand;
There is information indicating the data length L (byte, word, longword) of the operand, (2) a flag indicating the end of the operand, and (3) an address containing information about the next operand of the same instruction. .

(1) is output to the path 105-1 and is output to the address calculation unit (AU) 28, and (2) is output to the path 203 and sent to the decoding completed byte number detector 65.

Furthermore, the information in (2) and (3) is latched in the register 83, then output to the path 204, and used as an address for reading the next operand.

(Since the latch information of each of the four pieces of information is input to the selection terminal S of the selector 81, if the information of (2) is “l”,
The contents of the opcode register 64 (200) are used,
If it is "0", the information in (3) is used.

Meanwhile, in the bust 04, the end flag S is displayed on the indicator 65.
will be sent to.

Also, the first 7 bits of the operand specifier are the path 206
is sent to the operand specifier decoder 66.

The operand specifier is decoded using 7-bit information, and an example thereof will be explained with reference to FIG.

For example, (R, +D I S
When the operand specifier P8) is sent, it is detected that the eastern 3 bits of the upper 7 bits are 010, as shown in Figure 7, and the following information can be output.

(1) Must be an operand specifier with a length of 2 bytes.

(2) When outputting the contents of path 208 to path 106,
A 3-byte right shift is required to align the DISP digits.

(3) In order to convert the DISP value into 4 bytes, the most significant pit of DISP,l should be sign-extended and output for the upper 3 bytes.

(4) The address of the operand can be calculated using R, +DISP.

(5) The information for R must exist in the lower four pits of the first byte.

There are five. Similarly, (R) of A7 in FIG. 2(B).

+DI8P32) is sent, it detects that the upper 7 bits are 110110 as shown at the beginning of Figure 7, and the following information can be output.

(1) It is a 6-byte operand specifier, (2
] When outputting the contents of path 208 to path 106,
(3) All 32 bits of DISP are specified, so it must be output as is.(4)
The address of the operand can be calculated using R, , +DISP, and (5) the information on Ra is present in the lower four pits of the second byte of the operand specifier.

The two examples above have been shown, but if we summarize them, we get the following.

The operand specifier decoder 66 decodes the received operand specifier and outputs the following information.

(1) The length of the operand specifier is output in bytes to the path 215. For example, when an operand specifier of (FL, + DISP, ) is sent in the operand specifier of level 3 in FIG. 2 (to), ``2'' is output.

(2) To Lotus 211, Tis Placement (D'l
5P)/IM data aligner 6
Outputs the number of shift bytes for 7.

For example, in the case of the operand specifier (FL, +DISPa), as shown in Figure 7, 3 bytes right/left,
In the case of (R1+n 5 psz), a 1-byte left shift is instructed as shown in FIG. 70.

(3) Mask byte instruction data for the aligner 67 is output to the path 212 .

This corresponds to the 4 outputs to the path 106 for the aligner 67.
By instructing the mask of the upper 2 or 3 bytes of byte data, 1 or 2 bytes of DISP,
This is to convert the IM information into 4 bytes by sign extension.

For example, for DISP8, there is a 3-byte shift as shown in Figure 7, and for DISP3□, there is an extra byte called "-R5" in front of () in Figure 7, so one byte is shifted 7 feet to the left. .

This is because in the case of DISP, unless the sign bit of DISPa is expanded and inserted into the upper 3 bytes, normal address calculation of 32 pits cannot be performed. (Bus 21
2 is for that instruction) (4) An addressing controller is output to the bus 105-2, thereby instructing the operating mode of the address calculation unit AU28.

(a) to (h) regarding the addressing mode (U, address calculation unit (address calculation unit) AU28 in FIG. 3).
It has already been explained that there are eight modes.

(5) Information indicating whether the general register R4 is located in the first byte or the second byte is output to the bus 216.

(R, +DjSP&), the 1st byte, (R-+DI
5P32), the second byte is specified.

On the other hand, the index register R in the operand specifier is output to the bus 108.

Also, the selector 68 selects the portion corresponding to R- (the contents of the bus 207 or 210 contents) to bus 107
Output to.

As described above, the aligner 67 receives the second byte to the seventh byte of the operand specifier by the node 208, so it performs shift processing by the number of shifts given by the signal line 211, and also by the number of shifts given by the signal line 211. For the mask part given by , sign extension is performed and 4
Output as Nokuito data.

These are as shown in Figure 7, Figure 7.

Next, the decoding completed byte number detector 65 will be explained.

This part is also the main part when handling an undefined length instruction (one with S bit added) according to the present invention.

As described above, the decoding end byte number detector 65 includes the signal line 203 indicating the operand end fluff E, and the signal l! indicating the stop hit S of the operand specifier. i
ji! 205 and the number of operand specifiers (08
The three signal lines 215 representing DP69 are input to the signal line 215, and the added value DPINCB of DP69 is output in byte units to the signal line 214 to indicate the address of the next operand specifier.

The algorithm in this case is as follows.

If E=1, D'pINCm =08B Otherwise, if S-0, DPINC11=O8B 1 Also, if S-1, DPINCB = 0 That is, (1) Operand end flag If E is 1°', then
Since the processing of the relevant instruction has been completed, the signal is output to the signal line 214 so that the DP register 69 is incremented by the number of bytes of the operand specifier (08B) so as to point to the beginning of the next instruction.

(2) If (1) is not met and the end flag S is not set, the next operand specifier outputs the 1-byte tummy to the bus 104 as the first byte, so (number of bytes of operand specifier: 08m)-1 is output to the signal line 214 so as to be added.

(3) If (1) is not satisfied and the end flag S is set, "0" is outputted so that the DP register 69 takes the same action. As a result, the same operand specifier is used to process the next operand, and the same operand is used repeatedly.

FIG. 8 shows a hardware configuration for realizing the above algorithm in the decoding completed byte number detector 65.

In other words, in the case of E-1, the output gate 301 is opened, the content O8B of the bus 215 is output to the bus 214, and E=
o, the output gate 303 opens when s=o, and 08
When BI is output and S21, the output gate 302 is opened and "0" is output.

Also, when E is 1, if the S bit is not 1, it means that it is detected that there are more operand specifiers than the number of operands, and in FIG. 8, AND gate 304 is turned on and signal 105-3 is detected. Output and address calculation unit)A
U28 is notified of the occurrence of the corresponding error.

In the address calculation unit AU28, the code 105-3 is assigned to the following unit (operand fetch unit) OFU2.
9), and finally the execution unit () Eu2O is notified of the error occurrence.

In FIG. 8, 304 and 305 are inverters, and 30
6, 307 is an AND gate, and 308 is a subtracter.

The adder 71 adds the current value of the DP register 69 and the value of the signal line 214, and outputs the address of the next operand specifier to the bus 102 by setting it in the DP register 69 via the selector 70. becomes possible. As a result, AL I G26 sets the next operand specifier as shown in Figure 5.

It can be output to the bus 104 in the format shown in (B).

On the other hand, by selecting the contents of the bus 115 and setting them in the DP register 69 using the selector 70, it is also possible to change the DP register 69 in the aforementioned branch instruction.

Note that the adder 72 adds the value of the signal line 215 (08m) indicating the length of the corresponding operand specifier to the value of the DP register 69.
) and the carry input ``'1'' outputs the next address of the operand specifier being decoded to the bus 116.

Address calculation unit) AU 28U uses the contents of the bus 116 as the value of the program counter PC used for address calculation.

As described above, according to the present invention, the operation code and the operand specifier are independent, and the length of the operand specifier can be set arbitrarily, and one operation code can be used to write an A○B-+C type instruction. Both types of instructions, such as A, B' - + B, can be expressed by optimizing the amount of information for each instruction, increasing the number of instructions that can be specified with an opcode of the same length.

In other words, when the opcode lengths are the same, according to the present invention, more high frequency functions can be added.

Furthermore, by checking the rationality of the number of operands and the number of operand specifiers, the error detection rate can be improved.

In the above embodiment, the end flag S is added to the most significant bit of the operand specifier, but it is not necessarily limited to this part, and the end flag may be provided somewhere in the operand specifier.

Furthermore, in the above embodiment, the same operand is repeatedly used multiple times, but this is achieved by repeatedly decoding the same operand specifier without updating the contents of the DP register 69. In addition to this, a special signal may be sent from the decoding unit to the execution unit EU30 to instruct it to repeatedly use the previously obtained operand.

[Brief explanation of the drawing]

Figure 1 is a basic conceptual diagram of a data processing system to which the present invention is applied, Figure 2 (2) is a diagram showing the format of an indefinite length instruction and the format of an operand specifier used in the present invention. , FIG. 3 is a block diagram of a specific embodiment of the central processing unit of FIG. 1, and FIG. 4 is a block diagram of a specific embodiment of the decoding unit of FIG. 3, which is the main part of the present invention. , FIG. 5 is the format of the operand specifier used to explain FIG. 4, FIG. 6 is an explanatory diagram for explaining the contents of the operand information ROM 63 in FIG. 4, and FIG.
This figure is an explanatory diagram used to explain the operation of the operand specifier decoder 66 in FIG. 4, and FIG. 8 is an embodiment diagram showing the hardware configuration of the decoding process completed byte number detector 65 in FIG. 4. 27...Decode unit, 61...Operation code unit, 63...Operand information ROM. 65...Decoding processing completed byte number detector, 66...
・Operand specifier decoder, 205...End information 1
1 ro 296- '#l 2 ε (A) horse 3 z 40th 謬 5 mouth (3), 5 0,3 a person 15
2 204 1t) J3 byte mask 105-. 3 Continued from page 1 0 Inventor: Takeshi Kato, 5-2-1, Hitachi Omika-cho, Hitachi, Ltd. Omika Factory, Hitachi, Ltd. 0 Author: Hiroaki Nakanishi, 5-2-1, Omika-cho, Hitachi, Ltd. Hitachi, Ltd. 0 inventions in the factory Author Tetsuya Kawakami 3-2-1 Saiwai-cho, Hitachi City Hitachi Engineering Co., Ltd. Applicant Hitachi Engineering Co., Ltd. 3-2-1 Saiwai-cho, Hitachi City 299-

Claims (1)

[Scope of Claims] 1. In a data processing device that handles an instruction in which an operand specifier that specifies the addressing mode of an operand is independent of an opcode portion that specifies the type of processing and the number of operands, the instruction The decoding means includes at least operation code decoding means, operand specifier decoding means, and end information detection for detecting the end information added to the operand specifier. When the end information detection means detects that end information is set, it is determined that one instruction is formed including the operand specifier, and the instruction is processed. A data processing device that handles undefined length instructions. 2. If the end information detection means detects that end information is set before the operation code decoding means outputs a signal indicating that the operand is the last, the same operand is used again. A data processing device that handles an indefinite length instruction according to claim 1. 3. If the end information detection means detects a set of end information before the operation code decoding means outputs a signal indicating that it is the last of the operands, the end information detection means detects the set of end information, which is currently used as the address of the operand specifier to be read out to the decoding means next. 3. A data processing device for handling indefinite length instructions according to claim 2, wherein the same operand is reused by reusing an address therein.