JPS583443A - Private packet communication system using ring-shape transmission line - Google Patents

Abstract

PURPOSE:To realize the communication of plural routes at one time between optional terminal devices via a ring-shape transmission line of a simple constitution, by using a packet of a fixed length including the transmitting and receiving addresses. CONSTITUTION:A received signal A is supplied to a phase synchronizing oscillator PLG as well as to a packet receiver PKR. The clock pulse B generated from the oscillator PLG is synchronized with each bit of a receiving packet PK. Based on the pulse B, the receiving address RAF is discriminated. When the coincidence is obtained between the address RAF and the address of the own station, the presence or absence of an error is decided in response to the information of a data frame DAF and an error detecting frame EDF. Then the information of the frame DAF is converted into a receiving data C and then fed to either one of terminal devices TM1-TMn via a connecting circuit CON and in accordance with the designated information in the frame DAF. A data packet TP is set at a fixed length and suited best to a telephone requiring the transmission of a constant speed or the transmission of an electrocardiographical waveform, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a local packet communication system used for local data communication such as in an office automation system.

A common transmission path is used for such data communication, and this is called a data highway system. A conventional example of applying optical communication to this method is the one shown in the block diagram in Figure 1. .

That is, in the figure, a central office C having a switching function
8, terminal stations 'rngi to TD8n are connected as a bidirectional optical fiber GL loop, and the signals based on the primary group PCM communication system are further multiplexed to achieve high-speed optical communication. is being carried out.

In this case, the fundamental frequency of the primary group is set to 1.5 4 4 MH
z, the bearer communication speed is 64 Kbps, and the communication capacity is 24 channels. Among these channels, a control channel is provided, and information for exchange control is exchanged, and the central station c8 Since switching connections are made between each channel, the central station C8 requires a high degree of reliability, and the configuration of the central station C8 is complex and expensive, making it unsuitable for local communications. This results in some disadvantages.

On the other hand, a packet switching method is used to distribute the switching function to each of the terminal stations TD81 to TD8n, and in this case, a transmission signal having the configuration shown in FIG. 2 is used.

That is, synchronization fields 8 each consisting of multiple bits.
YF, receiving side address field RAP, sending side address field TAF, 7' data field DAF
and the error detection field ICDP K), which constitutes the packet, and each address field RAF and TAF.
Since the receiving side address information and the sending side address information are transmitted by the receiver, the receiving side and the sending side are individually specified, and an individual route between the sending side and the receiving side is set based on this. Ru.

In addition, as an example of a dormitory using the packet switching method, there is a "data communication system" (Japanese Unexamined Patent Publication No. 5
1-114804) has the configuration shown in the block diagram of FIG.

In other words, a plurality of communication nodes (Nod●) are provided for the bidirectional transmission line TL terminated by impedance Zd, and these node devices NICs-NICH are connected to each other. Transmitting/receiving section T via branch section BL
RX and control unit C are provided, and control unit CTK is provided.
Terminal devices 'f'Ms to TMn are connected.

Note that the transmitting/receiving unit TIIX has a modulation/demodulation function of the transmission signal and a function of detecting a carrier wave in the transmission path TL, and the control unit C
T, has a packet disassembly and assembly function, and a function to detect a collision that occurs simultaneously between a received packet and a transmitted packet, and the packets used in and \ have the same configuration as in Figure 2. It becomes.

Therefore, when any of the terminal devices 〒M, to TMn enters the transmitting state, the control unit CT converts the transmission data into packets and provides them to the transmitting/receiving unit τRK according to the ζ error. The transmission signal in the form of a packet is transmitted to the transmission path TL via the transmission line TL.

This transmission line is received at the same time by other node devices NE, ~N]Cn, and the receiving side address information is decomposed into pieces by the device that is connected to itself, and the data in the packet is It is sent to its own terminal device.

In addition, the above-mentioned carrier wave detection function enables transmission only when the transmission path TL is in a no-signal state. When a packet collision is detected during a packet collision, it immediately stops its own transmission.

However, in the case of FIG. 3, the temporal length of the data frame DAF changes depending on the amount of transmitted information,
This causes fluctuations in the required transmission time of packets, making it inconvenient to digitize and transmit analog signals such as voice signals and waveform signals that require constant speed transmission. This results in drawbacks that make it unsuitable for transmission.

Furthermore, in Fig. 3, a coaxial cable or the like is used as the transmission -τL to perform bidirectional transmission, but if an optical fiber or the like is used as the transmission line TEL, bidirectional relaying can be performed with a simple configuration. However, there is also the disadvantage that the same function cannot be achieved using a unidirectional transmission line.

The present invention has the purpose of fundamentally solving the drawbacks of the conventional technology, and has the purpose of connecting each node device in a unidirectional transmission path in a shilling shape, and using a plurality of bits for receiving and transmitting side addresses. By using transmission signals in the form of fixed-length packets containing information, the functions required for local communication are fully realized.

The present invention provides an extremely effective local packet communication system using a ring-type transmission path.

Hereinafter, the present invention will be explained in detail with reference to FIG. 4 and subsequent figures showing embodiments.

FIG. 4 is a block diagram showing the entire configuration, in which a plurality of node devices Nll to NEn are arranged in a ring configuration along a transmission line 8L using an optical 7-iper that performs unidirectional signal transmission as shown by the arrow. As shown in FIG. 5, each node device WE, -NEn transmits a fixed-length IP bucket) PK, and also sends a PK of a receiving side address frame RAP. When oneself is specified by the information, this packet PK is received as a packet addressed to oneself.

Therefore, since the PK (bucket) is defined as a fixed time length ip, the time width of the data frame DAP is also constant6, and the same amount of data is always transmitted by this, and it is difficult to transmit audio signals, waveform signals, etc. This makes it suitable for transmission.

FIG. 6 shows node devices NL to NEn corresponding to the first invention.
It is a block diagram showing the configuration of the receiving section RX, which includes a light receiving element, a demodulating circuit, etc., and receives the optical signal from the transmission line 8L, and receives the received signal (4) obtained by the transmission during relay operation. The signal is sent to the transmitter consisting of the modulation circuit, the circuit, the light emitting element, etc. via the switch 8W of the analog switch circuit cape in the state shown in the figure, and the received signal is converted into an optical signal again and then sent to the transmission line SL. is being sent to.

On the other hand, the received signal (4) is given to the phase synchronized oscillator PLO and the packet receiver pin, and the oscillator PL
Packet P received by ) of the clock pulse generated by O
Based on this, the receiver PKII is in a state synchronized with each bit of K. Based on this, each bit of PK is extracted by sampling, and it is specified by the information in the receiving side address frame 8. data frame D
t according to the information of AF and error detection frame KDF.
After determining the presence or absence of ab and converting the information in the data frame DAF to received data (b), the connection circuit CON
The data frame DAF is sent to one of the terminal devices TMI to iMn according to the specified information in the data frame DAF.

Furthermore, if any of the terminal devices TMI to TMn enters the transmitting state, the transmitting data (b) is sent as a packet transmission 1! via the connection circuit CON. PH7 and transmitter PKT
Assembles the packet PK based on the clock pulse (B)K and sends it out as the transmission number (G). At the same time, it sends out the switching signal (G) and switches the switch 8W to the packet transmitter P.
In order to switch to the KT side, the relay operation is cut off, and the transmission signal (2), which has been made into a bucket) PK, is converted into an optical signal and transmitted from the transmitter TX.

When starting transmission from itself, the phase-locked oscillator PLO is in an asynchronous state. Based on the clock pulse 01)K, the bucket (PK) to be transmitted is assembled.

Note that the transmission of the bucket) PK is performed on the premise that no transmission is being performed from other node devices NE, and to ensure this, a carrier detector CAD and a collision detector COD are provided.

That is, the carrier detector CAD detects the presence or absence of a carrier wave component based on the branched output of the receiving section RX, and uses the detection signal (G) of this to prohibit the operation of the packet transmitter PKT and simultaneously transmit multiple signals. Considering the case where the node device NK starts transmission, the collision detector COD detects each of the transmitted and received packets based on the packet output (6) of the packet receiver PKH and the packet output (I) of the packet transmitter PKT. If bit duplication is detected and the two are the same, it is determined that the packet PK sent by the self has been received after going around the transmission path 8L, but if the two do not match, the packet PK from another packet is determined to have been received. received and different buckets) PK
It is determined that the book has caused a collision, and the operation of the packet transmitter PIC'r is prohibited by a detection signal (J).

If the PK is received after going through one cycle, there may be a delay on the transmission path and there may be bit errors, so countermeasures should be taken to deal with these. Moreover, it performs the aforementioned detection. , this connection circuit CON has the function of storing and transmitting the transmission data from the terminal devices Mt to TMn, and transmitting it as transmission data (2), Depending on the terminal equipment TMl
. . . iMn.

Therefore, the configuration of FIG. 6 not only realizes the same functions as those of FIG. 3, but also allows the transmission of audio signals and waveform signals as well as the transmission of digital data signals.

Fig. 7 line, node device corresponding to the second and third inventions)
This is a block diagram showing the configuration of JIS ~) IIIn.
The time slots for time division multiplex communication shown in FIG. 8 are used for PK transmission.

In other words, time slots t1 to tn
is repeated for each time slot t!
~tnK are the same frames as in FIG. 5, 8YF, RAF,
TAF, DAFllDF (multi-configured bucket) P
K is inserted and each of these frames BYF, RAF,
TAF, DAF, and IDF each consist of multiple bits.

Therefore, if the bit length of the data field DAF included in one bucket) PK is Mbit, then the average transmission rate per one time slot is v=TXM(b
ps), and since each of the time slots t1 to tn can be regarded as one channel, in the example of FIG. 8, the number of channels is n1 and each channel has a transmission capacity of an average transmission rate V.

Also, time slot 1. Since the repetition period i' of -1n is constant, the time width of each of the time slots t8 to tn is also constant, and a fixed packet length ip is determined accordingly.

In addition, each time slot t1 to tn is set in advance.
- A single or multiple slots are assigned to each card device Nil to N]Cn, and the information in the sender address field TAF indicates the time slot number into which the packet PK is inserted. There is.

Therefore, similarly to FIG. 6, the received signal (4) in FIG. 7 given from the receiver RX is given to the phase synchronized oscillator LG and the packet receiver PKR, and the received signal (4) of the same oscillator PLO
Packet P received by clock pulse (B) generated by
The state is synchronized with each bit in PK, and based on this, the receiver 1'Kl is a bucket). Each bit of PK is extracted by sampling, and it is designated by the information in the receiving side address frame RAF. When the error occurred, the information in the sender address frame TAF is decoded and sent to the timer TIM as address information (6) indicating the time slot number of the received packet PK, and one data frame DAF and error detection frame EDF are sent. The presence or absence of an error is determined according to the information in the data 7 frame DAF, and after converting the information in the data 7 frame DAF to received data (Q), it is sent to one of the terminals W TMI to TMn via the connection circuit CON. .

The timer TIM has their configuration, and if any of the terminal devices (M1 to iMn) is in the transmitting state, it memorizes the address information (6) and sends a clock pulse)
The time slot number indicated by address information (6), the count number of clock pulses (11), and K are assigned to the self based on the time point given in address information (a). When the determined time slot reaches the start point of the determined time slot, the time slot signal ■ is transmitted as a packet R1FPK?
give to

Then, the packet transmitter PKT connects 1ICON
The transmission data (b) from the terminal devices TMI to TMn via is assembled as a packet PK according to the clock pulse (6), and from the time when the time slot signal (■) is given, it is 1,
The packet PK is inserted into its own time slot together with the packet PK in other time slots to be relayed in order to give it as a transmission signal to the mixer MIX inserted in the switch BwO switch shown in Figure 6. Bucket by transmission number work)P
K is transmitted by the transmitter TX&.

Then, the packet transmitter PKT sends the transmission number (2).

That is, firstly, the address information (6) is not stored in the timer TIMIC, and the clock pulse (B) is counted and assigned to Shizuku in an empty initial state. There was no fist wave detection signal (G) from the material detector CAD for the time 40,
A no-signal condition is determined for the period in which the own time slot is longer than period 1 in FIG. 8.

Second, 1. Packet transmission @ The transmission signal (g) from PKT is sent to the above-mentioned Shibakerato receiver PKR.

is received, does not cause collisions with other packets, and detects the detection signal (
J) is the condition under which it is not sent.

Note that when starting transmission from the self, the timer is activated based on the asynchronous clock pulse (to) and the transmission request signal from the terminal devices TMt to teMn via the connection circuit CON. Since the TIM sets its own time slot and sends out the time slot signal color,
The transmission number (6) is sent from the packet transmitter PKT under the above-mentioned conditions.

Terminal equipment TMs accommodated in the nonide device NE at ζ\
The following is a consideration of the relationship between the number of TMn units, communication speed, and time slot allocation.

(1) The number of terminal devices TM accommodated in each node device NEt-NICn is 11. A case can be considered in which the communication speed is equal to the average transmission conductivity V per channel according to the time slot 7), and in this case, due to the configuration shown in FIG. You can always fight against your enemies.

(2) Terminal device accommodated in a specific node device HE
If there are m devices and the communication speed of each channel is equal to the 1,000 average transmission rate of the channel, or if the number of terminal devices TM accommodated in the specific node HE is one Deishi,
It is conceivable that the communication speed is m'×v, and in this case, for a specific node device MW, m
Channel Sunawa? , m time slots must be allocated, and the controller CN'l'' in FIG. 7 is required. □(3) Specific /-'b' device NI
There may be a case where there are m terminal devices TM'il' accommodated in channel G, and the communication speed of each is much slower than the average transmission speed of channel mb. One channel, that is, one time slot, is allotted to a specific node device Nl, and this is switched in a time-division manner to share it with m terminal devices starting from M, and the switching function is performed to the connection circuit CON. By adding ti', this can be handled using the same configuration as (1). Note that this method is called subcommutation in the field of cyclic digital command telemeters.

(4) Terminal equipment TM accommodated in multiple node devices Nl
In this case, it is sufficient to allocate one channel to multiple node devices TH. The configuration shown in FIG. 7 can handle the problems described later.

Therefore, in FIG. 7, a controller CNT is provided, so that the high communication speed terminal equipment TM temporarily occupies a plurality of time slots. This is something that can be dealt with.

That is, the controller CNT monitors the disappearance of the carrier wave in each time slot based on the carrier wave detection signal side, and detects the disappearance of the carrier wave and the operation signals (materials) from iTMs to TMn to the terminals via the connection circuit CON. ) is applied to the timer TIM in response to the control signal Φ), detects an empty time slot in which the carrier wave has disappeared, and causes the time slot signal υ to be sent to this empty time slot as well. .

Then, the controller CNT monitors only the operation signal ■ of each terminal device 1M1 to 1Mn via the connection circuit C ('IN) and sends the control signal ψ to the timer TM when detecting the stoppage of operation. The time slot signal ■
It may also be possible to cause the transmission to be performed.

Figure 9 shows the controller C8 and timer T in Figure 7.
This is a block diagram showing details of IM and timer TIM.
In addition, a slot counter such as a ring counter that repeats a full count and repeats counting by the same number of timeslots tl to J shown in FIG. 8 is used.
Bucket shown in Figure 8) A full count equal to the number of bits in the PK, and a 7-frame counter CUTν such as a ring counter that repeats the count, as well as time slots assigned to the self corresponding to the terminal devices M1 to TMn. A register RE whose contents are undetermined and is used to hold a number or use a predetermined number m of time slots.
When Gl-RWGt is provided and address information (6) converted to a time slot number is given, this is preset to the slot counter CUTg as a count value, and at the same time, the frame color/re CUTi is reset. 1) When the transmission request signal is turned on, the frame counter CUT immediately starts counting clock pulses, and the counter CUT sends out a frame pulse for each packet length Tp. Suru.

Therefore, the slot counter CUTg counts frame pulses based on the preset time slot number, and its count output is the received packet P.
This indicates the number of the time slot synchronized with K.

The count output of the slot counter CUT is the exclusive OR (hereinafter referred to as EXOR) of the number of bits of the slot counter CUT and the corresponding number.
EXOR circuit GGI, which consists of a gate and an OR gate that takes these outputs as input, is compared with the held output of registers RIG and ~REGt, and when they match, a match signal is sent to the XOR circuit aa and ~GGt. This is given to the MND game) Gs via the OR game) Gs, and the AND game) Gs is outputted according to the judgment signal sent from the judgment circuit JUD as described below. If so, it is sent out as a time slot signal ■.

Therefore, a required time slot that is synchronized with the received packet is determined by sending the time slot signal (2).

On the other hand, the controller CNT selectively connects and supplies the operating signals (Nt) to (Nn) from the terminal devices T to TMn via the connection circuit CON to the judgment circuit JUD. The first stage stake 81 and the final stage stake sn are connected in a loop, and the terminal device TM
I % TIIIH and the same number of stakes8. A shift register 8RG having . A single bit in the shift register SRG is applied to each stake 8 of the shift register 8RG synchronously with the counting operation of the slot counter CUi- according to the frame pulse from the frame counter C'UT.
1 to 8n are sequentially circulated.

In addition, in the matrix circuit MTX, the operation signal (N
s) ~(Nn) are connected by internal cross points according to the order of the time slots assigned to the terminal equipment TMI ~TMn, and are fed to the judgment circuit JUD, and the output of the shift register 8RG is connected to the determination circuit JUD. Since a judgment signal is generated by the coincidence of
Only when the timing of the match signal from
A time slot signal ■ is to be sent.

Note that the matrix circuit TMX receives operation signals (N1) to (
Nn) can be periodically sampled by a microprocessor, etc., and the operations equivalent to connecting cross points can be processed by a program. It's okay.

In addition, when the carrier wave detection signal is applied to the AND gate G4, and when the AND gate G4 is turned on in the non-detection state, the frame pulse is transmitted through the distribution circuit DI8 which sequentially switches the distribution output according to the frame pulse. Since the register BEGz-J -RIGz is given sequentially as a hestrope signal, the count output of the slot counter CUTI is sent to the register RIGj-j- every time a non-detection state occurs.
R1℃t is set sequentially, and the time slot signal ■ is sent out according to the time slot number indicated by the count output, and the high communication speed terminal equipment 7
In addition to the allocated time slots,
It becomes possible to occupy empty time slots.

Therefore, in the configurations of FIGS. 7 and 9, time slot allocation for the case (2) described above is realized.

However, if an empty time slot is occupied forever,
In order to cause inconvenience to other node devices NE, it is necessary to reset the time slot number held in register IIIG4g-REGt, and some functions must be added.

That is, when transmission from the node device NE whose empty time slot is the assigned time slot is resumed,
As mentioned above, since a packet collision is detected in the packet receiver PKR, its detection signal (J) resets the register RIG that holds the time slot number where the collision occurred, and uses other empty time slots. , it can be assumed that it occupies a new empty time slot.

Note that when resuming transmission from the node device NIG whose assigned time slot is an empty time slot, it is preferable that a dummy packet containing no valid data is first transmitted.

The timer TMId used for (1) above
, the timer TIM in FIG. 7 may be slightly simplified and six timers may be used.

In the case of (4) above, transmitter address information from a packet transmitted by a node device NE sharing the same time slot is given as address information (6) to the timer TIM shown in FIG. , the full count number of the slot counter CυD- is determined according to the number of shared node devices in the same time slot, and the full count number of the frame color CUTF is determined for each node device Nl.
This can be determined according to the number of bits of the packet transmitted by e, and by this, the own transmission time can be determined based on the relative relationship between the transmitting side address information from each node device NIC and the count number of clock pulses @). When the 2nd ring is determined, it is possible.

Note that when multiple high communication speed terminal devices TM are provided, all time slots t1 to tn may be equally divided and allocated to each high communication speed terminal device TM, but A control packet is used to transmit control information, and by transmitting this control packet, the other node devices Nl are notified of the occupancy of multiple time slots, high-speed communication is performed using multiple time slots, and after this is completed.

If a control packet including control information for release of occupancy is to be transmitted to a limited number of time slots t1 to tn
can be used effectively. 4. The characteristics of each signal shown in FIGS. 6 and 7 can be arbitrarily selected according to the conditions, and in FIG.
GRX04% OR gate Gλ is NAND gate, NO
The same effect can be obtained even if the transmission line is replaced with an R gate or the like, and a general transmission line may be used as the transmission line 8L, and various modifications are possible.

As is clear from the above explanation, according to the present invention, any terminal equipment can be simultaneously connected to each other using a ring-shaped transmission line, which has a simple configuration due to its unidirectional nature, without providing a centralized exchange function. In addition to enabling communication over multiple routes, since communication uses fixed-length packets, voice signals, waveform signals, etc. can be transmitted along with data signals, and high-speed communication can be freely performed by effectively utilizing empty time slots. The special mission of Garu etc. has been realized, and it has a remarkable effect on communication between various terminal devices installed in the premises.

[Brief explanation of the drawing]

Figures 1 to 3 show conventional examples. Figure 1 is a block diagram for optical communication, Figure 2 is a diagram showing packets used in the packet switching method, and Figure 3 is for the packet switching method. Block diagrams, FIG. 4 and subsequent figures show embodiments of the present invention, FIG. 4 is a block diagram of the entire configuration, FIG. 5 is a diagram showing packets, and FIG. 6 is a block diagram of a node device corresponding to the first invention. , FIG. 7 is a block diagram of a node device corresponding to the second and third inventions, FIG. 8 is a diagram of time slots and packets, and FIG. 9 is a block diagram showing details of the timer and controller in FIG. 7. be. 8L...Transmission line, 8,~NEn...Node device, Rx...Receiving unit, TEX...Transmitting unit, MIX
...Mixer, PLO...Phase synchronized oscillator, PK
II-...Packet receiver, PK'T...-Packet transmitter, TEIM...Timer, CNT...Controller, tl"tn...Time slot, PK...
・Packet, RAF...1 bit Receiving side address field, TAF---... Sending side address field)', (it
3"・11s clock pulse, (6)・11-・address information, (rotation)... time slot signal. Patent applicant Hitachi Electronics Co., Ltd. Agent Yamakawa administration (1 person) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (3)

[Claims] (1) A plurality of node devices each having a terminal device are connected in a ring through a unidirectional transmission path, and fixed-length packets containing multiple bits and receiving side address information are used as transmission signals. Furthermore, each bit of the received packet is sampled based on a clock pulse synchronized with each bit of the received packet. (2) For time division multiplex communication, in which a plurality of node devices each having a terminal device are connected in a ring shape through a unidirectional transmission path, and fixed-length packets containing multiple bits and sender address information are formed. Using the transmission signal inserted into the time slot of i, the time slot assigned to itself is determined by the clock pulse synchronized with each bit of the received packet and the sender address information indicating the time slot number, and A local packet communication system using a ring-shaped transmission path, characterized in that the transmission signal is transmitted in time slots. (3) For time-division multiplex communication, in which multiple node devices each having a terminal device are connected in a ring shape through a unidirectional transmission path, and fixed-length packets containing multiple bits and sender address information are formed. In addition to using the transmission signal inserted into the time slot of the received packet, a clock pulse synchronized with each bit of the received packet and the sender address information indicating time slot No. 1 are used to find the time slot assigned to the self. An empty time slot caused by one of the terminal devices stopping operation is detected, and the time slot allocated to the self is detected using each of the time slot and the time slot allocated to the self. A local packet communication system using a ring-shaped transmission path, characterized in that the transmission signal is transmitted at a higher speed than the average transmission speed of the slot.