JPS5833940A - Charger for battery - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a battery charging device, and in particular to a charging fold #t equipped with a pair of charging terminals to which a battery to be charged is detachably connected and a memory circuit for storing the charging voltage of the battery. In the conventional device, the battery to be charged is connected to a pair of charging terminals, the start switch is temporarily closed, the memory a*t is reset, and then the battery is connected to a pair of charging terminals. The present invention solves this problem after the charging of the battery is completed.

The conventional start switch can be omitted by quickly resetting the memory circuit when a no-load state is detected when the battery is removed from a pair of charging terminals. The following is a description of the present invention based on the drawing 1fIltP. 1M1 is an electrical circuit diagram of the device according to the present invention.

The voltage of the AC power supply is stepped down, and the stepped down voltage is adjusted and smoothed to obtain the m voltage. The DC voltage frame charging/switching circuit (2) is connected to a pair of charging terminals (Pl) (P2) K mark 71E1 through a parallel circuit of the collector-emitter of the circular first transistor (Ql) and trickle charging path 13). At the same time, it is applied to a single line circuit of a diode (Dl) and a capacitor t (Of), and a constant voltage (
TO) t-obtain. The board constant voltage is applied to various fl* which will be described later ・@1 transistor (Ql) collector base [Wj[2] The emitter collector of transistor (Ql) is connected to 1 transistor (1) (Q2) ll3)
The base-emitter IIc of the third transistor controlled by the transistor (Q) is controlled by the fourth transistor (C
The collector and emitter of the fourth transistor (4) are connected to fL, and the voltage (vs) of the abnormal low voltage sensing circuit (4) is applied to the base of the fourth transistor. The sensing circuit has a pair of charging terminals (
It senses the abnormally low voltage of the battery pack 03) connected between Pl) (P!) and is released as shown below.
That is, a series circuit (41) of a resistor (R1) and a capacitor (C2) is connected to a VC between a pair of charging terminals (pt) (p2).
), the resistor (R) to which a constant voltage (Vo) is applied, the first constant voltage element (Zl) t, the M1 reference voltage circuit (42) connected in series, and the voltage (vl) of the capacitor (C2) The voltage of the 11 constant voltage element (zl), that is, the first reference voltage (V
2) Consisting of a first comparator circuit (COl) that produces a high level output (Vi) when it is smaller than the battery pack (
While Utsubo consists of one row of 8 unit cells (B1) connected,
The first reference voltage (42) is set corresponding to the rz(t1) battery voltages. For this reason, one of the eight unit batteries (B1)
When more than one battery is internally shorted, the sensing circuit (4
) will be at a high level.

(5) Make it into a memory circuit! It stores the voltage corresponding to the peak point voltage of the charging voltage of the battery back (B), and is an electrochemical potential storage element (M).
A second reference voltage (v4) of a second reference voltage circuit (6) to which a constant voltage (irradiation is applied) is applied to the element 'vc via the first analog switch (ASl) and the resistor (R5)'! #11 Analog switch (ASl) H second comparison circuit (
CO2) high level output IC.

At this high level output, the battery voltage a! 1 partial voltage (vs) is given when the storage voltage (v6) of the storage circuit (5) is larger. This first partial voltage (vs) Hl pair of charging terminals (P
l) Obtained from the voltage dividing circuit (7) provided between P' and the voltage dividing circuit includes resistors (R4) to (RlG), potentiometer (P), and g2 constant voltage element (z2). and capacitors (qx) (B4) (C5) & Icx.
vs. high voltage. This second partial voltage (vl) is the storage voltage (v6) of the storage circuit (5) and the third comparison circuit (CO
The comparison output (v8) is applied to the base of the third transistor (Qj). Third comparison circuit (
A detection circuit (8) is configured to detect a predetermined state of charge ll of the Cog)H battery pack (9).

(9; C) The no-load detection circuit is connected to a pair of charging terminals (Pl
) (72) is used to detect a no-load state in which the battery pack body) is not connected, and is configured as follows:
A pair of charging terminals (PL) (R2) are connected in parallel.
R11) series circuit (91), a resistor (R12) to which a constant voltage (To) is applied, and the 41st! Voltage meson (Zn)
ggj quasi-voltage circuit (92) (!:, I [column [1 path (9
t) 111 pressure (vy) is the third reference voltage (b) path (92
) is comprised of 514 comparison circuits (004) that generate a high level output (Vll) 2 when the voltage is higher than the third reference voltage (vlo). Parallel to this high level output (Vll) and L memory electron (transfer)! 1! The installed second analog switch (Le2) 2 is substantially closed, and the memory voltage (Vi)t of the memory element is discharged to reset the memory circuit (5).

μ is a charging display circuit, consisting of a resistor (R13) to which a constant voltage (To) is applied, the collector/emitter of the fifth transistor (LS), and an indicator light (L) in series. At the base of C5): is the resistance (
IN 4 ) A constant voltage (vO) is applied through f.
(C6) is a wE6 transistor, and its collector #
A constant voltage &E (VO) is applied to C through a resistor (IHs). Its collector is a diode CD2)? via j15) Base IIc1wI of transistor (Qs), 6
The emitters of the transistors (C4) are respectively connected to ground 'r'', and the output (Vl 1 ) of the fourth comparator circuit (CO4) is applied to the base of the transistor (C4).

Frame, diode CD on the base of the drop 5 transistor US)
The output of the third comparator circuit <aOS) (V-
) is applied. In the figure, WIi1 indicates the power supply display circuit.

In the above configuration H, the charging voltage characteristics of the normal battery pack (B) are shown by (71) in Figure 82, tl, % peak point (
b) t- and then decreases. In this decreasing region, the charge amount characteristic (Q) of the battery pack (Im) is fully charged.Now, connect the discharged battery pack (B) to a pair of charging terminals (Pl
) (R2), the no-load detection circuit (9
)'s output (V'11) switches from high level to low level9. Turn the second analog switch (MuBx) into
RfC. On the other hand, voltage divider circuit +7M) JII2 voltage divider (vl
) is larger than the storage voltage (vm) of the memory circuit (5), and the output C・) of the third comparator circuit (icos) becomes high level, so the third transistor (Ql) becomes conductive due to this output. Due to the conduction of N1 and the second transistor (Ql) (Q2), the battery 8121 is quickly charged. Therefore, when the battery voltage rises, the first partial voltage (v5) of 71 becomes higher than the memory voltage (vm), so that the voltage increases to 1 to 2 (CO2). Output>
("I 12 )" is turned on, and the first analog switch (MuS<) becomes substantially closed, and the storage voltage (
vm)a follows the first partial voltage (v5) and becomes equal to the first partial voltage, thereby opening the first analog switch (St).Thus, the memory voltage (vm)? ! The charging voltage characteristic (vm) follows the 111 partial pressure (v5) at the peak point ('b) and the time (tl) t, but after one time point (tl), the battery voltage decreases from the peak voltage, so the second Since the output (Vt t ) of the ratio circuit (002) becomes low level, the first analog switch (ASl) is held open. N2 in proportion to the decrease in battery voltage after time (tl)
At the time (t2) when the partial voltage (vl) decreases and becomes equal to the storage voltage (Vj)K corresponding to the battery voltage at the peak point (b), the output (Vll) of the third comparison circuit (005) is vx
- level, and the third transistor (0, 3) is turned off, so that the first and second transistors (Q, 1
) (Q2) is cut off and charging of the battery pack (B) is completed. In this case, between time points (tl) and (t2), the 11111 partial pressure (75) of the Nemo voltage dividing circuit (7) 7@2 partial pressure (v
1) is determined by the differential voltage (77-v5).

Therefore, the no-load detection circuit (9) detects the no-load state 11 when the battery pack CB) is not connected to the pair of charging terminals (Pl) (F2) and reads the memory surface II t511-. Now, its operation will be explained with reference to the operating characteristic diagram shown in FIG. Time in N3 diagram! (tl) connect zero hack (E) Th pair (7) charging terminal (Pl) (F2) Seki IIc.

At time (t4), the charging ends, and at time 1 (tS), the battery pack is removed from the charging terminal (PI) CF2).The voltage of the series circuit (91) increases until time (tS). (V?) A substantially constant voltage (barrel) corresponding to the no-load voltage between the frame and the pair of charging terminals (Pl) (F2), which is higher than the *S reference voltage (Vlo)!!^, therefore, the fourth The output (Vll) of the comparator circuit (W04) is at high level, and the 27th
vinegar. /Switch (AS2) Q substantially closes and the memory circuit (5) is activated. Therefore, the memory voltage of the memory circuit is zero volts - In this state, at one time point (tl), the battery pack CB ) is inserted between a pair of charging terminals (P+) (F2), and the series circuit (91) is connected in response to the voltage of the battery pack CB).
voltage (v9) is lower than the IK5 reference voltage (Vlo).

Therefore, the output (vll) of the fourth comparison circuit (004) is C
The fourth switch (is
Z) is substantially open, and the memory circuit A5) is reset! 1 at the time (tS) (i.e. memory circuit 15)
As mentioned above, the battery pack CB) is rapidly charged from that point in time, and from 1 point (tS) when the quick charging of the battery pack (B) ends at 1 point (t4) (
The voltage (V?) is the voltage (Vm) corresponding to the battery voltage (Vll) until t4), and the voltage (V?) is the voltage (Vm) corresponding to the battery voltage (Vll). )+7 charge path +31 Since it is charged via vl7, the charging current value decreases and the voltage (v9) also decreases.
At the time (tS) vc, the battery pack 俤) is removed, so at that time (tS) the voltage (
v9), the above-mentioned approximately constant voltage (laK, the fourth
The output (VZ) of the comparator circuit (004) becomes high level, and the second analog switch (A82) is substantially closed, thereby resetting the memory circuit (5). Therefore, the storage voltage (
vm) quickly decreases to zero after one point in time (tS).As described above, the frame of the present invention is equipped with a detection circuit that detects a no-load state in which the battery to be charged is not connected to a pair of charging terminals. This is because the memory circuit that stores the battery voltage, which is applied to the detection output of the circuit, is reset.

By removing the charged battery from the pair of charging terminals, the memory circuit can be reset each time the battery is charged. By connecting between a pair of charging terminals,
[Since the battery can be charged immediately and the memory circuit is reset at the start of charging, the start switch used in the conventional U.S. can be omitted.

[Brief explanation of the drawing]

Figure wL1 shows an electric circuit #llJ showing one embodiment of the I&F according to the present invention, Figure 2 shows a charging characteristic diagram, and Figure 3 shows an operating characteristic diagram of a no-load detection port. Rechargeable battery, (p+>(P2)...pair of charging terminals, t5)...memory circuit %19+...detection circuit.

Claims (1)

[Claims] (11) A charging device comprising a removable I/C dissemination device to be charged, a pair of charging terminals, and a memory circuit IIt for storing the charging voltage of the battery, wherein the battery is connected to the pair of charging terminals #C dissemination device. A battery charging device in which a detection circuit is provided to detect unloaded mt, and the memory circuit is reset by the detection output of the circuit.