JPS5833675Y2 - Pre-set and flexible pre-view software - Google Patents

Description

[Detailed description of the invention] This invention relates to a preview device for a preset type load control device, which is equipped with a storage device that stores and holds control signal groups of control states of a plurality of loads, and is capable of determining various control states of the load. Provides a device that can preview various dimming level signal groups stored at arbitrary addresses in a storage device using an indicator, especially in a dimming device that preset dimming a large number of lighting lights in theaters, television studios, etc. The purpose is to

The present inventor previously proposed a preset type load control device, which will be described later.

The present invention provides this preset type load control device with a preview device for checking the load control state stored in the main storage device using an indicator.
Before explaining the present invention, we will first explain the working principle of the preset type load control device, which is the premise of the present invention, with reference to Fig. 1, as follows: It is.

In Figure 1, a is the load, that is, a lighting lamp, and b is each lighting lamp a.
A controller that determines the dimming state of the
C is a storage element that sequentially stores and stores the dimming state determined by preset fader b for each scene after converting it into a digital quantity; A clock pulse generator, Sl is a write switch for storing the dimming level signal in the main memory device C, 2 is a first counter, 3 is a first decoder, 4 is an output voltage (analog amount) from each preset fader b
5 is an A-D converter that converts the output (analog amount) of the preset fader b into a digital amount; 6 is a multiplexer that receives the outputs of the A-D converter 5 and the first encoder 3 as input; 1 AND circuit, 7 is the first AN
In order to store the output of the D circuit 6 in the main storage device C, a temporary storage device temporarily holds the memory while the setting values of all preset faders b are converted into digital amounts by the A-D converter 5; 8 is, for example, a D that converts the output (digital amount) of the main memory device C into an analog amount and stores the state.
- An output circuit including at least a two-stage storage circuit corresponding to an execution scene and a next scene, which is made up of an analog voltage holding circuit etc. that receives the output (analog amount) of the A converter and the D-A converter and holds the same voltage. A slider voltage of a crossfader, which will be described later, is applied to each memory circuit.

9 is a dimming unit; 10 and 11 are a second counter and a second coder for obtaining address signals corresponding to each dimming level signal stored in the main storage device C; and 12 is an address signal for selecting an address signal. Selection switch S2 is a write mode changeover switch for writing memory to the main memory device C and writing memory to the sub-memory device d, which will be described later.
13 is a scene selection switch provided for each scene, d is a storage element for storing an arbitrary address signal of the main storage device C, for example, a circular sub-storage device composed of a shift register, etc., and 14 is a cyclic sub-storage device. A second AND circuit selects the address signal of the main memory C stored in each sub-storage device d according to the progress of the scene; 15 is a cross fader;
As described above, each slider voltage is applied to the two-stage storage circuit of the output circuit 8 via the polarity reversing device.

16 is a monostable multivibrator that operates every time the crossfader 15 is operated, 17 is a third counter that counts the output of the monostable multivibrator 16, and 18 is a converter that converts the output of the third counter 17 into a signal corresponding to each scene. 19 is an OR circuit, 20 is a third AND circuit that manually inputs the signals corresponding to each scene and the dimming level signal stored in the main storage device C, and 21 is a third decoder for the reasons described later. A shift pulse frequency divider is installed.

Here, the relationship between the shift pulse frequencies of the shift register of the main memory device C and the shift register of the sub-memory device d is such that, for example, one dimming level signal of the shift register of the main memory device C, that is, one word, is composed of n bits. If so, the shift pulse frequency of the shift register of the sub-memory device d is set to l/n of that of the main memory device C.

That is, a 1-bit shift in the sub-memory device d corresponds to an n-bit shift in the main memory device C.

Therefore, the number of bits of each shift register in main memory device C is set to n times that of each shift register in sub memory device d.

Next, to explain the principle of operation, first, each preset fader b is adjusted to set the first dimming state, and when the write switch S1 is closed, the first counter 2 counts clock pulses, which are counted by the first decoder 3. At the multiplexer 4 and the first A corresponding to each preset fader b as a fader address signal corresponding to each preset fader b,
It is distributed to the ND circuit 6.

The multiplexer 4 sequentially sends the output voltage (analog amount) set by each preset fader b to the A-D converter 5, which converts it into a digital quantity, and the digital output signal is sent to each first AND. It is distributed via the circuit 6 to the temporary storage device 7 corresponding to each preset fader b.

As already explained, the temporary storage device 7 sequentially stores and holds incoming digital signals until the digital conversion of the output voltages of all preset faders b is completed.

When the digital conversion of the output voltages of all preset faders b is completed, open the write switch S1, then close the write mode changeover switch S2 to the terminal side, and press, for example, 12□ of the address signal selection switch 12 to close the contact. , the first dimming state is simultaneously stored in the first address of each shift register constituting the main memory device C by the address signal 1 which has passed through the address signal selection switch 12 retained in memory.

When the storage operation of the first dimming state is completed, open the address signal selection switch 12 □, set a new second dimming state on the preset fader b, close the write switch S1 again, and first write the digital data into the temporary storage device 7. After storing the quantified dimming level signal, for example, 12□ of the address signal selection switch 12 is closed to store and hold the second dimming state in the second address of the main memory device C. Repeat the operation to store various dimming conditions in each address.

When all necessary dimming level signals have been stored, the write mode changeover switch S2 is switched to the terminal a side.

Further, in order to determine the dimming level signal to be used for each scene, the operation of storing the address signal of the main memory device C in the sub-memory device d is performed in the following manner.

For example, the first scene is set to the first dimming state, the second scene is set to the third dimming state, the third scene is set to the fifth dimming state, the fourth scene is set to the second dimming state, and the fifth scene is set to the second dimming state again. In the third dimming state...
In order to set the
Close the scene selection switch 13□ corresponding to the scene, then close the address signal selection switch 12□ corresponding to the first dimming state.
When closed, the address signal 1 corresponding to the dimming level signal for obtaining the first dimming state stored and held in the shift register of the main memory device C is transferred to the address signal selection switch 12 The data is inputted to the first address of the shift register d□ of the sub-storage device d, and is stored and held by a circular operation.

When memory retention is completed in this way, both the switches 13
．． .

That is, the first address signal of the main memory C is assigned to the first address of the shift register d1, the third address signal of the main memory C is assigned to the third addresses of shift registers 1 to d2, and the fifth address signal of the shift register d3 is assigned to the third address of the shift register d2. The address is the fifth address signal of the main memory C, the second address of the shift register d4 is the second address signal of the main memory C, and the third address of the shift register d5 is the third address signal of the main memory C. Each address signal is stored.

Each shift register d1, d2, etc. of this sub-storage device d...
The outputs of . . . are respectively given to one input terminal of the second AND circuit 14.

Since signals corresponding to each scene are input from the third decoder 18 to the other input terminal of the second AND circuit 14, the monostable multivibrator 16 operates every time the crossfader 15 is operated once, resulting in one pulse. The third counter 17 counts the pulses, and the third decoder 18 sequentially opens the second AND circuit 14 corresponding to each scene, and the shift registers d1, d2, etc. of the sub-storage device d are output.
. . are sequentially sent to the third AND circuit 20 via the OR circuit 19.

That is, when performing dimming control for the first scene, if the crossfader 15 is operated once, the second AND circuit 141 opens;
The output from the shift register d1, that is, the address signal 1 with the above-mentioned stored contents, passes through the second AND circuit 14□, passes through the OR circuit 19, and opens all the third AND circuits 20.

At this time, shift registers C1, C2 of main storage device C...
. . are cyclically operating in synchronization, so only the dimming level signal (first dimming state) corresponding to address signal 1 passes through the third AND circuit 20 and is output to the D-A converter of the output circuit 8. It is converted into an analog quantity and stored.

Next, when the crossfader 15 is operated once again, the D-A
The signal voltage for obtaining the first dimming state stored in the converter is transferred to the analog voltage holding circuit, where it is stored and via the dimming unit 9 controls the illumination lamp a to the first dimming state.

Also, at this time, the second AND circuit 14□ opens, and the output from the shift register d2, that is, the address signal 3 in the above memory contents, passes through the second AND circuit 14□, passes through the OR circuit 19, and then outputs the entire third AND circuit 20. When the signal is opened, only the dimming level signal for obtaining the third dimming state corresponding to the address signal 3 of the main memory device C passes through the third AND circuit 20 and is stored as an analog quantity in the D-A converter of the output circuit 8. be done.

In this way, the crossfader 15 is again used for the second scene and below.
Operate to change the dimming state.

That is, when the output circuit 8 has two stages of storage circuits, the output read from the main storage device C is executed by the lighting lamp a with a delay of -scene by the output of the sub-storage device d.

The above is the basic operation of the preset type load control device previously proposed by the present inventor, but in order to use this type of conventional device, it is necessary to complete the presetting when presetting various dimming level signals in the main memory device C. Before performing confirmation and load control, it is essential to confirm the dimming state set for each scene, that is, to preview it.

The present inventor first developed an indicator by using the unused side of the two memory circuits of the output circuit 8 in the output section of the preset load control device, that is, the memory circuit corresponding to the next scene. We proposed a device that previews by display.

However, in this method, it is previewed.

In such a case, the memory contents of the memory circuit corresponding to the next scene must be erased once, the dimming level signal of the address of the main memory device C for which preview is desired is newly stored, and this memory content converted from D to A is stored. Since the preview is performed using an indicator, after the preview operation is completed, this memory content must be erased and the dimming level signal that was stored before the preview must be stored again, which complicates the operation of the device and may cause malfunctions. becomes more sexual.

Also, when previewing with this method, it is necessary that the memory circuit corresponding to the next scene is not being used for execution, in other words, it is necessary that cross conversion is not in progress.
Therefore, since there is a limit on the time when preview operations can be performed, operations are complicated and prone to malfunctions.

Therefore, the present invention provides a preview device that allows previewing at any time, regardless of the output circuit 8, in order to facilitate operations during load control.

To explain the outline of the present invention, a multiplexer sequentially reads the dimming level signals stored in each shift register of the main memory C by one cycle at a time, starting with the dimming level signal stored at a desired address. ,
A sample consisting of an analog switch and a temporary voltage holding circuit installed for each channel, in which only the dimming level signal stored at the address at the beginning is sequentially D-A converted by a D-A converter for all channels. The signal is distributed to a hold circuit, and the output is used to wave the indicators of each channel for preview.

The present invention will be explained in detail below with reference to the drawings.

What is shown in FIG. 2 is a preview device e, which is an embodiment of the present invention, provided in the preset type load control device (FIG. 1), and is comprised of the following circuit elements.

In FIG. 2, 13' is a contact connected to the scene selection switch 13 and outputs the contents of the sub-storage device d.

104 is an OR circuit; 103 is a counter that counts the address signal that has passed through the OR circuit 104, that is, the address signal corresponding to the dimming level signal desired to be previewed; 102 is a main storage device that receives the binary code of the counter; A coder 101 is a multiplexer driven by the output of the coder 102, which converts the signal into a signal corresponding to the shift register of each channel of the main memory C. The signals are sequentially output starting with the dimming level signal of the address desired for preview.

105 is an AND circuit that sends a dimming level signal for which a preview is desired out of the output signals of the multiplexer 101 to a D-A converter 106, which will be described later; 106 is an output of the AND circuit 105, that is, a dimming level signal for which a preview is desired; A D-A converter 107 for D-A converting the level signal is an analog switch such as a field effect transistor, and is arranged corresponding to each channel.
and distributes the output of the DA converter 106 to each channel.

Reference numeral 108 denotes a voltage holding circuit, which is paired with the aforementioned analog switch 107 to form a sample and hold circuit.

109 is an indicator, and 110 is a preview mode switching relay. Only when this relay is activated, the indicator 109 is connected to the sample and hold circuits 107 and 108 through contacts 110', and a preview is executed.

110' and 110'' are contacts of the preview mode switching relay 110, 111 is a preview mode switching switch, and 12' and 13'' are contacts linked to the address signal selection switch 12 and the scene selection switch 13, respectively.

The other elements have been explained in FIG. 1 and will therefore be omitted.

In this preview device e, when the preview mode changeover switch 111 is turned on and either of the contacts 12' and 13'' are turned on, the preview mode changeover relay 110 is activated, and the contact 110' of the relay 110 is activated.

110'' is inserted into the b side and performs a preview operation.

Next, the case where the above circuit is operated will be explained with reference to the signal voltage waveforms of each part shown in FIG.

Here, as a premise, the main storage device C and the secondary storage device d
It is assumed that presets have already been made in FIG. 1 as described above.

If you want to preview the dimming level signal at an arbitrary address in the main memory device C at this stage, close the preview mode changeover switch 111 and specify an arbitrary address in the main memory device C with the address signal selection switch 12. It works like this.

That is, the preview mode changeover switch 111 is closed and any address signal selection switch, for example 1
When 23 is closed, the contact 12' is linked to the same switch 123.
3 is also closed, so the preview mode switching relay 110 operates, thereby each contact 110', 11
0'' is inserted into the b side.

Then, the indicator 109 indicates that the sample and hold circuit 10
7, 108 to receive the signal to be previewed.

Further, a high level signal is sent to the AND circuit 105 by the one contact 110'', thereby opening the AND circuit.

In this state, the address signal 3 (hereinafter referred to as 4-A) shown in FIG.
The signal is sent to circuit 105.

First, the first address signal 3 (4-A) is sent to the counter 10.
3, the counter 103 counts this, and the decoder 102 receives the signal corresponding to the first channel (4-B
) as multiplexer 101 and analog switch 107
and drive each.

Then, the multiplexer 101 reads the dimming level signal stored in the shift register C1 corresponding to the first channel of the main memory device C by one cycle (4-C) and sends it to the AND circuit 105.

However, it is the OR circuit 10 that opens the AND circuit 105.
This is only when address signal 3 (4-A) is input from D-4, so only the dimming level signal stored at address 3 of shift register C1 of the first channel is input from D-.
The signal is input to the A converter 106, converted into an analog signal (4-D), and sent to the analog switch 107.

However, the only analog switch that is open at this time is 107□, which receives the output (4-B) of the first channel of the encoder 102.

In the end, when the first address signal 3 (4-A) is input manually, only the dimming level signal stored in the address 3 of the shift register C1 of the first channel is D-A.
After being converted into an analog quantity by the converter 106, it passes through an analog switch 107□ and is then connected to a voltage holding circuit 108□.
and the indicator 109□ indicates the voltage holding circuit 1.
08. The output (4-E) is received and displayed.

Then, the second address signal 3 (4-A) is passed through the OR circuit 104 to the counter 103 and the AND circuit 105.
, the path of the second channel is opened and the dimming level signal stored at address 3 of the shift register C2 of the second channel of the main memory C is transferred to the voltage holding circuit 1082 in the same manner as described above. This output (4-F
), the indicator 109□ makes a display.

The following operations are performed in the same manner for all channels, and the main memory C
Each time the D-dimension level signal is stored in address 3 of each channel, D-
It is converted into A.

Note that the voltage holding circuit 108 is configured as shown in FIG. 3, for example, and stores the peak value of the voltage once reached via the analog switch 107 in the capacitor C, and applies a voltage proportional to this voltage to the output terminal (OUT). It's starting to happen.

In this circuit, the electric charge stored in the capacitor C is prevented from flowing backward by the analog switch 107, and since the gate current of the field effect transistor (FET) is very small, the multiplexer 101 scans all channels and returns to
A constant voltage can be output to the indicator 109 until it is input from the -A converter 106.

In the above explanation, the preview was performed by turning on the address signal selection switch 12 and specifying the address of the main storage device C, but the scene selection switch 13 can be used to preview the control state corresponding to each scene of the secondary storage device d. It is also possible to do so.

In this case, when any switch of the scene selection switch 13 is turned on, the contacts 13' and 13'' linked thereto are closed, activating the preview mode switching relay 110, and switching on the memory corresponding to the arbitrary scene in the sub-storage device d. An address signal is sent from the element to the counter 103 and the AND circuit 105 via the contact 13' and the OR circuit 104, and the dimming level signal of the desired scene can be previewed in the same manner as described above.

Note that unless the preview mode changeover switch 111 is turned on, the contacts 110' and 110'' of the preview mode changeover relay 110 are turned on to the a side, and the indicator 109 is connected to the output side of the output circuit 8.
The control status being executed is displayed on an indicator 109.

As explained above, in the above embodiment, the main memory device stores and holds the dimming level signal, and the sub-memory device stores and holds the address signal of the main memory device. In a preset type load control device that controls a load by reading out a dimming level signal stored in a storage device, it has been possible to provide a preview device that can preview regardless of the load control execution state. As in the case of using a conventional preview device that uses one of the two memory circuits in the output circuit that is not in use, it is possible to erase the memory of the memory circuit, preset and erase the control signal of the load of the desired preview address, and restore the original The complicated operation of re-presetting the control signal is no longer necessary, and malfunctions caused by this are eliminated.Furthermore, even during execution of cross conversion, the desired address in the main memory or the desired scene in the sub-memory can be addressed. It becomes possible to preview the control signal, there is no restriction on when the preview can be performed, and the preview operation becomes easier, which is of great practical value.

Note that the above embodiment is a preset type automatic adjustment having a main memory device C for storing dimming level signals and a sub-memory device d for storing addresses of the main memory device C corresponding to dimming level signals to be executed for each scene. Although the optical device has been described, the present invention is not limited to this in any way. For example, the present invention may include only a storage device corresponding to the main storage device C, and sequentially read the dimming level signals stored in this storage device. It can also be implemented in a preset type light control device that adjusts the light by adjusting the light.

As explained above, the present invention provides a preview device that does not use an output circuit in a preset type load control device that controls a load by reading a load control signal stored in a storage device. Erase the memory of the memory circuit, such as when using a conventional preview device that uses one of the memory circuits that is not in use.
Preview The complicated operations of presetting and erasing the load control signal of the desired address and presetting the original control signal again are no longer necessary, and the erroneous operations caused by this are eliminated.Furthermore, previewing is possible even while cross conversion is being performed. This makes preview operations easier and has great practical value.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a preset type load control device that is the premise of the present invention, Figure 2 is a schematic diagram of the configuration of an embodiment of the present invention, and Figure 3 is a voltage holding circuit used in the embodiment of Figure 2. FIG. 4 is a circuit diagram of an example of the configuration of FIG. 2, and is a signal voltage waveform diagram of each part for explaining the operation of the circuit of FIG. a...Load (lighting light), b...Controller (preset fader), C...Storage device (main memory), d...Sub. Storage device, e...
- Preview device, 12'...Contact linked to address signal selection switch 12, 13'. 13''...Contacts linked to scene selection switch 13, 101...Multiplexer, 102...
...Decoder, 103...Counter, 10
4...OR circuit, 105...AND circuit, 106...D-A converter, 107...
... Analog switch, 108 ... Voltage holding circuit, 109 ... Indicator, 110 ...
...Preview mode switching relay 110', 11
0''...Contact of preview mode switching relay, 111...Preview mode switching switch.

Claims (1)

[Scope of utility model registration request] It is equipped with a plurality of loads, a plurality of controllers, and a storage device consisting of a plurality of storage elements that store control states of the loads set by the controller, and reads out control signals stored in the storage device to control the load. The preset type load control device to be controlled is provided with a D-A converter that sequentially converts the readout output of the storage device into an analog quantity, a sample hold circuit and an indicator corresponding to each storage element of the storage device, and a preview mode changeover switch. and at least by operating an address signal selection switch, the control state of the load stored at a specific address in the designated storage device can be previewed with an indicator via the D-A converter and sample hold circuit. A preview device for a preset type load control device, which is characterized by: