JPS5833640B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory control method for initializing a memory;
For example, if a data processing system that has a memory system that includes error correction code generation circuitry and error detection and correction circuitry is turned on, the error detection and correction circuitry is disabled following an initial reset at system power-on. The present invention relates to a memory control method characterized by reading the contents of a memory device, applying an error correction code to the data bits, and initializing the data bits.

Normally, data pits, Kld parity check bits, error correction codes, etc. stored in memory are added to improve the reliability of the system.

By the way, in a system in which non-volatile memory such as core memory and volatile memory such as dynamic semiconductor memory without battery support coexist, when the system is powered on, the data bits and error correction codes of the non-volatile memory are In fact, the volatile memory data bit buttons and error correction codes are mostly correct.

Therefore, if a program on non-volatile memory is started following a power-on reset and accesses an area of volatile memory, almost all the data read from volatile memory will be subjected to error checking. It's refreshing.

Regardless of the data in this volatile memory, if the error correction code pits are correct, the read data will not pass error checking.

In the memory device to which the present invention is applied, one word consists of a plurality of bytes, and address access is performed in word units or bait units.

The check bits generated at this time are generated in units of words.

Therefore, if the access unit is a word address, one check bit is generated and added to the data to be written in response to a write command, and the data is stored in a storage area at a predetermined word address.

On the other hand, when the access unit is a byte address, the write command reads the word address that includes the specified byte address, updates the contents of the specified byte address with the data to be written, and writes the specified byte. This configuration stores data in which check bits are generated and added for words containing words as words and addresses.

If the access is to a byte address, the read will precede as described above, so if the check bit in the address is incorrect, error checking will occur.

The present invention is based on the above considerations, and provides a memory control method that prevents a contradiction between data bits and check bits in the memory when a data processing device starts operating. It is an object.

Therefore, the Memo IJ I+1 method of the present invention includes a memory device that adds check bits to data for error detection or error correction and stores the data in a storage location, and a check bit generator that generates check bits for write data. and error checking/correcting means for checking/correcting errors in data read from the memory by referring to the check bits, the error checking/correcting means is disabled. An error check/correction invalidation means and a memory initialization means for initializing the writing memory device are provided, and the memory initialization means (a) performs the error check/correction invalidation means at the time of starting operation of the data processing device. (0) In a state where the error checking and correction means is disabled, the storage area at 1 from a pre-specified address to another pre-specified address is controlled. ←) The data stored in the storage area is sequentially read out, the check bits generated by the check bit generation means are added to the data, and the data is written to the original storage location. After the processing of ridge 0 is completed, the error check/correction invalidation means is controlled to enable the error check/correction means.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram for explaining the outline of one embodiment of the present invention, FIG. 2 is a flowchart showing the procedure for initializing the memory, and FIG. 3 is a diagram showing the error correction code generation mechanism and error detection and correction mechanism. FIG.

In FIG. 1, 1 is a central processing unit, 2 is an adapter, and 3 is a central processing unit.
is a floppy disk device, 4 is a memory control unit, 5 is a memory device, 6 is a read-only memory, 7 is an error correction code generation circuit, 8 is an error detection/correction circuit, 9 is a register for controlling the error detection/correction circuit, Ro and R1 indicate registers, respectively.

A program is stored on the floppy disk of the floppy disk device, and this program is transferred to the memory device 5 by the loader.

The memory control section 4 is provided with an error correction code generator 7 button and an error detection/correction circuit 8.

The memory device 5 includes nonvolatile memory and volatile memory, and addresses 0 to 999 are register areas.

Programs and data are stored in the 1000th address i to FFFFth address of the memory device 5.

Each address of the memory device 5 stores 2 bytes of data and a 6-bit error correction code.

However, the memory 5 can also be accessed in byte units.

To rewrite only one byte of data, proceed as follows.

For example, assuming that data A1, data DBb, and error correction code E1 are stored at address ADi, and when rewriting data DB to data DC, data DA,
The data DB and error correction code E□ are stored in the memory device 5.
, and stores it in a register (not shown) in the memory control unit 4, rewrites the data DB to DC, generates an error correction code "E2" for all data DA and DC,
Data D 1 Data D.

and error correction code E2 are stored in the original storage location specified by address ADi.

When the i button reads the data DA, DB and the error correction code El from the memory device, the error detection/correction circuit 8 operates.

The read-only memory 6 stores a program routine for initializing the memory and an initial program load routine (tPL routine).

These program routines are executed when the data processing device starts operating.

The error correction code generator 7, when writing is performed,
It generates an error correction code for write data.

When writing 2-byte data to the i button, an error correction code for these 2-byte data is immediately created, but when writing 1-byte data, the operation described above is performed.

The error detection/correction circuit 8 performs error checking when reading is performed, and performs error correction if a 1-bit error occurs.

The error detection/correction circuit control register 9 controls whether the error detection/correction circuit 8 is enabled or disabled.

Register 9 is address 20 in this example, and when logic "O" is set in its seventh pit position, error detection and correction circuit 8 is disabled and does not operate, and the data read from memory device 5 is disabled. is considered to be normal i.

When logic "1" is set in the seventh bit position, the error detection/correction circuit 8 is enabled and operates normally.

FIG. 2 shows a flowchart of the memory initialization program stored in the read-only memory 6.

This program routine is executed, for example, when a start key on the console is pressed.

When the execution of this memory initialization program routine starts, an error is detected at address 20 on the memory device 5.
A logic “0” is placed in the seventh bit position of the correction circuit control register 9.
'' is set, and the error detection/correction circuit 8 is disabled.

After this invalidation is performed, the 1000th address is set in register R6.

As mentioned earlier, in this example, addresses O through 9
Address 99 is a register area, and addresses 1000 to FFFF are storage areas for programs and data.

After the 1000th address is set in register R6, the first
As soon as the data bit at address 000 undergoes an error check, it is read out and set in register R1.

The data bits in register R1 are then transferred to register R6.
(initially, address 1 ooo).

At this time, an error correction code for the input data is generated by the error correction code generator 7, and the error correction code is added to the input data and written at the original address.

After the above processing is performed, the contents of register R6 (1000 at this time) are incremented by 1 and set in register R6 again.

After register R6 is updated, it is checked whether the contents of register R8 are (FFFF+1).

If NO, the same processing operation is repeated: 3YES-'
m, after setting the logical month in the 7th bit position of the error detection/correction circuit control register 9 at the 20th address and enabling the error detection/correction circuit 8, the initial program and load routine are executed. The program and data in the floppy disk of the floppy disk device 3 are stored at a predetermined address in the memory 5.

For memory initialization operations, read/write operations are 2
This is done in byte units (1 word units).

FIG. 3 shows parts related to error detection and correction, in which 8a is an error detection circuit, 8b is an error correction mechanism, and 10
fi to 13 is an AND circuit, 14 is a NOT circuit, S is syndrome information, A is a multi-bit error signal, and B is a 1-bit error signal.

In the case of a write, address information is first provided, followed by input data.

If the input data is 2 bytes, an error correction code for the 2 bytes of data is immediately created, and the data bits and error correction code are written to the address specified by the address information.

In the case of writing 1-byte data, all data bits and error correction code are read from the address specified by the address information and set in a register in the error correction code generator γ.

Then, replace some of the data, bits with input data,
An error correction code is generated for the replaced 2-byte data, and these data, bit information, and error correction code are stored again in the original location.

When logic "1" is set in the seventh bit position of the error detection/correction circuit control register 9, reading is performed as follows.

When a logic “1” is set in the above bit position, the AN
When the D circuit 10.11 is opened, address information is supplied, and a read signal (not shown) is applied, the data and error correction code are read out and supplied to the error detection circuit 8a.

The error detection circuit 8a performs error detection and notifies the central processing unit of the error when a 1-bit error or multiple-bit error occurs.

If 1-bit error signal B is generated, AND
Circuit 12 is opened, AND circuit 14 is closed, and the data is input to correction mechanism 8b.

The correction mechanism 8b corrects errors based on the syndrome information S and outputs corrected data.

If 1-bit error signal B is not output, AN
The D circuit 13 is opened and the data read from the memory device 5 is output.

The data or correction data read from the memory 5 is
It is once set in a latch circuit (not shown) and then transferred to the central processing unit or channel.

The central processing unit or channel can read data in 1-byte or 2-byte units, but in either case, the memory controller ignores the least significant bit of the addressing (word addressing) and reads the 2-byte data. Just transfer it.

Also, if the central processing unit or channel requires 1 byte of data, and the lowest bit of address information specifies the high-order data, specify only the high-order data and the low-order data. If so, you only need to import the data on the lower level.

i) Access to the memory device 5 is performed while ignoring the least significant bit.

When logic "O" is set in the seventh bit position of the error detection/correction circuit control register 9, the AND circuit 1
0.11 closes.

Therefore, the central processing unit is always notified that the error check is OK, and at the same time, the AND circuit 12 is closed and the AND circuit 13 is opened, and the data read from the memory device 5 is forwarded to the requester.

As is clear from the above description, according to the present invention, regardless of the boundary position between nonvolatile memory and volatile memory, the data in the area of nonvolatile memory is 1\, and the data in the area of volatile memory is All correct checks and bits are generated and added.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an overview of an embodiment of the present invention, FIG. 2 is a flowchart showing a procedure for controlling memory initialization, and FIG. 3 is an error correction code generation mechanism and an error detection/correction mechanism. FIG. DESCRIPTION OF SYMBOLS 1... Central processing unit, 2... Adapter, 3... Floppy disk device, 4... Memory control unit, 5...
...Memory device, 6...Read-only memory, 7...
Error correction code generation circuit, 8...Error detection/correction circuit, 9...Error detection/correction circuit control register, R
o and R1...Register, 8a...Error detection circuit, 8b...Error correction mechanism, 10 to 13...A
ND circuit, 14...NOT circuit.

Claims (1)

[Scope of Claims] 1. A memory device that adds check bits to data for detecting or correcting errors in the data and stores the added data in a storage location; a check bit generating means that generates check bits for write data; A data processing device comprising an error check/correction means for checking/correcting errors in data read from the memory by referring to bits,
An error check/correction invalidation means for invalidating the error check/correction means and a memory initialization means for initializing the memory device are provided, and the memory initialization means (a) operates the data processing device At the time of starting, the error check/correction invalidation means is controlled to invalidate the error check/correction means (with the zero error check being invalidated), the error check/correction invalidation means is controlled and the error check/correction means is invalidated. Sequentially read the data stored in the storage area 1 up to the address, add the check bit generated by the check bit generation means to the data, write it to the original storage location, and store it in the above storage area. After the processing in (b) above is completed for all the data being processed, the error check is performed.Control is performed to enable the error check/correction means by controlling the correction invalidation means. memory control method.