JPS5833636B2 - Storage device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a memory device, and particularly to a semiconductor memory device.

When writing information to the memory element of a semiconductor memory device,
A typical type is one in which a negative or positive write high voltage signal is applied to the storage element via a write circuit.

The configuration of such a semiconductor memory device is as shown in the block diagram shown in FIG. 1, for example.

In FIG. 1, 1 is an X address input circuit, 2 is an X decoder, 3 is a Y address input circuit, 4 is a Y decoder, 5 is a write circuit, 6 is a bus line connecting the Y decoder 4 and the write circuit 5, Reference numeral 7 designates a memory circuit consisting of memory elements arranged in a matrix, 8 a bus line connecting the write circuit 5 and the memory circuit 7, and 9 a data input/output circuit.

When writing data to a storage device configured as described above, in response to signals from address input circuits 1 and 3, decoders 2 and 4 write data into a large number of storage elements arranged in a matrix of storage circuit 7. A specific storage element is selected from.

When writing data to the selected specific memory element, a negative or positive high voltage signal is applied from outside the memory device to the specific memory element in the memory circuit 7 via the write circuit 5.

For example, when the memory element of the memory circuit 7 is composed of an element with a FAMO3 structure, information is stored by applying a negative high voltage to its source and accumulating electrons generated by avalanche in the floating gate.

As described above, during a write operation, it is necessary to apply a high voltage write signal to the memory element in the memory circuit 7 via the write circuit 5, so that the logic circuit constituting the write circuit 5 has a complementary insulated gate field effect. Transistor (
(hereinafter referred to as "CMO8) transistor"), the above high voltage write signal causes CMO8)
Conventionally, logic circuits made of CMO transistors could not be used in such circuits because of the risk of transistor failure.

This invention solves the above problems and allows CMO8)
It is an object of the present invention to provide a memory device in which a write circuit made up of a logic circuit made of transistors is not destroyed by a write voltage.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a write circuit section of a semiconductor memory device according to an embodiment of the present invention.

In FIG. 2, 10 is a P-channel MO8) transistor, 11 is an N-channel MO8) transistor, and 12 is a P-channel MO8) transistor.
Channel MO8) transistor, 13 is N channel M
O8) is a transistor.

Here, transistors 10, 11 and 12, 13 constitute inverters 14 and 15 of CMO8 structure, respectively.

16 is a write control circuit, 17 is a write control circuit 16
P-channel MO3) transistor, controlled by
18 is a P-channel MO8) transistor that controls the write signal; 19 is a capacitor connected between the gate and source of the transistor 18; 20 is the output terminal of the inverter 15; 21 is a switching circuit consisting of the transistor 18; 22
is the output terminal of the switching circuit 21, 23 is the connection point between the output terminal 20 of the inverter 15 and the output terminal 22 of the switching circuit 21,
24 is the output terminal 20 of the inverter 15 and the transistor 1
Diode inserted in the connection path with 3, VDD and V
SS is a constant potential point.

In this embodiment, VDD is positive, VSS is grounded or negative potential, and a negative high voltage is used as the write signal.

Next, the operation of the circuit diagram of the embodiment shown in FIG. 2 will be explained.

First, as explained in FIG. 1, when the path line 6 selected by the Y decoder 4 is set to a low level in response to a signal from the Y address input circuit 3, the transistor 10 becomes conductive, so that the output of the inverter 14 is turned on.・Becomes level.

As a result, the transistor 12 is turned off and the transistor 13 is turned on, so that the output of the inverter 15 becomes low level.

On the other hand, since the transistor 17 is rendered conductive by the write control circuit 16, the gate potential of the transistor 18 becomes low level.

Here, when a negative write voltage having a potential lower than VSS is applied to the source of the transistor 18, the diode 24 is of reverse biased polarity, so the negative write voltage is not applied to the transistor 13.

That is, since the transistor 13 is protected by the diode 24, it will not be destroyed by a negative write voltage.

Note that the write voltage is supplied from the connection point 23 to the memory circuit via the pass line 8.

Next, when the write voltage applied to the source of the transistor 18 is at a high level, the polarity is such that the diode 24 is forward biased, so the potential of the connection point 23, which is the output point of the write circuit, becomes the potential of VSS. .

Next, during reading, the pass line 6 selected by the Y decoder 4 is at a low level, as in the case of writing described above.

However, since the transistor 17 is turned off by the signal from the write control circuit 16, the transistor 1B is turned off.

At this time, the transistor 13 of the inverter 15 is in a conductive state, but the diode 24 operates in the forward direction, so
The potential of the connection point 23 becomes the vSS potential, and the insertion of the diode 24 does not cause any inconvenience.

Note that in the above description, a case has been described in which the diode 24 is inserted between the output terminal 20 of the inverter 15 and the transistor 13, but the diode may be inserted between the transistor 13 and the constant potential point VSSO. .

That is, it is clear that inserting the diode 24 in the connection path from the output terminal 20 of the inverter 15 to the constant potential point vSS via the transistor 13 can produce the same effect as described above.

Furthermore, the same method can be implemented even when the write voltage is a positive high voltage.

That is, the conductivity type of each transistor may be reversed to that described above, the potential polarity may be reversed, and the polarity of the diode may be reversed.

As described above, according to the present invention, a diode is inserted in series with one of the transistors constituting an inverter stage made of CMOS transistors which is in a conductive state at the time of writing, and a diode is inserted in series with the transistor in which the write voltage is in the conductive state. Since the write voltage is prevented from being applied to the transistor, it is possible to obtain a memory device in which the write circuit constituted by the logic circuit consisting of the CMO transistor is not tested by the write voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a semiconductor memory device, and FIG. 2 is a circuit diagram showing a write circuit section of the semiconductor memory device according to an embodiment of the present invention. In the figure, 12 is the other transistor, 13 is one transistor, 15 is an inverter stage, 20 is an output terminal of the inverter stage, and 21 is an opening/closing circuit. 22 is an output terminal of the switching circuit, 23 is a connection point, 24 is a diode, SS is a first constant potential point, and VDD is a second constant potential point. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Comprised of complementary insulated gate field effect transistors,
One main terminal of one of the transistors is connected to a first constant potential point, one main terminal of the other transistor is connected to a second constant potential point, and the other main terminals of each of the two transistors are connected to each other. It is configured to connect and derive an output terminal from there, and includes an inverter stage that responds in response to an address signal, and an opening/closing circuit that responds to the address signal and controls the transmission of a write signal. The one transistor of the inverter stage is made conductive and the switching circuit is closed, and the output terminal of the inverter stage and the output terminal of the switching circuit are connected, and the write signal is transmitted from this connection point to the next stage. In a storage device having a write circuit configured to supply
A storage device characterized in that a diode is inserted in a connection path from the output terminal of the inverter stage to the first constant potential point via the one transistor with a polarity such that the write signal is applied in the opposite direction.