JPS583317A - Envelope tracking type slice level generating circuit - Google Patents
Envelope tracking type slice level generating circuitInfo
- Publication number
- JPS583317A JPS583317A JP10081881A JP10081881A JPS583317A JP S583317 A JPS583317 A JP S583317A JP 10081881 A JP10081881 A JP 10081881A JP 10081881 A JP10081881 A JP 10081881A JP S583317 A JPS583317 A JP S583317A
- Authority
- JP
- Japan
- Prior art keywords
- slice level
- input terminal
- voltage
- voltage comparator
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、エンベロープ追従型スライスレベル発生回路
、特に磁気記録装置の読出し回路に使用されるスライス
レベル発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope-following slice level generation circuit, and particularly to a slice level generation circuit used in a read circuit of a magnetic recording device.
磁気記録装置の読出し信号のレベル検出用のスライスレ
ベルを発生する回路において、従来は第1図に示すよう
に、ダイオードlと、これと直列に接続された抵抗器2
と、2の他層と接地間に、並列に接続さに苑コンデンサ
3と抵抗器4で構成した。Conventionally, in a circuit that generates a slice level for detecting the level of a read signal of a magnetic recording device, as shown in FIG.
It consists of a capacitor 3 and a resistor 4 connected in parallel between the other layer of 2 and the ground.
ダイオードlのアノード端子に読出し信号を印加し、そ
のピーク電圧を抵抗器2とコツプ/す3で決定する時定
数でコンデンサ3に充電し、放電はコンデンサ3と抵抗
器4で決定する時定数で行ない、コンデンサの端子電圧
をエンベロープに追従したスライスレベルとしていた。A readout signal is applied to the anode terminal of diode l, and the peak voltage is charged to capacitor 3 with a time constant determined by resistor 2 and resistor 3, and discharge is performed with a time constant determined by capacitor 3 and resistor 4. The capacitor terminal voltage was set to a slice level that followed the envelope.
以上の回路では、ダイオード1の順方向電圧降下による
レベルの損失の問題や、読出し信号をこの回路に印加す
る場合に、信号源の結合条件が直流結合で、しかも低イ
ンピーダンスでなければならない等の使用上の困難があ
った。In the above circuit, there are problems such as level loss due to forward voltage drop of diode 1, and when applying a read signal to this circuit, the coupling condition of the signal source must be DC coupling and low impedance. There were some difficulties in using it.
本発明の目的は、続出し信号のピーク電圧と、そのエン
ベロープに追従したスライスレベル電圧との誤差を少な
くシ、また入力インピーダンスの高い回路を提供するこ
とである。SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that reduces the error between the peak voltage of a continuous signal and a slice level voltage that follows its envelope and has a high input impedance.
本発明によれば、差動入力の電圧比較器を用い、その正
側入力端子に読出し信号を印加し、電圧比較器の出力を
ダイオードと充電用抵抗器を通して前記の電圧比較器の
負側入力端子に印加し、更に負側入力端子と接地間にコ
ンデンサと放電用抵抗器を接続し、前記負側入力端子よ
り工7ベロープに追従したスライスレベル発生回路が得
られる。According to the present invention, a differential input voltage comparator is used, a read signal is applied to its positive input terminal, and the output of the voltage comparator is passed through a diode and a charging resistor to the negative input terminal of the voltage comparator. A slice level generation circuit that follows the curve from the negative input terminal is obtained by connecting a capacitor and a discharge resistor between the negative input terminal and ground.
本発明は電圧比較器を用い、その出力f:積分して発生
するスライスレベルと読出し信号のピーク電圧とt比較
し、その誤差を帰還することによシスライスレベル會補
正し、誤差が少なく、かつ入力インピーダンスの高くし
たものである。The present invention uses a voltage comparator, and compares the output f: the slice level generated by integration with the peak voltage of the readout signal, and corrects the slice level by feeding back the error, resulting in less error. It also has high input impedance.
次に本発明の実施例を図面を参照しながら説明する。Next, embodiments of the present invention will be described with reference to the drawings.
第2図を参照すると、本発明の実施例は、読出し信号の
レベル検出したパルス列を発生する回路であ)、電圧比
較器5と、5の正側出力端子にアノード側で接続された
ダイオード6と、6のカソード側と、5の負側出力端子
間にIjI!続された抵抗器7と、5の負側入力端子と
接地間に接続されたコンデンサ8と可変抵抗器9と、9
の摺動端子と負側入力端子で接続された電圧比較器10
.11と、10.11の負側出力端子と接続されたNA
ND回路12とを含む。Referring to FIG. 2, the embodiment of the present invention is a circuit for generating a pulse train by detecting the level of a read signal), which includes a voltage comparator 5 and a diode 6 connected to the positive output terminal of 5 on the anode side. and IjI! between the cathode side of 6 and the negative side output terminal of 5. a capacitor 8 and a variable resistor 9 connected between the negative input terminal of 5 and the ground;
Voltage comparator 10 connected by the sliding terminal and negative input terminal of
.. 11 and the NA connected to the negative output terminal of 10.11.
ND circuit 12 is included.
al、a2は磁気記録装置の読出し信号であり、差動の
信号である。al and a2 are read signals of the magnetic recording device and are differential signals.
alは電圧比較器5.10の正側入力端子に印加され、
a2は11の正側入力端子に印加される。al is applied to the positive input terminal of voltage comparator 5.10,
a2 is applied to the positive input terminal of 11.
第3図はalの波形を示す。a2は前記したようにal
の逆極性の波形である。al、a2は振動変動している
。FIG. 3 shows the waveform of al. a2 is al as mentioned above
This is a waveform with the opposite polarity. al and a2 are subject to vibrational fluctuations.
5の電圧比較器は、alの信号とCの電圧とを比較し、
alがCを越えた時間だけ、第3図で示すパルスbt−
出力する。Voltage comparator 5 compares the signal of al and the voltage of C,
For the time when al exceeds C, the pulse bt- shown in FIG.
Output.
コンデンサ8はbのパルスによ)抵抗器7の抵抗値で定
まる時定数で充電される。bのパルスがない区間では、
コンデンサ8に充電された電荷は抵抗器9全通して放電
される。以上のような充放電の繰9返しにより発生する
のがCの電圧であシ、入力の読出し信号a1の工/ペロ
ープに追従した波形となる。The capacitor 8 is charged by the pulse b) with a time constant determined by the resistance value of the resistor 7. In the section where there is no pulse b,
The charge stored in the capacitor 8 is discharged through the resistor 9. The voltage C is generated by the nine repetitions of charging and discharging as described above, and has a waveform that follows the curve of the input read signal a1.
電圧比較器10.11扛al、a2のレベル検出に使用
する。Voltage comparators 10 and 11 are used to detect the levels of al and a2.
Cの波形は!1の1001のレベルに追従したスライス
レベルなので、レベルの検出マージンを上げるため可変
抵抗器9によシ分圧し、dの信号音発生して10.11
の負側入力端子に印加する。What is the waveform of C? Since it is a slice level that follows the level of 1001 of 1, in order to increase the level detection margin, the voltage is divided by variable resistor 9, and the signal tone of d is generated.
applied to the negative input terminal of
e、fはそれぞれal、a2がdの電圧を越えた時間を
パルス幅とする負のパルス列となシ、12ONAND回
路によシ論理和され正のパルス列となる。e and f are negative pulse trains whose pulse width is the time when al and a2 exceed the voltage of d, respectively, and are ORed by the 12ONAND circuit to become a positive pulse train.
このようにして、読出し信号のピーク電圧に対して誤差
の少ないスライスレベル電圧が生成でき、安定したレベ
ル検出が可能で、かつ読出し信号を、印加される回路が
通常、入力インピーダンスが高い電圧比較器であるため
、駆動するのが容易であるという効果がある。In this way, a slice level voltage with little error can be generated with respect to the peak voltage of the readout signal, stable level detection is possible, and the circuit to which the readout signal is applied is usually a voltage comparator with high input impedance. Therefore, it has the effect of being easy to drive.
本発明は、以上説明したように、電圧比較器を用い、入
力の読出し信号のピーク電圧と、その電圧比較器の出力
からつくるスライスレベルとを比較することによシ誤差
が少なく、かつ入力インピーダンスが高くする効果があ
る。As explained above, the present invention uses a voltage comparator to compare the peak voltage of an input read signal and the slice level created from the output of the voltage comparator, thereby reducing errors and reducing input impedance. It has the effect of increasing the
第1図線従来のスライスレベル発生回路を示した回路図
、第2図は本発明の実施例を示した回路図、第3図拡N
2図の一部の波形を示したタイムチャートである。
1・・・・・・ダイオード、2・・・・・・抵抗器、3
・・・・・・コンデ/す、4・・・・・・抵抗器、5・
・・・・・電圧比較器、6・・・・・・ダイオード、7
・・・・・・抵抗器、8・・・・・・コンデ/す、9・
・・・・・可変抵抗器、10.11・・・・・・電圧比
較器、12・・・・−NAND回扇Figure 1 is a circuit diagram showing a conventional slice level generation circuit, Figure 2 is a circuit diagram showing an embodiment of the present invention, Figure 3 is an enlarged diagram.
2 is a time chart showing some waveforms in FIG. 2; 1...Diode, 2...Resistor, 3
......conde/su, 4...resistor, 5.
...Voltage comparator, 6...Diode, 7
...Resistor, 8...Condition/su, 9.
...Variable resistor, 10.11...Voltage comparator, 12...-NAND fan
Claims (1)
た出力信号’ktBす電圧比較器を有し、その電圧比較
器の出力端子をダイオードと第1の抵抗器を直列に通し
て、前記電圧比較器の第2の入力端子にl!絖し、第2
の入力端子よシ接地間にコンデyすと第2の抵抗器を並
列にN!!続し、前記電圧比較器の1lG1の入力端子
に信号を印加し、第2の入力端子よ多出力するエンベロ
ープ追従型スライスレベル発生器。It has a voltage comparator that outputs a signal 'ktB corresponding to the magnitude of the voltage applied to the first and second input terminals, and the output terminal of the voltage comparator is passed through a diode and the first resistor in series. , l! to the second input terminal of the voltage comparator. Knitting, 2nd
Connect a second resistor in parallel with a capacitor between the input terminal and ground of N! ! Next, an envelope following type slice level generator which applies a signal to the 11G1 input terminal of the voltage comparator and outputs multiple signals from the second input terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10081881A JPS583317A (en) | 1981-06-29 | 1981-06-29 | Envelope tracking type slice level generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10081881A JPS583317A (en) | 1981-06-29 | 1981-06-29 | Envelope tracking type slice level generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS583317A true JPS583317A (en) | 1983-01-10 |
Family
ID=14283920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10081881A Pending JPS583317A (en) | 1981-06-29 | 1981-06-29 | Envelope tracking type slice level generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS583317A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5315711A (en) * | 1976-07-28 | 1978-02-14 | Ricoh Co Ltd | Picture signal processing circuit |
-
1981
- 1981-06-29 JP JP10081881A patent/JPS583317A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5315711A (en) * | 1976-07-28 | 1978-02-14 | Ricoh Co Ltd | Picture signal processing circuit |
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