JPS5832500B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that enables high density and miniaturized structure.

In recent years, efforts have been made to increase the density and integration of semiconductor devices, especially semiconductor integrated circuits, and for this reason, efforts are being made to miniaturize these devices.

For example, the diode array attached to the heat generating head of a facsimile machine is composed of a group of diodes lined up horizontally at a constant pitch. This is a factor that determines the resolution, and a smaller pitch is required.

Figure 1 shows an example of a diode 1/i that has been used in the past.

That is, it is formed using a well-known semiconductor integrated circuit device manufacturing technique, for example, a high concentration N-type buried layer 2 is selectively formed in a predetermined region of a type silicon substrate 1. Afterwards, an N-type epitaxial layer 3 is formed to form a P 2 isolation diffusion region 4 to electrically isolate the individual diodes, and then a P-type region 5 and an N-type region 6 are selectively formed. The electrodes of the diode were taken out by metal vapor-deposited wirings 7 and 8 made of aluminum or the like.

9 indicates a surface insulating film.

The distance l between the dashed lines shown in the figure indicates the pitch interval of the aforementioned diode group. For example, if the resolution of the print head is 6 per month, the pitch of this diode is approximately 150 microns or less. Must.

If this is made 8 per 1 mm, the pitch of the diodes will be required to be approximately 100 microns.

The diode is composed of a PN junction formed at the interface between the P-type region 5 and the N-type epitaxial layer 3.
Since it is difficult to take out the electrode directly from the N-type epitaxial layer 3, the N region 6 is necessary, and in order to further reduce the series resistance and prevent the parasitic P N l) N operation, the N region 6 is necessary.
The P region 5 is surrounded by a region 6 and a buried layer 2.

Therefore, in order to secure the required current capacity of the diode, it is not possible to reduce the P region 5, and the only option is to reduce the surrounding N+ regions 6, 2, the isolation region 4, or the spacing between them. It is not possible to reduce the pitch interval.

However, as these regions were reduced, the parasitic effects could no longer be ignored, leading to miniaturization.

The conventional diode array shown in FIG. 1 also has the following drawbacks.

First, an extra area is required because there is an additional N+ area around the actual PN junction surface.

As is well known, after the formation of the buried layer, lifting of the buried layer occurs during the epitaxial growth and separation/diffusion steps, and variations in process conditions often cause the buried layer 2 and P region 5 to come into contact with or come close to each other, lowering the withstand voltage. thing.

The process is complicated, including N+ implantation, epitaxial growth, isolation diffusion, P region diffusion, N diffusion, and electrode wiring, and requires five photomasks, leading to an increase in cost.

The above has been explained using a diode array built into a facsimile machine as an example, but as is well known, this is a generalized technology for ordinary bipolar integrated circuit devices, and the above drawbacks are common to conventional bipolar integrated circuits. I can say that.

The present invention is a method for manufacturing a semiconductor device with a novel structure that improves the drawbacks faced by conventional semiconductor device manufacturing methods. It is an object of the present invention to provide a method for manufacturing a semiconductor device that makes it possible to

Still another object of the present invention is to provide a novel method for manufacturing a semiconductor device, which reduces the number of steps, improves yield, and reduces cost, while preventing parasitic effects in the semiconductor device.

Isolation methods using insulators have already been proposed as a means of preventing parasitic effects and achieving miniaturization.

However, many of the methods that have been proposed involve complicated processes and have not yet been put into practical use.

Recently, a technology has been announced for separating insulators by selectively making a silicon crystal porous and then oxidizing it.

For example, as introduced in the July 29, 1970 issue of Nikkei Electronics, page 28, after forming a P separated diffusion region, the P separated diffusion region is made porous by anodization, and then thermally oxidized. This forms a thick oxide region.

However, according to the inventors' experiments, the hole concentration within the silicon crystal contributes to the reaction in anodizing to create porosity.
The density and pore diameter of the porosity depend on the impurity concentration in the region. For example, when making the P-type separation and diffusion region described above porous, the porosity density and pore diameter will vary from the substrate surface toward the interior of the substrate according to the diffusion profile of the P-type impurity. changes.

Therefore, when performing thermal oxidation, the oxidation is not homogeneous, resulting in unevenness on the surface and unoxidized portions remaining, resulting in reliability problems.

The present invention is based on a method of making a separation region porous and oxidizing it, but instead of a conventional diffusion separation region, a region with a uniform impurity concentration distribution and a relatively low concentration is made porous. It is characterized by points.

The basic structure of the present invention is to form an epitaxially grown layer containing a low concentration impurity of the same conductivity type on one surface of a substrate of one conductivity type, and selectively form a predetermined region of the growth layer into a porous layer until it reaches the substrate. The semiconductor device is constructed by a method of manufacturing a semiconductor device including a portion in which an insulating region is formed by oxidizing the material after it has been made into a material.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

FIGS. 2A and 2-E show one embodiment of the present invention, and explain the manufacturing process when applied to the facsimile diode array shown in the conventional example.

First, a substrate 101 made of a P-type silicon single crystal with a specific resistance of 1 Ω-α is prepared as a starting material, and an N-type buried region 102 is formed in a predetermined region of the substrate 101 by a well-known selective diffusion method (FIG. A). .

Next, a P-type epitaxial growth layer 103 is formed on the surface where the buried region 102 is formed, and N diffusion region 1 reaches the buried region 102 from the surface of the grown layer 103 by a selective diffusion method.
04 (Figure B).

The impurity concentration of the epitaxial growth layer 103 is determined by the required breakdown voltage of the diode, but it is set at 2×1017 crIL-
Never go above 11.

For example, if 40V is required as the diode breakdown voltage, 4×10 16 crrL-3 is selected.

In this case, the growth thickness of the growth layer is preferably 3 μm.

Next, a selective mask 105 for selective porous treatment is formed on the surface of the growth layer 103 to selectively form porous regions 106.
is formed to a depth that penetrates into the substrate 101 (C in the same figure).
.

As the selection mask 105, depending on the method of porosity treatment, the resist organic material film may be used as is, but generally a silicon nitride CVD film is used.

In that case, a silicon nitride film of about 2000 λ is once deposited on the entire -1 surface using the CVD method, and then holes are formed in predetermined areas using phosphoric acid by photoetching.

The porous treatment is performed on the hydrofluoric acid-resistant resin container 1 as shown in Figure 3.
A silicon wafer 12 is supported by a holder 11 of 0.0, a hydrofluoric acid solution 13 is filled in a container, platinum electrodes 14 and 15 are immersed in the solution, and a power source 16 is used to power the electrodes 14.
A predetermined voltage is applied between 15 and 15.

The polarity of voltage application is such that the surface 1γ of the silicon wafer 12 is the second polarity.
A selective mask 1 is placed on the surface of the epitaxial growth layer 103 shown in the figure.
05, the electrode 14 becomes an anode and applies a positive voltage.

In this case, the back surface 18 of the wafer 12 is connected to the silicon substrate 101.
It may be used as is, but as the starting material substrate 101 in FIG.
By using the substrate 201 on which 02 is formed, the controllability of the porous treatment becomes better.

In addition to the porous treatment method shown in FIG.
Although the method described on page 28 of the July 29, 1999 issue may be used, the method shown in FIG. 3 has the advantage of protecting the silicon crystal from contamination because the electrodes are not directly taken out from the silicon wafer.

In order to form the porous region 106 to a depth of about 4μ in FIG. Then, the selective mask 105 is dissolved and removed using a hydrofluoric acid solution.

Next, by heating and oxidizing in an oxidizing atmosphere, a thermal oxide film 107 is formed on the surface of the epitaxially grown layer 103, and at the same time, the porous region 106 is also oxidized and transformed into a thick oxide region 108 (FIG. D).

The conditions for thermal oxidation are determined by balancing the shrinkage due to re-densification of the porous region by heat treatment and the expansion due to oxidation, and therefore vary depending on the impurity concentration of the substrate and epitaxial layer and the porous formation conditions, but the above-mentioned The following values were selected for the conditions: wet oxidation at 800° C. for 15 minutes, followed by wet oxidation at 1050° C. for 30 minutes.

Finally, by forming the electrode 109 from the N region 104 and the electrode 110 of the P region 103, which is separated into each diode from the (■) type epitaxial layer, in the same manner as in the conventional method, a diode array wafer is completed. (Figure E)
.

In this case, since the depletion layer of the PN junction surface 111 extends into the epitaxial layer, it is less susceptible to the effect of auto-doping of the buried layer than the conventional structure shown in FIG.
It can be seen that this is extremely advantageous for increasing density because the ratio of the junction area to the diode area can be increased.

That is, when comparing FIG. 1 of the conventional example and FIG. 2 E of the present invention, the diode in FIG. N+ region 6 is now required.

- In Fig. 2 E of the old manuscript, the diode is the interface 111 where the N type conductive region composed of the N diffusion region 104 and the buried region 102 and the P type conductive region 103 contact each other. If they are made the same, it is clear which one will be miniaturized.

Furthermore, in FIG. 1, there are epitaxial layers 3 and P between the islands.
In contrast to the presence of the type separation diffusion region 4, FIG.
In this case, only the oxide region 108 exists, and it is clear that the latter is extremely advantageous for increasing the concentration.

For these reasons, in this embodiment, the pitch of the diodes can be sufficiently increased from 100 microns to 50 microns while maintaining the same characteristics as the conventional example.

When the specific resistance value of the substrate 101 is increased, the oxide region 10
In some cases, an N-type conversion layer or channel is formed at the bottom of 8 to increase leakage current.

In order to prevent this, after forming the buried layer 102 shown in FIG. 2A, a high concentration P+ selective diffusion region 112 as shown in FIG. Just follow the process.

That is, a channel stopper 113 is formed at the bottom of the thick oxide region 108 as shown in FIG. 5H.

Furthermore, as described above, the method for forming the porous region 106 shown in FIG.
In addition to using a photoresist commonly known as a mask, such as Kodak's KMER, there are also cases in which the selection mask 105 is not used, and the P-vacancy region becomes more porous than the N-type region. It is also possible to directly create competitive porosity by taking advantage of its fast properties.

In this case, a P-type region also exists inside the island region surrounded by the N+ regions 104 and 102, but in the anodization reaction, this region becomes a floating potential region surrounded by the N+ region. Another feature is that it has a structure that remains almost non-porous because there is no current path.

In this case, the number of steps is N embedding, evixaxial growth, N
+ Diffusion, porous treatment, electrode wiring, and four photomasks are all that is required, and it can be seen that the number of steps is reduced compared to the case explained in the conventional example.

FIG. 6 shows a cross-sectional structural diagram when the present invention is applied.

The process is similar to the embodiment shown in FIGS. 2A to 2E and X', in which an N buried diffusion region 202 is formed in the P type silicon substrate 201 in FIG. do.

Next, the N 2 diffusion region 204 is selectively diffused deep until it contacts the buried region 202, and the interior surrounded by the N 2 regions 202 and 204 becomes an island region.

Such a separation method is already known as CDI (Collector Diffusion Isolation) (Co11ecto
This is known as the diffusion 1solation) method, but in the present invention, in the subsequent step, the surface is selectively masked with a nitride film, the spaces between each island are made porous, and this is thermally oxidized to form a thick oxide region 205. It is formed.

Furthermore, since this porous treatment is performed on an epitaxially grown layer having a uniform, relatively low concentration of P-type impurities, an extremely uniform and stable porous region is formed.

In FIG. 6, a description of the integrated circuit components formed in the island region surrounded by N regions 202 and 204 will be omitted as they are already well known. The aluminum electrode 208 is formed by diffusion.

As explained above, according to the present invention, the island region of the element is of the same conductivity type as the semiconductor substrate, and its periphery is surrounded by an insulator rather than a PN junction, which not only reduces capacitance but also reduces capacitance. Since the parasitic element effect, which becomes a problem when increasing the density, can be prevented in the lateral direction, the packaging density can be significantly increased.

Although the embodiments of the present invention have been described above in the case where they are applied to diode arrays and bipolar integrated circuit devices, the present invention is not limited to the above embodiments. This can be applied to any semiconductor device including an island region constituted by a buried layer of the opposite conductivity type and a region of the same conductivity type as the buried layer that penetrates the eviaxial layer and reaches the buried layer. Not even.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structure diagram of a conventional diode array, Fig. 2 A-E is a process sectional view of an embodiment of the present invention, Fig. 3 is a configuration diagram of a porous treatment device, and Fig. 4 is a porous structure diagram. 5A and 5B are views showing the channel stopper directly under the thick insulator region of the present invention. FIG. FIG. 101...P-type semiconductor substrate, 102...
・N type buried region, 103...P type epitaxial growth layer, 104...N diffusion region, 105
... Selection mask, 106 ... Porous region, 107 ... Thermal oxide film, 108 ...
Oxide region, 109, 110... Electrode.

Claims (1)

[Claims] 1. A step of forming a buried layer region of the other conductivity type opposite to the semiconductor substrate on a semiconductor substrate-L of one conductivity type, and a step of forming an epitaxial growth layer of one conductivity type on the surface of the semiconductor substrate. , forming an impurity region of the other conductivity type from the surface of the epitaxial growth layer to the buried layer region, and making the epitaxial growth layer on the buried layer region a semiconductor island region of the one conductivity type; A method for manufacturing a semiconductor device, comprising the steps of: making a region in direct contact with the semiconductor substrate porous; and making the porous portion an insulator.