JPS583196A - Memory system for image processing - Google Patents

Abstract

PURPOSE:To make the error correction effcient, by producing an ECC code stored in an ECC memory from specified image sub-arrangement not duplicated with equal intervals. CONSTITUTION:A data is read out from a memory 7 in the mode of (1Xpq) of lateral one row with equal intervals, for example, and this is written in a memory area 9 with one longitudinal column mode, (pqX1) by rotating the data by 90 deg. via an intermediate buffer 8. On the other hand, the data is read out in a rectangular (pXq) mode from a memory 7', turned by 90 deg. via an intermediate buffer 8' and written in a memory area 9'. In this case, in adding the ECC to the data of memory, the ECC is generated by splitting the memory area with the correspondence to the access type as one lateral row of (1Xpq) mode, one longitudinal column of (pqX1) mode, or a rectangular pXq mode. Since it is possible to take the intermediate buffers 8 and 8' as required larger, the buffers can be designated as the 2nd specified address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement on the invention disclosed in Japanese Patent Publication No. 54-39098, and is a method for adding an error correction code (ECC) function to a memory system including a function suitable for image processing. It is related to.

As an example, let us consider a case in which data collected using the Rusk Scan method is rotated 90'' counterclockwise and output again in the order of the Rusk Scan method.

As shown in Figure 1, in the rusk scan method, data is collected in the direction of increasing j on the image array, and j = j
After max, data is collected in the order of i+i +1 and j×O. Therefore, in actual memory, writing/reading must be performed in IXpq mode.

In the case where there is no error correction code ECC, as shown in FIG. This can be done very easily by using the method of writing a predetermined number of times in the mode. However, if ECC is added to this, the data read in IXpq mode will be changed to -! It is not possible to write in one time in mapq This is an unavoidable problem with parity checks and ECCK, which detect and correct errors in word units.

A possible method to avoid this problem is to triplex the entire memory, write the same data, and select the correct data by majority vote when read. This would solve the above-mentioned contradiction, but on the other hand, the memory cost would be relatively high.

The method shown in FIG. 3 takes this point into account, and attempts to triplex only a small portion to avoid an increase in memory cost, and corrects the rest of the data using ECC. In the figure, 2 is a memory for image processing, 3 is a memory area where the first data is stored, 4, 4',
4" is the triplexed memory area, 5 is the final storage memory area, ECC
is for data in area 3.

First, from a predetermined address in the first memory area 3, IX
The data read out a predetermined number of times in pq mode is once written to the triplexed memory areas 4.4', 4' in pq×1 mode. Next, this data is read out by majority vote in Y I

3- In this case, it takes twice as much effort as compared to the method described with reference to FIG. 2 or the full-scale triplexing method, but it can be processed much faster than the method of processing one bit at a time described above. Note that if it is possible to set the second predetermined address in the triplexed memory area, double effort can be avoided, but in this case, a sufficient memory area is required, and in some cases is not much different from a full-scale triplex system.

The present invention solves various drawbacks of such conventional methods, enables memory operations that always apply the ECC function to various access modes for image manipulation, and reduces the amount of memory required. It also provides a memory system with a relatively small capacity. The present invention also provides an efficient addressing method for ECC memory.

Therefore, the present invention has the configuration t shown below.

P + q + R and 5ya - B4 as a design parameter
- image point I(i,j) with unity value, where O≦i(
R, pXs-q consisting of R, p and 0≦j<8-q)
An image array can be stored, and I Xp q! of said image array can be stored. Alternatively, a word-organized random access memory system in which 29 image points in any subarray of p , for a storage means and image point I(i+j) consisting of 29 storage modules that can be stored in different storage locations, and in each storage module only one storage location can be accessed at a time. M(i,
A memory system having an access means for reading from and writing to storage location A('1j) of a j)-th storage module and writing to the storage location A(J+j), comprising: an ECC memory; A memory for image processing characterized in that the BCC code stored in the memory for image processing is generated from 10,000 non-overlapping image sub-arrays of IXpq or I)Xq or both, divided at equal intervals. system.

The present invention will be explained in detail below with reference to the drawings.

FIG. 4 to FIG. 7 are diagrams of embodiments for explaining the present invention in detail, respectively.

The method shown in FIG. 4 is a method that achieves the same effect as the method shown in FIG. 3, but is devised to avoid the triple memory method, which is a burden on hardware. In the figure, 6.6' is the image processing memory, 7.7' is the memory area where the first data is stored, 8.8' is the intermediate buffer area, and 9.9' is the final data storage memory area. . FIG. 4(a) also shows data YIXpq from memory area 7.
mode and sends it through intermediate buffer 8 to 90
4(b) shows data 'vp xq' from memory area 7'.
mode, and transfers it to 9 through intermediate buffer 8'.
A case is shown in which the data is rotated by 0° and written into the memory area 9'.

In the case of the system shown in FIG. 4, a BCC is added to data in each memory area. Here, the memory is divided into areas and EC (J) is generated in correspondence with the IXpq mode, pqX1 mode, or pxq mode and the access type.

The area may be fixed to a physical address using hardware, or may be freely specified for each fixed size using software. In this case, there is no problem even if the pot modes are mixed. In addition, the intermediate buffers 8 and 8' in FIG. 4, which correspond to the triplexed memory area in FIG. You may.

In this way, it is a very effective method to change the method of generating ECC codes depending on the area, but another problem is how to specify the address of the FCC (6 to 7 bits are used). If addressing in IXpq mode and addressing in other pqXl or pxq modes are determined independently, a case may occur where the addresses match even though the areas are different.

The most straightforward way of addressing is shown in Figure 5 (a).
s (b), (C) K.

Figure 5(a) 7- is an example in which IXpq mode (t=0) access is possible, Figure 5(b) is an example in which pxq mode (t=1) access is possible, and Figure 5(C) is an example in which access is possible in pxq mode (t=1). ) is IXI) q mode and pxq
Mixed accessible areas with modes (t=0/l=1
) t and examples are shown respectively.

These figures all show the case where S≧87·s=p r and p==q=4, r=2, and S=8.

In the case of FIG. 5C, when t=i, ECCyal' is valid only when i%&p=2 is specified. Expressing this as a t expression, if the ECC address is Agcc (i, j, t), then AJcc (i, j, s = Tx (txr + jlp
q)+t×((i/p)×S+j〆q). The symbol "/" represents the quotient with the remainder rounded down,
The symbol "7./, J" represents the remainder.The logical address (■, ■, ■) obtained by calculating this formula.

) matches the physical address both when t=Q and when t=1.

However, in the case of mixed mode as shown in Figure 5(C),
- If you think about it, confusion arises because the physical address is the same for 1=0 and t=1. In other words, after writing image data to address ■ in t=0 mode, if you access ■ in t=1 mode, the BCC bit will contain exactly ■.
An error occurs because it contains a code that matches the address data.

In order to avoid such a situation, it is sufficient to set a limit Y on how to take the 1=0 area and the t=1 area. That is, t=1
If we restrict the mode to be divided at the region YiIp=O, the same AICC(i, j +
t) may occur, and conflicts can be avoided.

Figure 6 (at + (b) r (c) is an example of another addressing method without the above constraints. In an image processing memory system, handling 5pQ
Addressing for each bit θ~(pq-1) of image points i, j
It is considered that if the bits of is applied to the ECC address. In other words, the property described in the patent application filed concurrently with the present application) Ak=A(i+t+9uv/'Q * j+tX7uv
+tX? vIQ)K, = 0 (therefore u=v=0)84
Substitute 1' and consider the ECC boundary condition.■. =0 (
'f, LT(v+v(1)=O) and the formula %() ((() is used for addressing.

In this case, even in the mixed mode shown in FIG. 6(C), the ECC address conflict as described above does not occur.

In the case of FIG. 6(C), when t=1, ECC is valid only when i, &p=2 is specified.

FIG. 7 (a) * (bl t (c) K What is shown is yet another example of addressing. This time, the above-mentioned formula K
k = 0 ((u = v = O) or = 15 (
u=v=3) Y is assigned to C0 to C3 of the address 9ECC bits obtained by the former method, and C4 to C6 of the address 9ECC bits obtained by the latter method. The address calculation formula is as follows.

x, o(i, j, t) = [i+tx(p-(riff 1)+i,/'q), llp)・EQ((i%,/p
+j/q Vlp +O)ko×rj/pq Als(i, j+D= [i+tx(p-1-(iIp
+j//q), fp)] xr+j, //pq In the case of FIG. 7(C), ECC is valid only when t=1 and ladder p=2 is specified.

In such a correspondence, for example, as shown in the shaded area in (b), physical addresses are not aligned with respect to the same logical address (although, for example, the output of address Ao is
Compared to supplying all of the C bits C0 to C6, the load can be distributed more easily, which is advantageous from a hardware perspective.

11- By performing K in this manner, any m (m is the number of ECC bits) that allows duplication from k=0 to (pq-1) can be selected and used as the ECC bit address.

In this method, there is no need to particularly calculate the ECC address, and in terms of hardware, only a set timing for writing the F3CC code and a timing for checking it are required. Incidentally, in the method shown in Figure 5, when 1=00 and when t=1
An OR circuit for the case is required.

Although the present invention has been described above in accordance with a few embodiments, many modifications can be made based on the idea of the present invention.

[Brief explanation of the drawing]

Figure 1 shows a raster scan of an image, Figure 2 shows a 90° rotation of image data in image memory, and Figure 3 shows how a triple buffer is used to transfer an image. Explanatory diagram of the method for performing rotation operation, 4th
Figures (a) and (bl generate ECCY in the memory storage of different sub-array modes, respectively, and transfer the image through there and perform rotation operation. b) I (C) is a diagram showing an example of the ECC addressing method for each area with different sub-array modes, Figures 6 (a), (b), (C
) is a diagram showing another EICC addressing method similar to FIG. 5, and FIG. 7(a) I (b) l (C) is a diagram showing another ECC addressing method similar to FIG. 5. In the figure, 6 and 6' are memory for image processing, 7 and 7' are the first data storage memory area, 8 and 8' are intermediate buffer areas,
9 and 9' represent final data storage memories. Applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi t=o (
IXP 1 iodine "l'S Figure t=l(F)7-donj=Q/l, = + LA1 692-t-0(l to F)E-Fnt6m t-1( r〆)E-1") EeChi-,) t=o/l=mouth＾５693-2;+, &Ctbi,,,to(1) t-0(l X nE-do)i'+7
Open. )t-1(P*%t-k,)t-o7't-+
mixed 694

Claims (1)

[Claims] It is possible to store an Rp A word-organized random access memory system in which 99 image points in an image array IXpq or any subarray of pxq can be read or written in a single memory cycle, each with R8 or more image points. The image point I(i
tj), the storage location A(' l j) of the M(i. j)th storage module
access means for reading from and writing to the storage location A(itj); and! A memory system having an ECC memory is provided, and the ECC code stored in the ECC memory is divided into equally spaced I
A memory system for image processing, characterized in that it is generated from non-overlapping image subarrays of one or both of XPQ or pxq.