JPS583196A - Memory system for image processing - Google Patents

Memory system for image processing

Info

Publication number
JPS583196A
JPS583196A JP56101497A JP10149781A JPS583196A JP S583196 A JPS583196 A JP S583196A JP 56101497 A JP56101497 A JP 56101497A JP 10149781 A JP10149781 A JP 10149781A JP S583196 A JPS583196 A JP S583196A
Authority
JP
Japan
Prior art keywords
memory
mode
data
ecc
memory area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56101497A
Other languages
Japanese (ja)
Inventor
Takeshi Murata
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56101497A priority Critical patent/JPS583196A/en
Publication of JPS583196A publication Critical patent/JPS583196A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Abstract

PURPOSE:To make the error correction effcient, by producing an ECC code stored in an ECC memory from specified image sub-arrangement not duplicated with equal intervals. CONSTITUTION:A data is read out from a memory 7 in the mode of (1Xpq) of lateral one row with equal intervals, for example, and this is written in a memory area 9 with one longitudinal column mode, (pqX1) by rotating the data by 90 deg. via an intermediate buffer 8. On the other hand, the data is read out in a rectangular (pXq) mode from a memory 7', turned by 90 deg. via an intermediate buffer 8' and written in a memory area 9'. In this case, in adding the ECC to the data of memory, the ECC is generated by splitting the memory area with the correspondence to the access type as one lateral row of (1Xpq) mode, one longitudinal column of (pqX1) mode, or a rectangular pXq mode. Since it is possible to take the intermediate buffers 8 and 8' as required larger, the buffers can be designated as the 2nd specified address.
JP56101497A 1981-06-30 1981-06-30 Memory system for image processing Pending JPS583196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56101497A JPS583196A (en) 1981-06-30 1981-06-30 Memory system for image processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101497A JPS583196A (en) 1981-06-30 1981-06-30 Memory system for image processing

Publications (1)

Publication Number Publication Date
JPS583196A true JPS583196A (en) 1983-01-08

Family

ID=14302273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56101497A Pending JPS583196A (en) 1981-06-30 1981-06-30 Memory system for image processing

Country Status (1)

Country Link
JP (1) JPS583196A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131289A (en) * 1985-12-03 1987-06-13 Nec Corp Memory circuit for graphic display unit
EP0582824A2 (en) * 1992-07-31 1994-02-16 E.I. Du Pont De Nemours And Company Orthogonal image rotation using matrix transposition

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131289A (en) * 1985-12-03 1987-06-13 Nec Corp Memory circuit for graphic display unit
EP0582824A2 (en) * 1992-07-31 1994-02-16 E.I. Du Pont De Nemours And Company Orthogonal image rotation using matrix transposition
EP0582824A3 (en) * 1992-07-31 1994-05-04 Du Pont

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