JPS5831140B2 - signal receiver - Google Patents

signal receiver

Info

Publication number
JPS5831140B2
JPS5831140B2 JP53137892A JP13789278A JPS5831140B2 JP S5831140 B2 JPS5831140 B2 JP S5831140B2 JP 53137892 A JP53137892 A JP 53137892A JP 13789278 A JP13789278 A JP 13789278A JP S5831140 B2 JPS5831140 B2 JP S5831140B2
Authority
JP
Japan
Prior art keywords
level
circuit
maximum value
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53137892A
Other languages
Japanese (ja)
Other versions
JPS5564464A (en
Inventor
康二郎 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP53137892A priority Critical patent/JPS5831140B2/en
Publication of JPS5564464A publication Critical patent/JPS5564464A/en
Publication of JPS5831140B2 publication Critical patent/JPS5831140B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/46Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies comprising means for distinguishing between a signalling current of predetermined frequency and a complex current containing that frequency, e.g. speech current

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 本発明は押ボタン信号等を受信する信号受信器に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal receiver that receives push button signals and the like.

押ボタン信号により加入者端末から中央のデータ受信装
置にデータを送信するいわゆるEND−TO−END方
式で信号が送信される場合、中継段階での4線ループに
よりエコーの発生する場合がある(参考文献IEEE
TRANSACTIONSON COMMUNICAT
ION TECHNOLOGYVOL、 C0M−15
、NO,6、DEC67’ P P812〜824)
When signals are transmitted using the so-called END-TO-END method in which data is transmitted from subscriber terminals to a central data receiving device using pushbutton signals, echoes may occur due to the 4-wire loop at the relay stage (Reference Literature IEEE
TRANSACTIONS COMMUNICAT
ION TECHNOLOGYVOL, C0M-15
, NO, 6, DEC67' P P812-824)
.

このため、これらデータを受信する多周波信号受信器に
はエコーによる影響を受けないための保護手段が必要と
なる。
Therefore, a multi-frequency signal receiver that receives these data requires protection means to prevent it from being affected by echoes.

従来、この保護手段として、(1)AGC回路(上記文
献)(2)パッド制御回路←特公昭49−15643号
公報他)が知られているが、(1)はAGC回路が比較
的複雑である。
Conventionally, as this protection means, (1) AGC circuit (the above-mentioned document) and (2) pad control circuit (Japanese Patent Publication No. 49-15643, etc.) have been known, but in (1), the AGC circuit is relatively complicated. be.

(2)はパッド制御用としてリレー回路及び外部からの
リセット信号等が必要である。
(2) requires a relay circuit and an external reset signal for pad control.

等の欠点を有していた。It had the following drawbacks.

本発明の目的は、前記した従来技術の欠点をなくシ、よ
り簡単な回路で同等の機能を達成する信号受信器を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal receiver that eliminates the drawbacks of the prior art described above and achieves the same function with a simpler circuit.

本発明は、前記したエコー保護の手段を、入力された信
号の最大値を検出する最大値検出回路と、ソノ出力レベ
ルに応じてリミッタ回路の検出レベルを可変する可変閾
値回路とを設けることで実現するものである○ 以下本発明の詳細な具体的実施例に従って説明する。
The present invention provides the echo protection means by providing a maximum value detection circuit that detects the maximum value of the input signal and a variable threshold circuit that varies the detection level of the limiter circuit according to the sono output level. The present invention will be described below in accordance with detailed specific embodiments.

第1図はAGC回路を使用した従来例である。FIG. 1 shows a conventional example using an AGC circuit.

入力端子INに入力された多周波信号はAGC回路1に
より一定レベル化された後、分波F波器2により高群、
低群にl波づつ分離される。
The multi-frequency signal input to the input terminal IN is made into a constant level by the AGC circuit 1, and then divided into high groups,
Each wave is separated into low groups.

しかる後、リミッタ回路3′及び3“に入力され、予め
設定されたレベル以上のもののみ矩形の出力としてチャ
ンネルフィルタ4に入り、レベル検出回路5により検出
すべき周波数であるか否か判定され、引き続く出力回路
6にて出力すべきか否か等がチェックされ出力0UT1
〜8の該当端子に出力を生じさせる。
Thereafter, it is input to the limiter circuits 3' and 3'', and only those above a preset level enter the channel filter 4 as a rectangular output, and it is determined by the level detection circuit 5 whether or not the frequency is to be detected. The subsequent output circuit 6 checks whether to output or not, and outputs 0UT1.
An output is generated at the corresponding terminal of ~8.

ここでAGC回路1は先に受信器に到達する優勢なレベ
ルにより作動し、引き続き到来するエコー成分(これは
先に到達するレベルより必ず低く通常は14〜L5dB
以上低いレベルである)はAGC回路の立下り応動時間
をエコー成分の到来する時間(通常は最大40 m s
以下といわれている)の開作動し続けるように設定する
ことにより抑圧し、受偏レベル以下とすることにより、
エコーによる影響を防止している。
Here, the AGC circuit 1 is activated by the dominant level that reaches the receiver first, and the echo component that arrives subsequently (which is always lower than the level that arrives first, typically 14 to L5 dB).
The falling response time of the AGC circuit is the time at which the echo component arrives (usually at a maximum of 40 ms).
By setting the opening operation of
Prevents the influence of echoes.

しかし、一般にAGC回路の構成は複雑であり、かつ高
価となる欠点を有している。
However, the structure of an AGC circuit is generally complicated and expensive.

また1図示はしていないが、もう一方の方法である“パ
ッド制御回路“を使用する場合は、パッドの挿脱をする
ためのリレー及びパッド制御をするための回路及び挿入
されたパッドをはずすためのリセット信号等を必要とす
るため、構成が複雑かつ大形となり、信頼性上も問題な
しとはいえない欠点がある。
1.Although not shown, when using the other method, a "pad control circuit," the relay for inserting and removing the pads, the circuit for controlling the pads, and the inserted pads must be removed. Since a reset signal and the like are required for this purpose, the configuration is complicated and large, and there are drawbacks in terms of reliability.

これらの欠点を解消したのが第2図に示す本発明による
方法である。
The method according to the present invention shown in FIG. 2 overcomes these drawbacks.

第2図において、入力された多周波信号は分波、沢波器
2により高群、低群の各1波)こ分離された後、リミッ
タ回路3′、3“に印加されるが、この時同時に最大値
検出回路7′、7“にも印加される。
In Fig. 2, the input multi-frequency signal is separated into one high group wave and one low group wave by a wave splitter 2, and then applied to limiter circuits 3' and 3''. At the same time, the voltage is also applied to the maximum value detection circuits 7' and 7''.

ここで検出された入力信号の1構成分の最大値は弓き続
く可変閾値回路8′、8“に入力され、受信すべき最低
レベル(固定閾値)VF(第4図参照)と比較され、ま
ずは検出すべきレベルか否かがチェックされた後、検出
すべきレベルであれば、先に検出した最大値よりも必要
なだけ減衰された(通常2〜3dBでよい7)閾値をリ
ミッタ3′、3“の検出レベル発生端子9(第4図参照
)に印加し、検出すべきレベルでなければ固定閾値VF
を印加する。
The maximum value of one component of the input signal detected here is then input to the variable threshold circuits 8', 8'', where it is compared with the lowest level (fixed threshold) VF (see FIG. 4) to be received; First, it is checked whether the level is to be detected or not, and if the level is to be detected, the threshold value is attenuated by the necessary amount (usually 2 to 3 dB is sufficient7) than the previously detected maximum value, and then the limiter 3' , 3" to the detection level generation terminal 9 (see Fig. 4), and if it is not at the level to be detected, the fixed threshold value VF is applied.
Apply.

一方、リミッタ回路3′、3“の他の一端は分波ろ波器
2からの入力信号の1波が到来しているので、リミッタ
回路3′、3“で両端子に印加されているレベルが比較
され、検出レベル発生端子に印加されているレベルを越
えている時のみ、リミッタ回路より矩形を出力し、以降
第1図に説明したのと同様の手順にて信号が処理される
On the other hand, since one wave of the input signal from the splitter filter 2 has arrived at the other end of the limiter circuits 3', 3'', the level applied to both terminals of the limiter circuits 3', 3'' is is compared, and only when it exceeds the level applied to the detection level generation terminal, a rectangle is output from the limiter circuit, and thereafter the signal is processed in the same procedure as explained in FIG.

ここで、エコー成分が到来した場合は、最大値検出回路
1′、7“の放電時定数を適切に(AGC回路と同様に
40m5程度)設定することにより、エコー成分でのリ
ミッタ回路3′、3“の作動を阻止することができる。
Here, when an echo component arrives, by appropriately setting the discharge time constant of the maximum value detection circuits 1' and 7" (about 40m5 like the AGC circuit), the limiter circuit 3', 3" operation can be prevented.

以上述べた最大値検出回路7′、7“、可変閾値回路8
′、8“の具体的実施例を各々第3図、第4図に示す。
The maximum value detection circuits 7', 7'' and the variable threshold circuit 8 described above
3' and 8'' are shown in FIGS. 3 and 4, respectively.

まず第3図に示す最大値検出回路では、人力された信号
の最大値はコンデンサC1に充電され、記憶される。
First, in the maximum value detection circuit shown in FIG. 3, the maximum value of the manually input signal is charged and stored in the capacitor C1.

またこの最大値は時定数C1・(R1+ R2)により
決まる時間だけエコー成分によるレベルより高いレベル
に保持される。
Further, this maximum value is maintained at a level higher than the level due to the echo component for a time determined by the time constant C1·(R1+R2).

また同時に、R2/(R1+R2)で決まる比率だけ最
大値は減衰され、引き続く可変閾値回路8′、8“に印
加される。
At the same time, the maximum value is attenuated by a ratio determined by R2/(R1+R2) and applied to the subsequent variable threshold circuits 8', 8''.

一方、第4図に示される可変閾値回路は、オペアンプI
C2、ダイオードD2により構成される比較回路により
、前記最大値検出回路よりの出力レベルPHINと固定
閾値VFと比較し優勢なレベルを検出レベル発生端子9
に出力する。
On the other hand, the variable threshold circuit shown in FIG.
C2 and a diode D2, the output level PHIN from the maximum value detection circuit is compared with the fixed threshold value VF, and the dominant level is detected at the level generation terminal 9.
Output to.

この端子9のレベルとIN’より印加される分波ろ波器
2より分離された1構成分と比較し、リミッタ回路3は
端子9を越えるレベルのみ矩形として出力する。
The level of this terminal 9 is compared with one component applied from IN' separated by the splitter filter 2, and the limiter circuit 3 outputs only the level exceeding the terminal 9 as a rectangular signal.

以上述べた中で、最大値検出回路、可変閾値回路を高群
、低群の各出力に設ける代りに共通に各回路を1個づつ
設けること及び分波p波器を必要としない単周波受信器
に対しても適用することが可能であるのはいうまでもな
い。
Among the above, instead of providing a maximum value detection circuit and a variable threshold circuit for each output of the high group and low group, it is possible to provide one circuit for each in common, and to receive single-frequency reception that does not require a p/p divider. Needless to say, the method can also be applied to vessels.

以上述べたように、本発明による信号受信器は簡単な回
路構成で、かつ経済的にエコーによる影響を受けない保
護手段を実現することができる。
As described above, the signal receiver according to the present invention has a simple circuit configuration and can economically realize a protection means that is not affected by echoes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来技術の1例を示すブロック図、第2図は本
発明による信号受信器の1実施例を示すブロック図、第
3図、第4図は本発明を実現するための回路構成例で、
第3図は最大値検出回路、第4図は可変閾値回路とリミ
ッタ回路を示す回路図である。 2・・・・・・分波p波器、3′、3“・・・・・・リ
ミッタ回路、4・・・・・・チャンネルフィルタ、5・
・・・・・レベル検出回路、6・・・・・・出力回路、
7′、7“・・・・・・最大値検出回路、8′、8“・
・・・・・可変閾値回路、9・・・・・・検出レベル発
生端子、10・・・・・・固定閾値電源、IC3+2,
3・・・・・・オペアンプ。
FIG. 1 is a block diagram showing one example of the prior art, FIG. 2 is a block diagram showing one embodiment of a signal receiver according to the present invention, and FIGS. 3 and 4 are circuit configurations for realizing the present invention. For example,
FIG. 3 is a circuit diagram showing a maximum value detection circuit, and FIG. 4 is a circuit diagram showing a variable threshold circuit and a limiter circuit. 2...P-wavelength divider, 3', 3"...Limiter circuit, 4...Channel filter, 5.
...Level detection circuit, 6...Output circuit,
7', 7"...Maximum value detection circuit, 8', 8"...
...Variable threshold circuit, 9...Detection level generation terminal, 10...Fixed threshold power supply, IC3+2,
3...Op amp.

Claims (1)

【特許請求の範囲】[Claims] 1 人力された信号の信号レベルに応じ作動するリミッ
タ回路と、該リミッタ回路の出力を所定の周波数帯域に
通過させる帯域通過ろ波器と、所定以上のレベルがその
出力に得られた場合作動するレベル検出回路より構成さ
れる信号受信器において、前記入力信号の最大値を検出
し、その検出値に応じた出力レベルを所定時間保持する
最大値検出回路と、その出力レベルと予じめ設定された
固定閾値とを比較し優勢なレベルを前記リミッタ回路の
検出レベルとする可変閾値回路とを設けたことを特徴と
する信号受信器。
1. A limiter circuit that operates according to the signal level of a human input signal, a bandpass filter that passes the output of the limiter circuit in a predetermined frequency band, and a bandpass filter that operates when the output level exceeds a predetermined level. A signal receiver composed of a level detection circuit includes a maximum value detection circuit that detects the maximum value of the input signal and holds an output level corresponding to the detected value for a predetermined period of time, and A signal receiver comprising: a variable threshold circuit that compares the threshold value with a fixed threshold value and sets the dominant level as the detection level of the limiter circuit.
JP53137892A 1978-11-10 1978-11-10 signal receiver Expired JPS5831140B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53137892A JPS5831140B2 (en) 1978-11-10 1978-11-10 signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53137892A JPS5831140B2 (en) 1978-11-10 1978-11-10 signal receiver

Publications (2)

Publication Number Publication Date
JPS5564464A JPS5564464A (en) 1980-05-15
JPS5831140B2 true JPS5831140B2 (en) 1983-07-04

Family

ID=15209108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53137892A Expired JPS5831140B2 (en) 1978-11-10 1978-11-10 signal receiver

Country Status (1)

Country Link
JP (1) JPS5831140B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160937U (en) * 1985-03-26 1986-10-06
JPH0428768Y2 (en) * 1985-03-26 1992-07-13

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171994A (en) * 1989-11-30 1991-07-25 Hitachi Ltd Push-button dial signal receiving system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52107708A (en) * 1976-03-03 1977-09-09 Northern Telecom Ltd Method and device for translating multiple frequency signal
JPS5471512A (en) * 1977-11-17 1979-06-08 Nec Corp Receiver for multi-frequency signal

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52107708A (en) * 1976-03-03 1977-09-09 Northern Telecom Ltd Method and device for translating multiple frequency signal
JPS5471512A (en) * 1977-11-17 1979-06-08 Nec Corp Receiver for multi-frequency signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61160937U (en) * 1985-03-26 1986-10-06
JPH0428768Y2 (en) * 1985-03-26 1992-07-13

Also Published As

Publication number Publication date
JPS5564464A (en) 1980-05-15

Similar Documents

Publication Publication Date Title
US3942116A (en) Transceiver having improved voice actuated carrier and echo suppression circuit
CA2108829C (en) Power control circuit for a digital radio telephone
US4385208A (en) Multifrequency receiver
JPS6139731A (en) Noise detector
JPS5831140B2 (en) signal receiver
US4189679A (en) Noise detecting circuit having noise-immune AGC
JP3203414B2 (en) Receiver with interference wave prevention
US4145580A (en) Multi-frequency signal receiver
US3836727A (en) Signal receiver for receiving signals of different frequency
JP2655437B2 (en) Packet receiver
JP2859024B2 (en) DTMF receiver with malfunction prevention circuit
Chow Impulse noise reduction circuit for communication receivers
KR820001027B1 (en) Remote control system
JPH0140534B2 (en)
JPS55151851A (en) Signal blocking device
JPS5944837B2 (en) signal receiver
JPH02302129A (en) Video receiver
JPS5795791A (en) Multi-frequency signal detector
JPS61118050A (en) Data receiver
JPS6115665Y2 (en)
JPS59104836A (en) Agc system by pilot signal
JPH0226133A (en) Receiving wave interference detector
JPS61244152A (en) Multifrequency signal receiver
JPS6048624A (en) Squelch control circuit
JPS5535513A (en) Automatic gain control circuit