JPS5830679B2 - bistable circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a double-sided circuit such as a memory cell, and particularly to a memory cell constructed of an insulated gate field effect transistor.

a first field effect transistor whose gate is connected to the drain of the second field effect transistor and whose source is grounded; and a second field effect transistor whose gate is connected to the drain of the first field effect transistor and whose source is grounded. a field effect transistor, the drains of the first and second field effect transistors are respectively connected to a DC power supply via a load resistor, and a signal is transmitted to the drains of the first and second field effect transistors. In a memory cell equipped with supply means, a single DC power supply is commonly used and connected to each of the load resistors.

Conventionally, inspection of good and defective memory cells, that is, inspection of destruction of the field effect transistor used as the load resistor, has been carried out by writing a report in the memory cell and reading it.

However, in the case of high-speed inspection, the field effect transistor serving as the load resistor may be destroyed due to stray capacitance caused by transistor junction capacitance, wiring capacitance, etc., and the written information may be lost. As a result, it accumulates in the capacitor formed by said stray capacitance for a certain period of time, even though it is not memorized accurately and therefore cannot be read.
There was a drawback in that when the data was read, defective products were incorrectly determined to be non-defective products.

Furthermore, since the information stored in the capacitor disappears due to discharge after a certain period of time has elapsed, it is possible to accurately detect defective elements by waiting for that certain period of time before testing, but this would require an extremely long test time. It has the disadvantage of requiring

The present invention has been made in order to overcome the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to easily and quickly inspect whether the memory cells themselves are good or defective in a short period of time. A new memory cell that can
It is about providing.

Another object of the present invention is to provide a novel memory cell in which the states of all memory cells can be aligned (reset) at the same time in a so-called memory array in which a plurality of memory cells are used simultaneously.

The above object of the present invention is to provide a first field effect transistor whose gate is connected to the drain of the second field effect transistor and whose source is grounded.
a second field effect transistor whose gate is connected to the drain of the first field effect transistor and whose source is grounded; are each connected to a DC power source via a load resistor, and further includes means for supplying a signal to the drains of the first and second field effect transistors, the DC voltage applied to each of the load resistors is This is achieved by a memory cell characterized in that the voltage supply power sources are provided in separate systems, and the voltages are supplied by separate power sources.

That is, the present invention eliminates the drawbacks caused by using the above-mentioned conventional method by making the DC power supply connected to the memory cell two different power supplies, and easily distinguishes between good and defective memory cells. can be detected, and the consequences are enormous.

The objects, features, and advantages of the present invention will become more apparent from the accompanying drawings and the following description.

FIG. 1 shows a conventional memory cell, and FIG. 2 is a configuration diagram showing an embodiment of a memory cell according to the present invention. Explain about cells.

The memory cell shown in FIG. 1 is composed of P-channel insulated gate field effect transistors (hereinafter simply referred to as transistors), transistors Q1 and Q2 form loads for transistors Q3 and Q4, and the voltage of DC power supply vOG is applied to transistors Q1 and Q4. It is applied to the gate of Q2 and acts as a load, and the DC power supply VDD is connected to terminal 2.

Transistor Q3. Each gate of Q4 is connected to the drain of the other side, and the source is grounded.

It is a driving transistor, and transistors Q5 and Q
6 is controlled by the address signal ㆆ during writing and reading and functions as a gate.

Terminal 3, to which the address line is connected, is normally kept at ground potential or negative potential, thereby insulating the memory cell from digit lines C and D, maintaining the conduction and cut-off states of the memory cell's transistor, and transmitting data. When the transistor Q5 and the transistor Q6 become conductive (hereinafter referred to as the addressed state) by the address signal 〆, the digit lines C and D are connected to the memory cell.

First, when writing to this memory cell, the potential to be written to the digit line C, that is, the ground potential (hereinafter referred to as logic "1'") or the potential of the DC power supply (hereinafter referred to as V
DD potential (referred to as logic "0'') is applied, and a potential opposite to the potential to be written is applied to the digit line.

In other words, when writing the logic P1- into the memory cell, the ground potential and vDD potential are applied to the digit line C1, respectively, and when writing the logic TTOI+, the VDD potential and the ground potential are applied to the digit line C1, respectively. Give a potential.

In the case of reading, logic n 1 n or logic par 0'' is read depending on whether digit line C is at ground potential or VDD potential.

For example, in FIG. 1, if transistor Q4 is in a conductive state and transistor Q3 is in a cut-off state, point B is close to the ground potential, and point A is close to the VDD potential.

When writing logic "1", set the ground potential to digit line C and VDD to digit line C in the addressed state.
Give a potential.

Then, since digit line C is at ground potential, point A is at ground potential, and since digit line C is at VDD potential, point B is at VD.
The potential becomes D, transistor Q3 becomes conductive, and transistor Q4 becomes cut off, meaning that logic +11 tf has been written.

When writing logic 1j O11, the potential applied to the digit line is reversed, and the state of the transistor is therefore reversed.

Next, when reading when the above logic "■" is written, when it is in the addressed state, point A is at ground potential, so digit line C is at ground potential, and logic jl
1 ft is read.

In the case of reading the logic tl ON, the digit line C becomes the VDD potential and logic "0" is read.

In this manner, the circuit of FIG. 1 operates as a static memory cell.

Next, if the transistor Q1 or Q2 operating as a load is damaged or not formed, and the terminal 2 and the transistor Q3゜Q4 are electrically isolated (hereinafter referred to as damaged). ) inspection by writing and reading will be explained.

When operating with a pulse such that the time period between writing to the memory cell and reading it is shorter than the retention time of capacitors CI and C2 as explained below (hereinafter referred to as high-speed operation) In this case, although the conventional memory cell shown in FIG. 1 is actually a defective product, it is detected as a good product and functioning normally.

To explain this specifically, in FIG. 1, the capacitor C1 is formed by the junction capacitance of the transistor Q1 or Q3 and the wiring capacitance connecting these transistors to the transistor Q4, and the capacitor C2 is formed by the junction capacitance of the transistor Q1 or Q3. It is formed by the junction capacitance of , the wiring capacitance connecting those transistors to the transistor Q3, etc.

If the transistor Q1 is now damaged and the drain of the transistor Q3 is electrically isolated from the DC power supply VDD, the logic 9
10? When 1 is written, point B in Figure 1 becomes a potential close to the ground potential, and point A becomes a potential close to VDD, so that the capacitor C2 is charged with a negative charge and is charged to a potential close to the VDD potential.

When reading this, the potential of digit line C is checked in the addressed state.

Since the capacitor C2 is charged with the VDD potential during the holding time, the point A becomes a potential close to the VDD potential, so the digit line C becomes a potential close to VDD and is therefore read out as logic II OII.

However, if the time between writing and reading is long enough, an insulated gate field effect transistor will have a leakage current between the drain and source, and even when no voltage is applied to the gate, a small amount of current will flow between the drain and source. Also, since the capacitance of capacitors C1 and C2 is very small due to their nature, the transistor Q
If the capacitor C2 is damaged, the charge stored in the capacitor C2 will be discharged through the transistor Q3 as a leakage current of the transistor Q3.

Even if reading is performed after this discharge, no charge is stored in the capacitor C2 as described above, so the VDD potential does not appear on the digit line C, making it impossible to read the logic ItOF+, and thus damaging the transistor Q1. can be detected.

Hereinafter, the time from when the capacitors C2 and CI are charged in this way until the stored charges become leakage currents of the transistors Q3 and Q4 and are discharged will be referred to as retention time.

Conventionally, a single power supply as described above has been used for memory cells, but according to this method, the time between writing and reading or the read operation of a defective memory cell with a damaged load transistor as described above When the inspection is performed at a high speed where the time is shorter than the retention time,
Although this memory cell is a defective product, it operates as if it were normal.

Therefore, conventional memory cells have the disadvantage that defective memory cells cannot be operated at high speed and detected.

The present invention provides a memory cell in which a defective element with a damaged load transistor as described above can be easily detected even if such a defective element with a damaged load transistor is operated at high speed. A good example of this will be described below with reference to FIG.

FIG. 2 is a configuration diagram showing an embodiment of a memory cell according to the present invention.

Terminal 2 to which the DC power supply VDD in Figure 1 is connected is the second
The terminal 1 is divided into terminals 12 and 12' as shown in the figure.
2 and 12' are connected to the drains of transistors Q1 and Q2, respectively.

The terminals 12 and 12' are also connected to DC power supplies VDDI and VDD2, respectively, which generate voltages of the same value.

The other parts are the same as those in FIG. 1, and are designated by the same reference numerals as in FIG.

If the memory cell logic "0" shown in FIG. 2 is written, transistor Q3 is cut off, and transistor Q4 is in a conductive state (in this case, VD
(where a potential close to DI is stored) is a DC power supply vD
When the terminal 12 to which D1 is connected is grounded, the point A becomes a potential close to the ground potential, so the transistor Q4 is turned off, and the point B becomes a potential close to the VDD2 potential, so the transistor Q3 becomes conductive.

Therefore, compared to before the drain side of transistor Q1 was grounded, the state of the memory cell is completely reversed after grounding.
The state is the same as if the logic '°1'' was written.

However, even if the terminal 12' is grounded when the transistors Q3 and Q4 are in the cutoff and conduction states, since the point B is at the ground potential, there is no change in the state of the memory cell, and the logic "OIt" state is maintained.

In addition, when logic 91191 is written in the memory cell, the terminal 12' to which the DC power supply VDD2 is connected
If I ground it, the result would be logical as well? The state will be the same as if +091 had been written.

However, it is clear that even if the terminal 12 is grounded when a logic "1" is written in the memory cell, the state will not change.

From this, in a memory array where multiple memory IJ &++ cells are used simultaneously, if terminal 12 is grounded, the logic II O? The memory cell in which + was written is now in a state in which logic I+ 111 has been written, and the memory cell in which logic 211 $1 was originally written remains in a state in which logic ``1'' has been written.

Therefore, in the memory array, the states of a plurality of memory cells can be simultaneously aligned by grounding the terminal 12 or 12'.

However, in the case where the 1ζ load transistor Q1 or Ql is damaged as described above, the situation is different from the above.

Assuming that transistor Q1 is now damaged, logic "0'" is written and stored, and transistor Q3
is cut off, transistor Q4 is in a conductive state, and the DC power supply VDD is turned off.
Even if the terminal 12 to which I is connected is grounded, since the transistor Q1 is damaged, the point A will not reach the ground potential, and there will be no change in the state of the memory cell.

Therefore, the state of the memory cell is not reversed.

If the logic 11191 is written in the memory cell and the transistor Q2 is damaged, the state of the memory cell will not be reversed even if the terminal 12/ to which the DC power supply VDD2 is connected is grounded.

If the load transistor Q1 or Ql is damaged in this way, even if the terminal 12 or 12' is grounded, there is no change in the conduction or cutoff state of the transistor constituting the memory cell.

Therefore, based on the above facts, a given memory cell has a logic n
If OI+ is written, then terminal 12 is grounded, and the subsequent read results in a logic ``1'', or logic Pt 199 is written, then terminal 12' is grounded, and the subsequent read results in logic II O11. If the memory cell is read out, it is determined that the memory cell is good.
If logic pH011 is read out in the former case, or logic "1'" is read out in the latter case, the memory cell can be determined to be a defective product.

According to the present invention, however, the transistors Ql and Q of FIG.
By dividing the terminal 2 to which 2 is connected and creating two terminals, terminals 12 and 12', as shown in Figure 2, and separately supplying DC power from a separate system to each terminal, multiple memory cells can be connected. It is possible to align (set or reset) the states of the capacitor at the same time and at once, and by using this principle, the capacitor can be operated with a pulse so that the cycle from writing to reading is shorter than the holding time of the capacitor. In such cases, it has conventionally been difficult to detect damage to the load transistor due to wiring capacitance, etc., but the present invention provides a method for easily detecting damage.

Although the above-described memory cell relates to a P-channel insulated gate field effect transistor, it goes without saying that the same explanation can be applied to an n-channel insulated gate field effect transistor.

Moreover, although the above description is about a memory using unipolar transistors, it goes without saying that the idea of the present invention can also be applied to a memory element using bipolar transistors.

Although one embodiment of the present invention has been described above, this is merely an example, and it goes without saying that the present invention is not limited only to the embodiment described here.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional memory cell, and FIG. 2 is a block diagram showing an embodiment of a memory cell according to the present invention. Ql, Ql, Q3. Q4. Q5. Q6...Insulated gate field effect transistor, C line, D line...
... Digit line, C1, C2 ... Stray capacitance, Terminal ... Address signal.

Claims (1)

[Claims] 1 A pair of transistors whose input electrodes and output electrodes are cross-connected to each other at the first and second nodes, and a pair of load means whose one ends are connected to each other and exhibit a steady conduction state. In a bistable circuit having the other ends of the pair of load means connected to a DC power source, power supply wiring to each other end of the pair of load means is separately provided, and one of the power supply wirings is provided separately. A bistable circuit characterized in that a DC voltage difference can be generated between the pair of transistors and the other, so that one of the pair of transistors can be forcibly made conductive and the other can be forcibly cut off. .