JPS5830190A - Method of producing printed board - Google Patents

Method of producing printed board

Info

Publication number
JPS5830190A
JPS5830190A JP12776381A JP12776381A JPS5830190A JP S5830190 A JPS5830190 A JP S5830190A JP 12776381 A JP12776381 A JP 12776381A JP 12776381 A JP12776381 A JP 12776381A JP S5830190 A JPS5830190 A JP S5830190A
Authority
JP
Japan
Prior art keywords
pattern
plating
resist
conductor pattern
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12776381A
Other languages
Japanese (ja)
Inventor
小野瀬 勝秀
啓順 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12776381A priority Critical patent/JPS5830190A/en
Publication of JPS5830190A publication Critical patent/JPS5830190A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、パターン幅が100P以下の高密度なプリン
ト板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high-density printed board with a pattern width of 100P or less.

プリント板は集積素子の高集積化に伴い、パターンの細
線化が要求され、この要求のためプリント板の製造もサ
ブトラクティブ法からアディティブ法へと移行しつつあ
る。無電解銅めっきにより、基板全面に薄い銅箔を形成
し、その上にポジマスクを用いてフォトレジストのパタ
ーンを形成した後、電気銅めっきによシレジストのない
部分に選択的に銅を厚付けするセミアディティブ法はめ
つき時間が短いため生産性に優れる利点があるが、めっ
き厚さのばらつきが大きい欠点がある。特にパターン幅
が100PL以下の場合、薄いところと厚いところでは
3倍以上達うこともあり、パターン強度等に問題を生ず
る。他方めっき触媒を含有した絶縁板上にポジマスクを
用いてフォトレジストのパターンを形成した後、無電解
鋼めっきによシレジストのない部分を選択的に導体化す
るフルアディティブ法はめつき時間が長いという欠点が
あるものの、めっき厚さのばらつきが小さく基板の大き
さ、パターンの密度に関係なく比較的均一な厚さの導体
パターンが形成できるオi点がある。
Printed boards are required to have thinner patterns as integrated elements become more highly integrated, and to meet this demand, the manufacturing of printed boards is also shifting from subtractive to additive methods. A thin copper foil is formed on the entire surface of the board by electroless copper plating, a photoresist pattern is formed on it using a positive mask, and then a thick layer of copper is selectively applied to the areas where there is no resist by electrolytic copper plating. The semi-additive method has the advantage of excellent productivity due to the short plating time, but has the disadvantage of large variations in plating thickness. In particular, when the pattern width is less than 100 PL, the width may be three times or more in thin and thick areas, causing problems in pattern strength and the like. On the other hand, the full additive method, in which a photoresist pattern is formed using a positive mask on an insulating plate containing a plating catalyst, and then the areas without resist are selectively made conductive by electroless steel plating, has the disadvantage of a long plating time. However, there is an advantage in that the variation in plating thickness is small and a conductor pattern with a relatively uniform thickness can be formed regardless of the size of the substrate or the density of the pattern.

しかしながらパターン幅が50pm前後になるど、パタ
ーンの直流抵抗が増大するため、プリント板としての電
気特性から、めっき厚さは50μm以上が必要となる。
However, as the pattern width becomes around 50 pm, the direct current resistance of the pattern increases, so the plating thickness needs to be 50 μm or more in view of the electrical properties of the printed board.

この場合レジスト膜;ターンはパターン幅よりレジスト
の厚さが犬である高形状比のパターンとなるが、このよ
うな高形状比のレジストパターン上へ無電解銅めっきを
適用する場合鋼の析出時に発生する水素ガスをレジスト
パターンの中から除去することが困難であるという問題
がある。このため導体ノくターンはポーラスとなり、機
械的強面か弱く断線しやすいし、直流抵抗卆大きいとい
う欠点があった。
In this case, the resist film; the turn is a pattern with a high shape ratio in which the thickness of the resist is larger than the pattern width, but when electroless copper plating is applied on a resist pattern with such a high shape ratio, it is difficult to There is a problem in that it is difficult to remove the generated hydrogen gas from the resist pattern. For this reason, the conductor turns were porous, had weak mechanical strength, were easily broken, and had the drawbacks of high DC resistance.

本発明の目的はこれらの欠点を解決するため、絶縁基板
上に形成した導体パターン以外の部分にフォトレジスト
を用いて高形状比のレジストパターンを形成し、無電解
めっき液をその基板に噴射させて導体パターン上に金属
を厚付けする方法を提供することである。
The purpose of the present invention is to solve these drawbacks by forming a resist pattern with a high shape ratio using a photoresist on a portion other than the conductor pattern formed on an insulating substrate, and then spraying an electroless plating solution onto the substrate. An object of the present invention is to provide a method for thickly depositing metal on a conductive pattern.

すなわち本発明を概説すれば、本発明は、絶縁基板上に
形成された導体パターンを、無電解めっきを行うことに
よシ厚い金属パターンとするプリント板の製造方法にお
いてぐ絶縁基板上の導体パターン以外の部分にめっきレ
ジストパターンする工程と、そのめっきレジストが形成
された基板に無電解銅めっき液を噴射させて導体パター
ン上に銅を析出させる工程とを含むことを特徴とするプ
リント板の製造方法に関する。
That is, to summarize the present invention, the present invention provides a method for manufacturing a printed board in which a conductive pattern formed on an insulating substrate is made into a thick metal pattern by electroless plating. Manufacturing a printed board characterized by comprising a step of forming a plating resist pattern on other parts, and a step of spraying an electroless copper plating solution onto the substrate on which the plating resist is formed to deposit copper on the conductor pattern. Regarding the method.

以下、図面に基づいて本発明を具体的に説明する。Hereinafter, the present invention will be specifically explained based on the drawings.

第1図は、本発明のプリント板の製造方法における、各
工程の基板の断面図である。
FIG. 1 is a cross-sectional view of a substrate at each step in the printed board manufacturing method of the present invention.

第1図(a)は、絶縁基板(1)に、導体パターン(2
)、ランド(2’) 、スルーホール(3)ヲ形成した
断面図である。絶縁基板(1)としては、ガラス−エポ
キシ、ガラス−ポリイミド等の絶縁板、又はその上に接
着剤を塗布したものを使用することづ:できる。
FIG. 1(a) shows a conductor pattern (2) on an insulating substrate (1).
), a land (2'), and a through hole (3) are formed. As the insulating substrate (1), an insulating board made of glass-epoxy, glass-polyimide, etc., or an insulating board coated with an adhesive can be used.

導体パターン(2)の形成は、絶縁基板(1)の上に全
面無電解めっきあるいは真空蒸着によシ銅箔?形成し之
のち、フォトエツチング法で行われる。銅張積層板を出
発材料としてフォトエツチングにより導体パターン(2
)を形成することも可能であるが、この場合細線パター
ン形成のためには5μlnの極薄鋼箔を使用したものが
好ましい。
Is the conductor pattern (2) formed on the insulating substrate (1) by electroless plating or vacuum evaporation on the entire surface of the copper foil? After forming, photo etching is performed. Using a copper-clad laminate as a starting material, conductor patterns (2
), but in this case, it is preferable to use an ultra-thin steel foil of 5 µln in order to form a fine line pattern.

第1図(1))はフォトレジスト膜(4) ′ff−形
成した断面図であり、膜厚を5QP以上とするため、ド
ライフィルム状のフォトレジストが好ましい。第1図(
C)はポジマスク(5) fe介して紫外光を照射した
断面図であり、ポジマスク(5)は導体パターン(2)
f、位置合せマークとして使用して精度よく位置合せさ
れる。導体パターン(2)の上身外の部分は、光照射に
より硬化して溶媒不溶化する。第1図(d)は現像によ
り導体パターン(2)の上のレジスト膜を溶解させて、
レジスト膜くターン(6)ヲ形成した断面図である。第
1図(e)は導体パターン(2)の上に無電解銅めっき
液の噴射によって銅(7)及び(7’)  e厚く析出
させfcvgT面図である。第1図(f)はレジストパ
ターンを除去して得られたプリント板の断面図である。
FIG. 1(1)) is a sectional view of a photoresist film (4)'ff- formed, and in order to have a film thickness of 5QP or more, a dry film photoresist is preferable. Figure 1 (
C) is a cross-sectional view irradiated with ultraviolet light through a positive mask (5) fe, where the positive mask (5) is a conductor pattern (2).
f. It is used as a positioning mark and is precisely aligned. The portion of the conductor pattern (2) outside the upper body is cured by light irradiation and becomes insoluble in the solvent. Figure 1(d) shows that the resist film on the conductor pattern (2) is dissolved by development.
FIG. 6 is a cross-sectional view of a resist film formed with a turn (6). FIG. 1(e) is an fcvgT plane view in which copper (7) and (7') are thickly deposited on the conductor pattern (2) by spraying an electroless copper plating solution. FIG. 1(f) is a sectional view of the printed board obtained by removing the resist pattern.

本発明において導体パターン(2)はめつき触媒として
の役割を果しているが、導体パターン(2)t−無電解
銅めっきの下地とした理由は以下のとおりである。
In the present invention, the conductor pattern (2) plays a role as a plating catalyst, and the reason why the conductor pattern (2) was used as a base for t-electroless copper plating is as follows.

一般のフルアディティブ法ではPi、Ag等の貴金属が
めつき触媒として使用されているが、これらは基板上に
微粒子状で付着しているだけで、絶縁基板上に強固に保
持されていない。
In the general fully additive method, noble metals such as Pi and Ag are used as plating catalysts, but these are only attached to the substrate in the form of fine particles and are not firmly held on the insulating substrate.

本発明は、銅析出時に発生する水素ガスをレジストパタ
ーンの中から除去するため、無電解鋼めっき液を絶縁基
板上に強く噴射させるが、このときPd等のめつき触媒
は絶縁基板上に強固に保持されていないため、めっき液
で洗い流されてしまい銅の析出が生じない。そればかり
でなく流出したpa微粒tは無電解銅めっき中で銅の還
元を促進するため、無電解銅めっき液の寿命を著しく短
かくするという大きな問題がある。一方、本発明のよう
に1〜5Pの厚さの導体パターン(2)をめっき触媒と
じ之場合、導体パターンは金属箔として強固に基板上に
保持されているため、めっき液を強く噴射させても流出
することなく銅の析出が生じ、厚付けが可能となる。
In the present invention, in order to remove hydrogen gas generated during copper deposition from the resist pattern, an electroless steel plating solution is strongly injected onto the insulating substrate. Since the copper is not retained in the plating solution, it is washed away by the plating solution and no copper precipitation occurs. In addition, the leaked PA particles promote the reduction of copper during electroless copper plating, which poses a serious problem of significantly shortening the life of the electroless copper plating solution. On the other hand, when plating a conductive pattern (2) with a thickness of 1 to 5 P as in the present invention, the conductive pattern is firmly held on the substrate as a metal foil, so the plating solution is sprayed strongly. Copper precipitates without flowing out, making it possible to build up the thickness.

次に本発明に用いられる無電解銅めっき装置について説
明する。第2図は、本発明で使用するめつき装置の1例
を示す概略断面図である。
Next, the electroless copper plating apparatus used in the present invention will be explained. FIG. 2 is a schematic sectional view showing an example of a plating apparatus used in the present invention.

めつき槽(8)の下にある無電解銅めっき液(9)はポ
ンプαQにより吸引され、フィルタα◇と液管理装置(
6)を通り、ノズル(至)によシレジストパターンの形
成された基板C14に噴射される。液管理装置0辱は、
液の分析そして補給と温度制御を行う。
The electroless copper plating solution (9) below the plating tank (8) is sucked by the pump αQ, and is passed through the filter α◇ and the liquid management device (
6) and is sprayed by a nozzle onto the substrate C14 on which the resist pattern is formed. Liquid management device 0 humiliation is,
Performs liquid analysis, replenishment and temperature control.

ノズル01は噴射された銅めっき液が充円錐形となるよ
うなものが用いられ、必要に応じて首振りを行うことが
できる。
The nozzle 01 is one in which the injected copper plating solution forms a full cone shape, and can be oscillated as necessary.

スプレー圧力は、1.0kg/cm2から2.0 ’9
42まで変化させることができる。圧力1.0に9/1
rn2以下では、レジスト厚さ/パターン幅の比が1以
上になるとレジストパターン間の水素ガスが完全し・こ
除去できないため析出銅がポーラスとなり信頼性が悪い
。また圧力2 、0に9層cm”以上では銅の析出速度
が遅く、場合によっては導体パターンが溶解してしまう
ことがある。
Spray pressure is 1.0kg/cm2 to 2.0'9
It can be changed up to 42. 9/1 to pressure 1.0
If the ratio of resist thickness/pattern width is rn2 or less, hydrogen gas between the resist patterns cannot be completely removed, and the deposited copper becomes porous, resulting in poor reliability. Further, if the pressure is 2.0 cm or more and the thickness exceeds 9 cm, the copper deposition rate is slow, and the conductor pattern may dissolve in some cases.

無電解銅めっき液(9)は−一に市販されているものは
すべて使用できるが、めっき析出速度から厚付は用無電
解銅めっき液が好ましい。
As the electroless copper plating solution (9), any commercially available solution can be used, but an electroless copper plating solution for thick coating is preferred from the viewpoint of the plating deposition rate.

以下本発明による実施例につき説明するが、本発明はこ
れに限定されるものでない。
Examples according to the present invention will be described below, but the present invention is not limited thereto.

実施例1 1.6 m厚さのガラス−エポキシ積層板に0.5閤φ
の穴明けを行ったのち、クロム酸−硫酸によシ表面粗化
を行った。次いで一般に行われている表面活性化法によ
り、めっき触媒としてP(1を基板上に付着させたのち
、無電解めっき液(シラプレー社製OP−78)中に浸
漬し約3μm厚さの銅箔を基板上全面に形成した。その
銅箔分フォトエツチングすることによ’) 、50 P
”幅の導体パターンと0.6ssφの゛ランドを基板上
に形成した。次にその基板上に5oPL厚のドライフィ
ルム状ネガ形フォトレジスト(デュポン社製 リストン
730FR)をホットロールラミネータで貼シ合せた。
Example 1 1.6 m thick glass-epoxy laminate with 0.5 mm diameter
After drilling holes, the surface was roughened using chromic acid-sulfuric acid. Next, P (1) was deposited on the substrate as a plating catalyst using a commonly used surface activation method, and then the copper foil was immersed in an electroless plating solution (OP-78 manufactured by Silapray Co., Ltd.) to a thickness of approximately 3 μm. was formed on the entire surface of the substrate.By photo-etching the copper foil, 50P
A conductor pattern with a width of 1.5 mm and a land with a diameter of 0.6 ssφ were formed on the substrate.Next, a 5oPL thick dry film negative photoresist (Liston 730FR manufactured by DuPont) was laminated on the substrate using a hot roll laminator. Ta.

次にポジマスクをレジスト膜上に密着させて、紫外光を
照射した。露光エネルギーは100/amであつ次。ポ
ジマスクは導体パターンと同じ50IIrrL幅の黒い
パターンが形成されたもので導体パターンを位置合せマ
ークとして精度良く位置合せした。トリクロロエタン全
用いて現像することにより導体パターン上のレジスト膜
を溶解させて、レジスト厚さ/パターン幅の比が1であ
るレジストパターンを形成した。現像はスプレー現像よ
りも超音波発生装置内に置かれた溶媒中で行う方がパタ
ーンプロファイルに優れていた。第2図の装置に基板を
置きめっき液(OF−78)を圧力1.2kg/cm2
、温度40℃、時間12時間の条件で基板)−vc噴射
させて、導体パターン上に50μmの厚さの銅を析出さ
せ友。レジストパターンを塩化メチレンではく離して、
パターン幅50μmめっキ鋼厚さ50μm1スルーホー
ル径0.4鰭φ、ランド径0,6 wφのプリント板を
得た。ここではレジストパターンをはぐ離したが、基板
上に残置して絶縁層として使用することもできる。得ら
れたプリント板は導体パターンの細線化、スルーホール
の微小化によシ、現在の技術によるプリント板(導体パ
ターン幅150InIL)の8層に収容されるパターン
をすべて収容することができた。
Next, a positive mask was brought into close contact with the resist film, and ultraviolet light was irradiated. The exposure energy was 100/am. The positive mask had a black pattern with the same width of 50 IIrrL as the conductor pattern, and the conductor pattern was used as an alignment mark for accurate alignment. The resist film on the conductor pattern was dissolved by development using trichloroethane, and a resist pattern having a resist thickness/pattern width ratio of 1 was formed. The pattern profile was better when the development was carried out in a solvent placed in an ultrasonic generator than by spray development. Place the substrate in the apparatus shown in Figure 2 and apply the plating solution (OF-78) at a pressure of 1.2 kg/cm2.
Then, copper was deposited to a thickness of 50 μm on the conductor pattern by spraying the substrate with VC at a temperature of 40° C. for 12 hours. Strip the resist pattern with methylene chloride,
A printed board with a pattern width of 50 μm, a plated steel thickness of 50 μm, a through hole diameter of 0.4 fin φ, and a land diameter of 0.6 wφ was obtained. Although the resist pattern was peeled off here, it can also be left on the substrate and used as an insulating layer. The obtained printed board was able to accommodate all the patterns accommodated in the 8 layers of a printed board (conductor pattern width: 150 InIL) according to current technology due to the thinning of the conductor pattern and the miniaturization of the through holes.

実施例2 レジスト厚さ/パターン幅の比が2のレジストパターン
を形成するため、実施例1と同様の方法にて基板上に導
体パターン全形成し、ドライフィルムラ貼シ導体パター
ンとポジマスクを位置合せして紫外光を照射したのち、
現像を行わず、紫外光の照射され几その第1層目のレジ
スト膜上に同じドライフィルム状ネガレジスト膜をホッ
トロールラミネータで貼シ合せた。同じポジマスクを用
いて導体パターンと位置合せし、第2層目のレジスト膜
に密着させて紫外光を照射した。第1層のレジスト膜の
露光エネルギーは実施例1で述べたよシ少なく80/c
rn2であったが、第2層目のレジスト膜への露光エネ
ルギーは実施例1と同じ1001nJ42であつfc6
第1層目と@2層目のレジスト膜に光照射したのち、導
体パターン上の第1層目と第2膚目のレジスト膜を同時
に現像によシ溶解させてパターン幅が50Pでレジスト
厚さが1oo、mの高形状比のレジストパターンを得た
。次いで第2図の装置を用いて無電解銅めっき液(シラ
プレー社製 CP−78)を基板に噴射させて、導体パ
ターン上に100Pの厚さの銅を析出させた。
Example 2 To form a resist pattern with a resist thickness/pattern width ratio of 2, the entire conductor pattern was formed on the substrate in the same manner as in Example 1, and the dry film lamination conductor pattern and positive mask were positioned. After irradiating with ultraviolet light,
The same dry film-like negative resist film was laminated using a hot roll laminator onto the first resist film that had been irradiated with ultraviolet light without being developed. Using the same positive mask, it was aligned with the conductor pattern, brought into close contact with the second layer resist film, and irradiated with ultraviolet light. The exposure energy of the first layer resist film is 80/c as described in Example 1.
rn2, but the exposure energy for the second layer resist film was 1001nJ42, the same as in Example 1, and fc6.
After irradiating the first and second resist films with light, the first and second resist films on the conductor pattern are simultaneously developed and dissolved, so that the pattern width is 50P and the resist thickness is A resist pattern with a high shape ratio of 1 oo.m in diameter was obtained. Next, using the apparatus shown in FIG. 2, an electroless copper plating solution (CP-78 manufactured by Silapray Co., Ltd.) was sprayed onto the substrate to deposit copper with a thickness of 100 P on the conductor pattern.

形状比(レジスト厚さ/パターン幅の比)が2であるた
め、水素ガスを完全に除去するためには、圧力は1.8
″9/c−が必要であった。まためっき時間はめつき温
度40°Cで55時間が必要であった。レジストパター
ンを塩化メチレンではく離して、パターン幅50μm1
めつき銅厚さ100μm1スルーホール径Q、5mφ、
ラント径0.6關φの高密度プリント板を得た。このプ
リント板は細線パターンであるがめっきが厚いため、熱
衝撃(−65℃×”50分←→125°C×30分)試
験1000サイクル後でも断線等の問題はなく信頼性に
優れていた。
Since the shape ratio (resist thickness/pattern width ratio) is 2, the pressure must be 1.8 to completely remove hydrogen gas.
The plating time was 55 hours at a plating temperature of 40°C.The resist pattern was peeled off with methylene chloride, and the pattern width was 50 μm1.
Plated copper thickness 100μm 1 through hole diameter Q, 5mφ,
A high-density printed board with a runt diameter of 0.6 mm was obtained. Although this printed board has a thin line pattern, the plating is thick, so even after 1,000 cycles of thermal shock (-65°C x 50 minutes ← → 125°C x 30 minutes) test, there were no problems such as disconnections and it was highly reliable. .

実施例3 At203セラミツク板(厚さ1簡)上にPd ’1l
l−含有する接着剤を約10P厚さ塗布したのち、クロ
ム酸−硫酸で表面粗化1−て、その接着剤の上に約2μ
mの銅箔を形成し友。その銅箔をフォトエツチングする
ことによシバターン幅25Pnの導体パターンとした。
Example 3 Pd '1l on At203 ceramic plate (1 piece thick)
After applying an adhesive containing l- to a thickness of about 10P, the surface is roughened with chromic acid-sulfuric acid, and a layer of about 2μ is applied on the adhesive.
Form a copper foil of m. The copper foil was photoetched to form a conductor pattern with a pattern width of 25Pn.

次いで25μm厚のドライフィルム状ネガ形レジスト(
デュポン社製リストノ1010) ’iホットロールラ
ミネータで基板上に貼り合せ、第1層目のレジスト膜を
形成した。実施例2と同様にポジマスクを介して露光し
たのち、現像を行うことなく、第2層目のレジスト膜を
形成し、もう一度ボジマスクを介して露光した。露光エ
ネルギーは第1層目のレジスト膜には40 tnJA、
、で第2層目のレジスト膜には50“0X12であった
。露光後第1層目と第2層目のレジスト膜を同時に現像
して、パターン幅25PrrL1 レジスト厚さ50I
trrLの形状比が2であるレジネトパターンを導体パ
ターンを避けて形成した。第2図のめつき装置を用いて
圧力2.0ラタ2、温度40°C1時間20時間の条件
で導体パターン上に50μm厚のめつき銅を形成した。
Next, a 25 μm thick dry film negative resist (
Listono 1010 (manufactured by DuPont) was bonded onto a substrate using a hot roll laminator to form a first resist film. After exposure through a positive mask in the same manner as in Example 2, a second resist film was formed without development, and exposure was performed once again through a positive mask. The exposure energy was 40 tnJA for the first resist film.
, the second layer resist film was 50"0x12. After exposure, the first and second layer resist films were developed simultaneously to form a pattern width of 25PrrL1 and resist thickness of 50I.
A resinet pattern with a shape ratio of trrL of 2 was formed avoiding the conductor pattern. Plating copper having a thickness of 50 μm was formed on the conductive pattern using the plating apparatus shown in FIG. 2 under the conditions of a pressure of 2.0 ra and a temperature of 40° C. for 1 hour and 20 hours.

レジストパターンを塩化メチレンではく離して、セラミ
ック板上にパターン幅25μ光、めっき銅厚さ50μ漢
のプリントパターンを形成した。導電性インクを用いて
スクリーン印刷で形成したセラミックプリント板と比較
して、細線パターンでしかも直流抵抗の小さい高密度プ
リント板を得た。
The resist pattern was peeled off with methylene chloride to form a printed pattern on a ceramic plate with a pattern width of 25 μm and a plated copper thickness of 50 μm. Compared to a ceramic printed board formed by screen printing using conductive ink, a high-density printed board with a fine line pattern and low DC resistance was obtained.

以上説明したように本発明によるプリント板の製造方法
は、導体パターンをめっき触媒とし、導体パターン上を
避けて形成された高形状比のレジストパターンをめっき
レジストとして用いて無電解銅めっき液を噴射させてめ
っき銅を導体パターン上に形成したものであるから、め
っき銅がポーラスになることなく厚く形成できるため、
パターンが細線であるにもかかわらず信頼性、電気的特
性に優れ几プリント板が製造できる利点がある。
As explained above, the method for manufacturing a printed board according to the present invention uses a conductor pattern as a plating catalyst, and injects an electroless copper plating solution using a resist pattern with a high shape ratio formed avoiding the conductor pattern as a plating resist. Since the plated copper is formed on the conductor pattern, the plated copper can be formed thickly without becoming porous.
Although the pattern is a thin line, it has excellent reliability and electrical characteristics, and has the advantage of being able to produce solid printed boards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(f)は、本発明によるプリント板の製
造方法における、各工程の基板の断面図である。第2図
は、本発明で使用する無電解銅めっき装置の1例を示す
概略断面図である。 1:絶縁基板、2:導体パターン、2′:ランド、3ニ
スルーホール、4ニレジスト膜、5:ポジマスク、6:
レジストパターン、7.7’:めつ°き銅、8:めつき
槽、9:無電解銅めっき液、10:ポンプ、11:フィ
ルタ、12:液管理装置、13:ノズル、 14ニレジストパターンの形成された基板特許出願人日
本電信電話公社 代理人中 本  宏
FIGS. 1(a) to 1(f) are cross-sectional views of the substrate at each step in the printed board manufacturing method according to the present invention. FIG. 2 is a schematic sectional view showing an example of an electroless copper plating apparatus used in the present invention. 1: Insulating substrate, 2: Conductor pattern, 2': Land, 3 Varnish through hole, 4 Ni resist film, 5: Positive mask, 6:
Resist pattern, 7.7': Plating copper, 8: Plating tank, 9: Electroless copper plating solution, 10: Pump, 11: Filter, 12: Liquid management device, 13: Nozzle, 14 Resist pattern Formed substrate patent applicant Hiroshi Moto, agent of Nippon Telegraph and Telephone Public Corporation

Claims (1)

【特許請求の範囲】 1、 絶縁基板上に形成された導体パターンを、無電解
めっきを行うことによシ厚い金属パターンとするプリン
ト板の製造方法において、絶縁基板上の導体パターン以
外の部分にめっきレジストを形成する工程と、そのめっ
きレジストが形成された基板に無電解鋼めっき液を噴射
させて導体パターン上に銅を析出させる工程とを含むこ
とを特徴とするプリント板の製造方法。 2、 該めっきレジストを形成する工程において、導体
パターンをポジマスクの位置合せ一マークとして使用す
る特許請求の範囲第1項に記載のプリント板の製造方法
[Scope of Claims] 1. In a printed board manufacturing method in which a conductor pattern formed on an insulating substrate is made into a thick metal pattern by electroless plating, the conductor pattern is formed on a portion other than the conductor pattern on the insulating substrate. A method for producing a printed board, comprising the steps of forming a plating resist and depositing copper on a conductor pattern by spraying an electroless steel plating solution onto the substrate on which the plating resist is formed. 2. The method for manufacturing a printed board according to claim 1, wherein in the step of forming the plating resist, the conductive pattern is used as an alignment mark for a positive mask.
JP12776381A 1981-08-17 1981-08-17 Method of producing printed board Pending JPS5830190A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12776381A JPS5830190A (en) 1981-08-17 1981-08-17 Method of producing printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12776381A JPS5830190A (en) 1981-08-17 1981-08-17 Method of producing printed board

Publications (1)

Publication Number Publication Date
JPS5830190A true JPS5830190A (en) 1983-02-22

Family

ID=14968085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12776381A Pending JPS5830190A (en) 1981-08-17 1981-08-17 Method of producing printed board

Country Status (1)

Country Link
JP (1) JPS5830190A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182188A (en) * 1984-02-29 1985-09-17 矢崎総業株式会社 Circuit board and method of producing same
JPH06198608A (en) * 1993-01-08 1994-07-19 Soritsudo Giken Kk Preparation of square pillar timber using log

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182188A (en) * 1984-02-29 1985-09-17 矢崎総業株式会社 Circuit board and method of producing same
JPH06198608A (en) * 1993-01-08 1994-07-19 Soritsudo Giken Kk Preparation of square pillar timber using log

Similar Documents

Publication Publication Date Title
JP5213094B2 (en) Method and process for embedding conductive vias in a dielectric layer
TWI400024B (en) Wiring substrate and its manufacturing process
JPS62158393A (en) Manufacture of printed circuit
KR20100024449A (en) Wiring substrate manufacturing method
JP2003234573A (en) Method of manufacturing multilayer wiring board, and multilayer wiring board manufactured by the same
KR20010105366A (en) Method of manufacturing multilayer wiring board
TW200407057A (en) Method for the manufacture of printed circuit boards with integral plated resistors
JPH06275950A (en) Manufacture of wiring board
EP0837623B1 (en) Method for the manufacture of printed circuit boards with plated resistors
JP3402372B2 (en) Manufacturing method of wiring board
US5922517A (en) Method of preparing a substrate surface for conformal plating
JPS5830190A (en) Method of producing printed board
CN112996259B (en) Manufacturing method of circuit boards with different copper thicknesses
JPH05327224A (en) Manufacture of multilayer wiring board and multi-layer wiring board manufactured by the manufacture
JP4826020B2 (en) Manufacturing method of multilayer wiring board
JP3500977B2 (en) Manufacturing method of double-sided circuit board
JP2002271026A (en) Multi-layer printed wiring board and manufacturing method therefor
EP0848585A1 (en) Process for the manufacture of printed circuit boards with plated resistors
JP3828205B2 (en) Method for manufacturing transfer member and transfer member
JPH1140951A (en) Manufacture of multilayred wiring board
JPH03225894A (en) Manufacture of printed wiring board
JPH1168291A (en) Printed wiring board and production thereof
JPH05259609A (en) Manufacture of printed wiring board
JPH10270859A (en) Manufacture of multilayered wiring substrate
JPH04118992A (en) Manufacture of printed circuit board