JPS5828844A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5828844A
JPS5828844A JP56126714A JP12671481A JPS5828844A JP S5828844 A JPS5828844 A JP S5828844A JP 56126714 A JP56126714 A JP 56126714A JP 12671481 A JP12671481 A JP 12671481A JP S5828844 A JPS5828844 A JP S5828844A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor substrate
conductive
semiconductor device
photo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56126714A
Other languages
Japanese (ja)
Inventor
Nobutake Konishi
信武 小西
Masami Naito
正美 内藤
Tomoyuki Tanaka
知行 田中
Tokuo Watanabe
篤雄 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56126714A priority Critical patent/JPS5828844A/en
Publication of JPS5828844A publication Critical patent/JPS5828844A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To assemble gate means such as a photo guide which is required for ignition of a photo thyristor without breaking it by providing the positioning member such as insulation ring etc. which specifies the mutual positional relation between a semiconductor basic element and at least the one of a pair of conductive materials and the gate means such as a photo guide arranged on a pair of main surfaces of such basic element. CONSTITUTION:The other end of L-shaped photo guide 6 is bent at the center of a semiconductor device and its end point is facing to the light sensing surface of a semiconductor (photo thyristor) 101. The conductive members 2, 3 are composed of copper and is hermetically sealed from the cylindrical insulator 5 via the flanges 71 and 72 consisting of the Fe-Ni alloy. The insulation ring 40 is placed in such a way as being engaged with the semiconductor basic element 1 comprising the conductive member 3, photo thyristor 101 and supporting electrode 102. The portion allowing insertion of the L-shaped photo guide 6 of the conductive member 2 is provided with the cut-away part 20 which is engaged with a part of the insulation ring 40.

Description

【発明の詳細な説明】 本発明ば1へ導体装置に係り、背に加圧]&触型半導体
装置に191する。3 加圧接触博士導体装置は、少なくとイ)1つのPn接合
を有する半導体基体の一対の主表面に、゛電極および6
苅1体としての作1[1を兼ねる・、1+11賛本を加
圧接触さ伊たt71j造を有する。以下、第1図を参照
しつつその基体構造と利点について;IBべろ。7麻1
図において、゛1′導体基体1 it、一般に少々くと
も1つのPn接合が内部に形成された半導体101とこ
れを機械的な破jすlから保護するためのy詩1ti極
板102とから構成され、両者けろう4Mで固着結合さ
れている。半導体101はシリコン、ゲルマニウム、支
持市極板102けl″j、り体]01とρノ(膨張係数
の近いタングステン、モリブデン等が広く用いられてい
る。半導体基体Iの一対の主表面には、一対の置市部材
2,3が固着されることなく可滑動状態で加圧接触され
る。該導電部材2゜3は電気的熱的に抵抗の小さな部材
が好寸しく、例えば銅等が広く用いられている。導電部
材2゜3に用いられる銅は半導体101に比べて熱膨張
係数が一般に大きいため、半導体基体1と固着してし1
つと、半導体装置の運転時に受ける熱ザイクルによって
大きな熱応力が半導体101に発生し、半導体1010
屯気的特性に悪影響を及ぼす。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conductive device (1), applying pressure to the back and a touch type semiconductor device (191). 3. The pressure contact doctoral conductor device includes at least a) a pair of main surfaces of a semiconductor substrate having one Pn junction;
As a single body, it has a pressure contact with the 1 + 11 parts, which also serves as 1. The base structure and advantages thereof will be explained below with reference to FIG. 1; IB Vero. 7 hemp 1
In the figure, a conductive substrate 1 is generally made up of a semiconductor 101 with at least one Pn junction formed therein and an electrode plate 102 for protecting it from mechanical damage. Both are fixedly connected with 4M glue. The semiconductor 101 is made of silicon, germanium, supporting electrode plate 102, a solid body]01 and ρ (tungsten, molybdenum, etc. with similar expansion coefficients are widely used.On the pair of main surfaces of the semiconductor substrate I The pair of placement members 2 and 3 are pressed into contact with each other in a slidable state without being fixed.The conductive members 2 and 3 are preferably made of a material with low electrical and thermal resistance, such as copper or the like. Copper used for the conductive member 2.3 generally has a larger coefficient of thermal expansion than the semiconductor 101, so the copper used for the conductive member 2.3 is bonded to the semiconductor substrate 1.
Then, a large thermal stress is generated in the semiconductor 101 due to the thermal cycle that the semiconductor device undergoes during operation, and the semiconductor 101
It has a negative effect on the temperament characteristics.

極端な場合は、半導体101に亀裂が生じる場合がある
。かかる欠点を解消するために前記の如く一対の導電部
月2,3と半導体基体1とは固着しないで加圧接触させ
る構造が提案された。このような構造は現在では、犬心
力用のダイオード、トランジスタ、ザイリスタ等の半導
体装置に広く使用されている。
In extreme cases, cracks may occur in the semiconductor 101. In order to eliminate this drawback, a structure has been proposed in which the pair of conductive parts 2, 3 and the semiconductor substrate 1 are pressed into contact with each other without being fixed to each other as described above. Such structures are now widely used in semiconductor devices such as diodes, transistors, and Zyristors for dog-like forces.

一ブバ可滑動な加圧接触構造を採用するため、半導体基
体1と電極部材2,3との位置ずれを防ぐ保持手段が新
たに必要になった。保1、!方法としては第1図に示し
た構造が公知である。即ち、リング状の絶縁体4を導電
部材3と1′ノ、9体ノ11体1の1t411而に契合
する様に設け、該絶縁体4に1つ−C1半導体基体1は
導rlf ’Ffl≦月3(1′こX”j I、 にf
 <ij−決めされる。
In order to employ a pressurized contact structure that is slidable, a new holding means is required to prevent the semiconductor substrate 1 and the electrode members 2 and 3 from being misaligned. Ho 1,! As a method, the structure shown in FIG. 1 is known. That is, a ring-shaped insulator 4 is provided so as to engage with the conductive members 3 and 1', 1t411 of the 9th body and 11th body 1, and one -C1 semiconductor substrate 1 is connected to the insulator 4 so as to be connected to the conductive members 3 and 1'. ≦Month 3 (1'koX"j I, ni f
<ij-determined.

別な・構造として、該絶縁体4を曲刃の)#11部利2
に接触契合させて半導体基体1が導電部AK 2に対し
て位置決めされる構造がある。また、半導体基体1が筒
状絶縁、体5の内1111腹11に7+jして位置決め
される構造も公知である。
As another structure, the insulator 4 is a curved blade) #11 part 2
There is a structure in which the semiconductor body 1 is positioned with respect to the conductive part AK 2 in contact with the conductive part AK 2 . Further, a structure in which the semiconductor substrate 1 is positioned at 7+j on the inner 1111 side 11 of the cylindrical insulating body 5 is also known.

以」二述べた従来1SJ造では、半・、r14体基体重
を保1、イする1]的は達成されるが、−利の導、に部
材2,3の中心軸がずれて加圧接触される恐れがある。
In the conventional 1SJ construction mentioned above, the goal of maintaining the base weight of the half- and r14 bodies is achieved, but due to the disadvantage, the central axes of the members 2 and 3 are shifted and pressure is applied. There is a risk of being contacted.

中心軸ずれが生じるど、加圧時に半jM体基体1♀曲げ
ようと1−る応力が働き、この曲げ応力のために半導体
101に不均一な荷重がかかり電気的、熱的抵抗の不均
一を生じるために五Mf、東中を起す等、電気的特性へ
の悪影響がある。捷だ、半導体基体1がザイリスタの場
合、ゲート接続手段を筒状絶縁体5の一部を貫通させて
半導体装置の中心に向つて伸はしその先端をL字状等に
曲げて半導体101の所定部、例えばその中心に位置さ
せる必要がある。さらに、半導体基体1が光サイリスタ
の場合は、このゲート接続手段には光ガイドが用いられ
る。これらの場合は、第1図に示すように導電部材2の
一部に切欠部20を設ける必要があり、半導体装置を組
立てる場合に、半導体1は導電部材2,3のみならず、
光ガイド6とも位置合わせをする必要が生じる。特に、
光サイリスタの場合、光ガイドは一般にガラス性物質で
構成されており機械的強度が弱いので、導電部材2を最
後に組込む工程を採用するときに、上記導電部材2と光
ガイド6とは中心軸のみならず回転方向も位置決めする
ことが、光ガイド6の保護という点で重要である。
When a center axis misalignment occurs, a stress is applied to bend the semi-JM body substrate 1♀ when pressurized, and this bending stress causes an uneven load to be applied to the semiconductor 101, resulting in uneven electrical and thermal resistance. This has an adverse effect on the electrical characteristics, such as causing 5Mf, East and Middle. If the semiconductor substrate 1 is a Zyristor, extend the gate connecting means through a part of the cylindrical insulator 5 toward the center of the semiconductor device, bend the tip into an L-shape, etc., and connect the semiconductor 101. It is necessary to locate it in a predetermined part, for example, in the center. Furthermore, if the semiconductor body 1 is an optical thyristor, a light guide is used as the gate connection means. In these cases, it is necessary to provide a notch 20 in a part of the conductive member 2 as shown in FIG.
It is also necessary to perform alignment with the light guide 6. especially,
In the case of an optical thyristor, the light guide is generally made of a glass material and has low mechanical strength. Positioning not only in the rotational direction but also in the rotational direction is important in terms of protecting the light guide 6.

本発明の目的は、上述した欠点を解決すると共に光ザイ
リスタの点弧に必要な光ガイド等のゲート手段を破損さ
せないように組立てることが可能な構造の半導体装置を
提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure that solves the above-mentioned drawbacks and can be assembled without damaging gate means such as a light guide necessary for ignition of an optical thyristor.

本発明は、半導体基体とその一対の主表面側に配置推さ
れる−7・」の導電部材の少なくとも一方及び光ガイド
等のゲート手段の相互位置関係を規定する絶縁リング等
の位置決め部材を設けることを!]4徴とする。
The present invention provides a positioning member such as an insulating ring that defines the mutual positional relationship between at least one of the conductive members and the gate means such as the light guide, which are arranged on the semiconductor substrate and its pair of main surfaces. That! ] There are four signs.

以下、本発明の特徴とするところ全具体的な実施例をも
って詳細に説明する。第2図15、本発明の第1実施例
の縦断面構造を示す。lJ字型光ガイド6Vi、石英ガ
ラス単体あるいは、=1ア、クラッド層を有する石英フ
ァイバでt1η成さ扛ており、筒状絶縁体5を貫通しこ
れと銀ろうで接層されている金属スリーブ60の中空部
を通って半導体装置の外部に伸びている。光ガイド6ば
、化学的安定性に優れている点で、無・磯材別から成る
ことが好捷しい。該り字型光ガイドの他端は半導体装置
の中心で曲っており、その先端は半導体(以下光ザイリ
スタ)101の受光部に而している。導電部材2,3は
銅で構成されており、筒状絶縁体5とはFe−N1系合
金で構成さnているフラッジ71及び72を介して気密
対重されている。絶縁リング40は、導電部材3(以下
、下ボス]・)及び光ザイリスタ101と支持電極10
2から構成された半導体基体(以下光サイリスタサブア
センブリ)■と契合するように配置している。導電部材
2(以下、上ボスト)のL字型光ガイドが挿入される部
分(は切欠部20を設けてあり、該絶縁リング40の一
部401は該切欠部20にはめ合う114造になってい
る。第3図に該絶縁リング40の立体図を示す。絶縁リ
ング40としては、機械的に変形しにくり、かつ、化学
的、熱的に安定である材料、例えばセラミックス、テト
ラフルオロエチレン衿から成ることが望外しい。
Hereinafter, the features of the present invention will be explained in detail with reference to all specific embodiments. FIG. 2 15 shows a vertical cross-sectional structure of the first embodiment of the present invention. The J-shaped light guide 6Vi is made of quartz glass alone or t1η of a quartz fiber with a cladding layer, and is a metal sleeve that passes through the cylindrical insulator 5 and is bonded to it with silver solder. 60 and extends to the outside of the semiconductor device. Since the light guide 6 has excellent chemical stability, it is preferable that the light guide 6 is made of solid wood or made of rock material. The other end of the L-shaped light guide is bent at the center of the semiconductor device, and its tip is connected to the light receiving part of the semiconductor (hereinafter referred to as an optical zyristor) 101. The conductive members 2 and 3 are made of copper, and are hermetically sealed to the cylindrical insulator 5 via fludges 71 and 72 made of Fe--N1 alloy. The insulating ring 40 connects the conductive member 3 (hereinafter referred to as the lower boss), the optical zyristor 101 and the supporting electrode 10.
The optical thyristor subassembly (hereinafter referred to as the optical thyristor subassembly) (2) is arranged so as to be engaged with the semiconductor substrate (hereinafter referred to as an optical thyristor subassembly) (2). The portion of the conductive member 2 (hereinafter referred to as the upper boss) into which the L-shaped light guide is inserted is provided with a notch 20, and a portion 401 of the insulating ring 40 has a 114 structure that fits into the notch 20. Fig. 3 shows a three-dimensional view of the insulating ring 40.The insulating ring 40 is made of a material that is resistant to mechanical deformation and is chemically and thermally stable, such as ceramics and tetrafluoroethylene. It is undesirable that it consists of a collar.

次に、本発明の第1実施例の組立て法の一例を示す。筒
状絶縁体5と下ボスト3をフランジ72を介して溶接し
た後、光サイリスタサブアセンブリ1を挿入する。次い
で、L字型光ガイド6を金属スリーブ60の中空部を通
し、光ガイド6と金属スリーブ60の一部とを気密接着
する。気密接着する方法並びに構造は種々あるが、本発
明の内容には直接関連しないので省略する。次いで第3
図に示した切欠部402をL字型光ガイドの案内として
絶縁リック゛40を挿入12、光−リーイリスクザブア
センブリ1の外側面と契合させ、該光ガイドの先端と光
サイリスク201の受光部とをF91定の位置関係とな
る」:うにする。その後、該絶縁リングの内側に伸びた
突出部/101を案内と1〜て上ボスト2をllli人
し、該」−ボスト2を11て)伏、他11イ(体5のフ
ランジ71を介1〜で溶接し、気密構■告とする。
Next, an example of an assembly method of the first embodiment of the present invention will be shown. After welding the cylindrical insulator 5 and the lower boss 3 via the flange 72, the optical thyristor subassembly 1 is inserted. Next, the L-shaped light guide 6 is passed through the hollow part of the metal sleeve 60, and the light guide 6 and a part of the metal sleeve 60 are hermetically bonded. There are various methods and structures for airtight contact, but they are not directly related to the content of the present invention and will therefore be omitted. Then the third
An insulating click 40 is inserted 12 using the notch 402 shown in the figure as a guide for the L-shaped light guide, and is engaged with the outer surface of the optical fiber subassembly 1. be in a fixed positional relationship with F91. After that, guide the protrusion 101 extending inside the insulating ring to the upper boss 2, and then lower the upper boss 2 (through the flange 71 of the body 5). Weld in step 1 to create an airtight structure.

本実施例に」:れば、該絶縁リング40の突出部401
を案内として」ニボス]・2を挿入する。このとき、光
ガイド6は絶縁リック40にて保護さ扛ているから、光
ガイド6f:破4fiさす−1−に+ボスト全セットで
きる。
In this embodiment, the protrusion 401 of the insulating ring 40
Insert "nibos]・2 using as a guide. At this time, since the light guide 6 is protected by the insulating lick 40, all the posts can be set in the light guide 6f: break 4fi -1-.

第4図は、本発明の第2実MIL例の4(に断面構造を
示す。第2図と同−符弓゛の1部分に]第2図における
と同等部品を示す。本実施例では絶縁リック41の−1
SIS 413は金属スリーブ60の外径と契合する」
:うな構造となっている。第5図に絶縁リング41の立
体図ケ示す。金属スリーブ60と契合するような突出部
413を設けることにより、I咳絶縁すング41は、筒
状絶縁体5と相対位置が失する。このため、絶、謙リン
グ41が円周方向に回転するのを防ぐことができ、光ガ
イド6を破損することがない。かつ突出部411を具え
ているため第1の実施例で示したと同様に上ポスト2を
容易に案内できる。また、本実施例では下ポスト3のサ
ブアセンブリ1側での外径と絶縁リング41の内径とが
1賂同じにされている。
FIG. 4 shows the cross-sectional structure of the second actual MIL example of the present invention. In the same part of the arch as in FIG. 2, parts equivalent to those in FIG. -1 of insulation lick 41
SIS 413 engages the outer diameter of metal sleeve 60.
: It has an eel structure. FIG. 5 shows a three-dimensional diagram of the insulating ring 41. By providing the protrusion 413 that engages with the metal sleeve 60, the I-cough insulator 41 loses its relative position to the cylindrical insulator 5. Therefore, it is possible to prevent the circumferential ring 41 from rotating in the circumferential direction, and the light guide 6 will not be damaged. In addition, since the protruding portion 411 is provided, the upper post 2 can be easily guided in the same manner as shown in the first embodiment. Further, in this embodiment, the outer diameter of the lower post 3 on the subassembly 1 side and the inner diameter of the insulating ring 41 are made the same.

第6図、第7図は、本発明の第3.4の実施例であり、
各々第3図、第5図の実施例の変形である。第6図、第
7図に示した構造の絶縁リングは、半導体装置を組立て
る手順を変えた場合に採用可能な構造を示す。即ち、上
ポスト2の筒状絶縁体5を最初にフランジ71を介して
溶接した後、光ザイリスタサブアセンブリ1、次いで絶
縁リング42あるいは43、下ポスト3の順に組立てる
場合に適する。各々の効果は、上記したように、絶縁リ
ング42は40と、43は41と同様である。
6 and 7 are embodiments 3.4 of the present invention,
These are modifications of the embodiments shown in FIGS. 3 and 5, respectively. The insulating rings having the structures shown in FIGS. 6 and 7 show structures that can be adopted when the procedure for assembling the semiconductor device is changed. That is, it is suitable for the case where the cylindrical insulator 5 of the upper post 2 is first welded via the flange 71, and then the optical zyristor subassembly 1, then the insulating ring 42 or 43, and the lower post 3 are assembled in this order. As described above, the effect of each of the insulating rings 42 and 43 is similar to that of 40 and 41, respectively.

第8図は、本発明の第5の実施例の縦断面構造を示す。FIG. 8 shows a longitudinal cross-sectional structure of a fifth embodiment of the present invention.

絶縁リング44は、その内側面の半径が、上ボスト3の
外側面の半径より大きいが、絶縁リングの−に端に突出
部414を有し、これらによって上ポストと絶縁リック
44とを契合させる。第9図に絶gIJング44の立体
図を示す。第5図に示した第2の実施例との相違点1:
突出部414゜415′に:設けた点にあるが、これを
設けることにより、」−下ボスト2,3と絶縁リック4
4の位置関係を規定することができるため、上ボスト2
゜下ボスト3、光ザイリスタザブアセノブリ200及を
さらに精度良く相ズ・1位l青を規定することができる
。寸だ、スリーブ60には、絶縁リングの位置決め用の
つば61が設けられている。
The insulating ring 44 has a radius on its inner surface larger than the radius on the outer surface of the upper post 3, but has a protrusion 414 at the negative end of the insulating ring, which allows the upper post and the insulating lick 44 to engage. . FIG. 9 shows a three-dimensional view of the absolute gIJ ring 44. Difference 1 from the second embodiment shown in FIG. 5:
Protrusions 414° and 415': By providing these, the lower bosses 2 and 3 and the insulating licks 4
4 can be defined, the upper boss 2
゜The lower boss 3, the optical fiber assembly 200, and the phase/first position blue can be defined with even greater accuracy. The sleeve 60 is provided with a collar 61 for positioning the insulating ring.

以」−述べた絶縁リングは一体化(〜た(11−j造を
図示したが、2個若しくはそれ以−4−の部品で構成し
ても良いことは明らかである。この」烏合、各1<16
材間の絶縁性が確保されるならば、一部に嗜電材全使用
しても良い。斗だ、絶縁リングの周壁は円筒状のみなら
ず、全体としての形全ぐずさない限り、変形させたり、
部分的に窓を明けたり、棚状としても良い。更に、第8
図、第9図で示した突出部414全絶縁り/グの周方向
全体に設けても良いし、他の実施例にこれを応用しても
良い。このように実施例相互間の部分的応用は自由であ
る。半導体としては、同様の課題がある限り電気ゲート
ザイリスタ#にも適用できる。寸だ、支持型@j!、)
L202を省略したものであってもよい。更に、半導体
と上ボストの間に公知のインタープルバッファを追加し
たものであっても良い。本発明は両面圧接型あるいは片
面圧接型に適用し得る。
Although the insulating ring described above is shown as an integral structure, it is clear that it may be constructed of two or more parts. 1<16
As long as the insulation between the materials is ensured, all electrically conductive materials may be used in some parts. The circumferential wall of the insulating ring is not only cylindrical, but it can also be deformed as long as the overall shape remains intact.
You can partially open the window or create a shelf. Furthermore, the eighth
The protrusion 414 shown in FIGS. 9 and 9 may be provided in the entire circumferential direction of the entire insulation ring, or may be applied to other embodiments. In this way, parts of the embodiments can be freely applied. As a semiconductor, it can also be applied to electric gate zyristor # as long as it has similar problems. It's a support type @j! ,)
L202 may be omitted. Furthermore, a known interple buffer may be added between the semiconductor and the upper boss. The present invention can be applied to a double-sided pressure contact type or a single-sided pressure contact type.

以上説明したように、本発明によれば、位置決めが容易
かつ確実で部材の破損の恐れのない半導体装置を得るの
に効果がある。
As explained above, according to the present invention, it is possible to obtain a semiconductor device whose positioning is easy and reliable and whose members are free from damage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置を示す縦断面図、第2図ない
し第9図は本発明半導体装置の実施例をi説明する図で
あり、第2図、第4図、第8図は半導体装置の縦断面図
、第3図、第5図、第6図、第7図、第9図は絶縁リン
グの立体図である。 2.3・・・導電部材(上ポスト、下ポスト)、4゜4
0.41..42,43.44・・・絶縁リング、■・
・・半導体基体(光ザイリスタザブアセンブリ)、第 
1 図 / 第 2図 皐 3 図 審 40 牢 8 図 第 C/ 図
FIG. 1 is a longitudinal sectional view showing a conventional semiconductor device, FIGS. 2 to 9 are diagrams for explaining an embodiment of the semiconductor device of the present invention, and FIGS. The longitudinal sectional views of the device, FIGS. 3, 5, 6, 7, and 9 are three-dimensional views of the insulating ring. 2.3... Conductive member (upper post, lower post), 4゜4
0.41. .. 42,43.44...Insulation ring,■・
・・Semiconductor substrate (optical xyristor subassembly), No.
1 Figure / Figure 2 3 Figure 40 Prison 8 Figure C / Figure

Claims (1)

【特許請求の範囲】 1 少くとも1つのPn接合を有する半導体基体、該半
導体基体をその一対の主表面の両−〇から挾持する一対
の導シ部材及び、該導電部材と一体化されて気密容器を
形成しこの気密容器日に上記半導体基体を封止する筒状
絶縁体、筒状絶縁体を貫通し、外部からの信号を半導体
基体の所定部に伝えるゲート手段を有し、上記半導体基
体の両生表面に上記導電部材を直接あるいlま間接的に
その少なくとも一方を押圧して心気的並びに熱的接触を
得る半導体装置に2いて、上記半導体基体及び少なくと
も1つの4区部材にその周囲から契合してこれらを位置
決めする部分と上記ゲート手段全案内する切欠部を有す
る1つの4区部材の上記切欠部とはめ合わせされる部分
とを備える位置決め部材を有することを特徴とする半導
体装置。 2、特許請求の範囲第1項において、上記位置決め部材
は非弾性を有し、熱的、化学的に安定な絶縁材で構成さ
れていることを%徴とする1″、・、q体装置濾。 3、特許請求の範囲第1頂にF、−いて、ヒ記ノーI・
手段は、無機拐イ;31からなる光ガイドであり、1−
記半導体基体は光ザイリスタであることを’R1+−徴
とする半導体装16゜
[Scope of Claims] 1. A semiconductor substrate having at least one Pn junction, a pair of conductive members that sandwich the semiconductor substrate from both sides of the pair of main surfaces thereof, and an airtight conductive member that is integrated with the conductive member. a cylindrical insulator that forms a container and seals the semiconductor substrate in the airtight container; a gate means that penetrates the cylindrical insulator and transmits a signal from the outside to a predetermined portion of the semiconductor substrate; The conductive member is directly or indirectly pressed on at least one of the conductive members on the amphibatic surface of the semiconductor device to obtain inspiratory and thermal contact. A semiconductor device characterized in that it has a positioning member that includes a portion that engages from the periphery to position them, and a portion that fits into the notch of one four-section member that has a notch that guides all of the gate means. . 2. In claim 1, the positioning member has inelasticity and is made of a thermally and chemically stable insulating material. 3. F at the top of the first claim, and I.
The means is a light guide consisting of inorganic particles; 1-31;
A 16° semiconductor device having 'R1+- characteristics that the semiconductor substrate is an optical zyristor.
JP56126714A 1981-08-14 1981-08-14 Semiconductor device Pending JPS5828844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56126714A JPS5828844A (en) 1981-08-14 1981-08-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56126714A JPS5828844A (en) 1981-08-14 1981-08-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5828844A true JPS5828844A (en) 1983-02-19

Family

ID=14942039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56126714A Pending JPS5828844A (en) 1981-08-14 1981-08-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5828844A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61176502A (en) * 1985-01-30 1986-08-08 Yamaide Kosan Kk Thermally molded article for insecticidal and fungicidal use
US4757366A (en) * 1985-04-12 1988-07-12 Siemens Aktiengesellschaft Light-triggerable thyristor having low-loss feed of the trigger energy
JPH01129423A (en) * 1987-11-16 1989-05-22 Fuji Electric Co Ltd Flat semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61176502A (en) * 1985-01-30 1986-08-08 Yamaide Kosan Kk Thermally molded article for insecticidal and fungicidal use
US4757366A (en) * 1985-04-12 1988-07-12 Siemens Aktiengesellschaft Light-triggerable thyristor having low-loss feed of the trigger energy
JPH01129423A (en) * 1987-11-16 1989-05-22 Fuji Electric Co Ltd Flat semiconductor device

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