JPS5828611B2 - Interrupt method for list processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to processing information stored in the memory of a digital computer system.

Information is organized as a chained list of elements.

Each element can be used, for example, to contain a data record.

Organizing data records in the form of a chained list of elements can facilitate retrieval and updating of data, for example.

List processing in a computer system refers to operations such as inserting, removing, or searching elements on a chained list in a storage device.

A chained list is also called a queue.

FIG. 1 shows the structure of a typical chained list 2.

The header 4 of the linked list 2 contains status information 4s about the list and the address 4a of the first element on the list.

Linked list 2 also includes a plurality of elements 6, 8 and 10.

Adjacent elements of a territory do not necessarily have to be adjacent in storage.

Each element includes an address field 6a-10a for encoding the address of the next element on the list, a key field 6-10k for encoding a priority number and a data field 6d-10d. .

The priority number in the key field is used to order the elements on the list.

For example, elements can be arranged on a list in order of increasing key value, with the lowest value key at the beginning of the list.

Japanese Patent Application No. 53-77554 discloses a computer system particularly suitable for processing such chained lists.

Among typical list processing operations are removing and inserting elements in chained lists.

The act of removing an element with a desired key value involves searching the list one element at a time until an element with the desired key value is found.

This element is then removed from the list by moving the address contained in that element's address field to the address field of the previous element on the chain.

In this way the chain is forced to bypass the removed element.

Insertion operations are typically performed in a similar manner. List processing operations can be very time consuming due to the sequential nature of insert and remove operations and the fact that chains can be very long.

For this reason, it is desirable that list processing operations be interruptible, allowing the computer to process occasional tasks.

One solution used in the past is to allow interrupts to occur between processing of adjacent elements in the chain.

If an interrupt occurs, the list processing operation simply ends and is later restarted from the beginning.

The disadvantage of this approach is that if the chain is very long and the interruptions are fairly frequent, a situation may arise where the list processing operation cannot be completed.

Additional difficulties may arise if elements of one chain are listed on different pages of the virtual storage system.

In such a case, the address field of an element of the chain stored in main memory may refer to an element that, for example, is not currently in main memory, but is in a page stored on disk. unknown.

Search operations encountering this address will generate a "page not found", which will cause not only the referenced page to be loaded but also to restart the search.

However, the page containing the territory's previous elements may have been removed from main memory to make room for the newly loaded page.

Therefore, in that case a second page fault will occur before the originally referenced element is encountered.

For very long chains, such page faults and load operations can occur periodically and the originally referenced element may not be reachable.

Such periodic page fault and load behavior in a virtual memory system is called "thrashing".
g) It is called j and can be a very troublesome problem.

The list processing scheme of the present invention allows list processing operations to be restarted following an interrupt while avoiding the problems of the prior art described above.

In particular, the present scheme allows for interrupting and restarting sequential list processing operations.

List processing operations involve sequentially accessing a plurality of elements in a digital computer's storage.

List processing operations are identified by list processing descriptors.

Each element includes an address field encoding the address of the next element to be accessed.

Preferably, the encoding is the binary address of the next element.

Multiple elements ordered by an address field define a chain of elements.

The beginning of the chain is defined by a header, which contains an address field encoding the address of the first element of the chain.

The method of the present invention includes the step of receiving and taking an interrupt signal indicating that a sequential list processing operation is to be interrupted.

The method further includes the step of setting a busy bit position in the chain header to indicate that the territory listing operation has been interrupted.

For example, the busy bit position is set to a logic one.

The method further includes the step of loading the interrupt address field of the chain header with the address of the element being accessed by the list operation when the interrupt signal is received.

Also, the interrupt action field of the chain header is loaded with the list action descriptor.

The method of the present invention also includes the step of accepting and taking requests to perform requested list processing operations.

The requested list processing operation has an access request descriptor.

This may or may not be the same descriptor stored in the interrupt action field of the chain header.

Whether a request to perform a requested list processing operation is granted depends on the information stored in the header and the access request descriptor.

Accordingly, the method further includes the steps of reading the status of the busy bit from the header and comparing the access request descriptor with the descriptor stored in the interrupt action field of the header.

One of three alternative steps is then taken.

The first alternative step is to determine if the state of the busy bit indicates that the territory list processing operation has been interrupted and the access request descriptor matches the descriptor stored in the interrupt operation field of the header. If so, the step is to restart the requested list processing operation at the element whose address is stored in the interrupt address field of the header.

A second alternative step is if the state of the busy bit indicates an interrupt of the territory's list processing operation and the access request descriptor did not match the descriptor stored in the interrupt operation field of the header. , prohibiting restart of the requested list processing operation.

A third alternative step is to restart the requested list operation in the first element of the chain if the state of the busy bit indicates that the territory's list operation was not interrupted. This is the step of

One feature of the invention is that the method allows interruptible list processing in a virtual memory computer system.

The thrashing problem described above is avoided because the interrupted list processing operation is restarted from the element in the territory where the interruption occurred.

A second feature of the invention relates to the protection of data stored on the chain during interrupt periods.

If a first list processing operation is interrupted, the element of the chain on which the operation was being performed will not be modified by any second list processing operation during the course of the interruption.

When the first list processing operation is restarted, the territory's data will be in the same state as before the interruption.

The method of the present invention can be implemented on a computer system using hard-wired logic circuits.

Furthermore, if the computer system has a microprogrammed CPU, the method of the present invention could be implemented by microprogramming the CPU.

The following is a detailed description of the invention as implemented in a digital computing system particularly suited for list processing.

The digital calculation system is based on the patent application filed in 1983, cited earlier.
For details regarding its architecture and repertoire of list processing instructions, please refer to the above documents.

Modifications of the above apparatus that facilitate the implementation of the invention are listed below.

Referring to FIG. 2, instruction register 20 includes three fields: an OP code field 24, a base register field 26, and an address field 28.

Opcode field 24 contains a machine language instruction called the SENDM instruction.

The SENDM instruction requests certain list processing operations (see specification of said application).

For purposes of understanding the invention, it is sufficient to know that the SENDM command causes an element called a send/receive message (SRM) to be inserted at the appropriate priority position in a chain called a send/receive queue (SRQ).

The SENDM instruction is a task dispatching element (TD
K) (see above).

Therefore, the address of the task dispatching element that executes the SENDM instruction can serve as a descriptor for the SENDM instruction.

The address field 28 of the instruction register 20 is
Contains the address of the location in storage of the header 34 of the receive queue 30.

Base register field 26 of instruction register 20
identifies a base register 46 containing the address of the location in storage of the unchained send/receive message 48 to be inserted into the send/receive queue 30 by a SENDM operation.

Unchained Send/Receive Message 48 Key Field 4
8k, including an address field 48a and a data field 48d.

In addition to the header 34, the send/receive queue 30 has first, second and third send/receive messages 31-33.

Valley send/receive messages are in key field 31~3
3k, address fields 31a-33a and data fields 31d-33d.

The numbers stored in key field 31 to 33k are:
A relative priority is established between the sent/received messages 31-33 which determines the order in which they are placed in the territory.

The address field 31a of the first sent/received message 31 contains the address of the second sent/received message 32;
Field 32a likewise contains the address of the third sent/received message 33.

The address field 33a of the third sent/received message 33 contains zero, which means that the message is sent/received.
This means that it is the last element of the receive queue 30.

The address of the first sent/received message 31 is header 3
SRM address field 35 of No. 4.

The header 34 also includes a status field 36, a busy
bit field 37, interrupt operation field 38,
It also has an interrupt address field 39 and a first TDE address field 40.

Neither status field 36 nor first TDE address field 40 are relevant to any of the novel aspects of the present invention and will not be further described.

The meaning of each field of busy bit 37, interrupt operation 38 and interrupt address 39 will be explained below along with an example.

In addition to OP1 address register 41, CTDE address register 42 and PCH address register 43
is used to store the addresses of items in storage that are relevant to SENDM operations.

CTDE address register 42 stores the address of the current task dispatching element executing a SENDM instruction.

The address stored in CTDE address register 42 thus serves as a descriptor for the SENDM instruction.

The PCH address register 43 is S E N D M
Stores an address pointing to the address field of the sent/received message accessed by the instruction.

Interruption and restart of the SENDM instruction according to the present invention will now be described with reference to FIGS. 2 and 3.

In the following description, it will be assumed that the key odd value of the non-chain transmitted/received message 48 is greater than the key odd value of the third transmitted/received message 33.

The SENDM operation therefore inserts the send/receive message 48 at the end of the send/receive queue 30.

FIG. 2 schematically shows the state of the computer immediately before an interrupt during the course of a SENDM operation.

OP1 address register 41 contains the address of the header 34 of transmit/receive queue 30 that is accessed by a SENDM operation.

The PCH address register 43 contains the address of the address field 32a of the second send/receive message 32, which in turn contains the address of the third send/receive message 33.

The key value in the key field 33 of the third sent/received message is therefore compared with the value stored in the key field 48 of the unchained sent/received message 48.

In the situation shown in Figure 2, any interrupt will be sent to the SE in the CPU.
It has no higher priority than the NDM command.

Since a list processing instruction is in progress, the busy flag in header 34
Bit field 37 is a logical zero.

When the busy bit field is zero, neither the interrupt action field 38 nor the address interrupt field 39 of the header 34 is accessed, so these two fields can contain arbitrary numbers.

FIG. 3 diagrammatically illustrates the state of the computer after SENDM operations are restarted following an interrupt.

The interrupt occurred after the second send/receive message 32 was accessed and before the third send/receive message 33 was accessed.

Interrupts activate and activate task dispatching elements.
Move from the status and stop execution of the SENDM command.

If an interrupt signal occurs before the state of FIG. 3, the address in PCH address register 43 is stored in the interrupt address field of header 34.

The address in CTDE address register 42 is stored in interrupt operation field 38.

Also, the header busy bit field 37 is set to a logic 1 value at the time of an interrupt and remains at a logic 1 value during the interrupt period.

At the end of the interrupt, the task dispatching element that issued the SENDM instruction regains active status.

Therefore, the SENDM instruction is executed again.

The descriptor of the SENDM instruction, ie the address of the task dispatching element that executes the instruction, is compared to the address stored in interrupt action field 38.

Since the descriptors are the same, the busy bit is cleared to logic zero and execution of the SENDM instruction is executed at the second address whose address is stored in the interrupt address field 39 of the header 34.
The transmission/reception message 32 is restarted.

When busy bit 37 is cleared to a logical value O, any list processing operation can access transmit/receive queue 30.

If the SENDM instruction is executed by a task dispatching element with a different address than the task dispatching element that was interrupted, the descriptors do not match and the SENDM instruction allows access to the send/receive queue 30. It will not be done.

An additional mechanism incorporated into the computer of the above-mentioned Japanese Patent Application No. 53-77554 facilitates the handling of interrupts.

The computer provides a mechanism for storing the contents of the address and base registers of a task dispatching element when the task dispatching element loses active status, e.g. when an interrupt with a higher priority occurs. has.

Thus, the interrupted task dispatching element can begin operation after the interrupt ends using the instruction it was executing when the interrupt occurred.

The flow of operation is summarized below.

When an interrupt signal is received, the I10 latch in the CPU is set.

The I10 latch is tested and if there is no interrupt then a normal SENDM cycle is performed and if there is an interrupt the busy bit field 37 is set.

The address of the task dispatching element that will then execute the SENDM instruction (thus serving as a descriptor for the SENDM instruction) is then stored in the interrupt action field 38 of the header 34.

The address of the transmitted/received message being accessed at the time of the interrupt is then stored in the interrupt address field 39.

The system then handles the interrupt.

When there is a request to execute a SENDM instruction, the state of busy bit field 37 is tested.

If the busy bit is O, the SENDM command is started from the beginning of the transmit/receive queue 30.

If the busy bit is 1, the address of the task dispatching element executing that SENDM instruction (which serves as a descriptor for the requested SENDM instruction) is compared with the descriptor stored in interrupt action field 38.

If the two descriptors match, the SENDM instruction is restarted.

If the two descriptors do not match, the SENDM instruction is prohibited.

There is no intention to limit the invention to the particular embodiments described above.

It is clear that the invention can be used to provide interruptability for various list operations.

The list processing operations described in the above-mentioned Japanese Patent Application No. 77554/1983 to which the present invention is particularly suited include message sending (SENDM), message reception (RECM), message enqueue (ENQM), and message dequeue. It is a command.

As is clear from the above description, list processing operations can be made more efficient by using the present invention.

By using the interrupt scheme of the present invention, page faults can be handled without having to restart the entire list instruction, and different tasks can be scheduled within the CPU without having to complete multiple processing instructions.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a chain of elements in the prior art, and FIG. 2 is an explanatory diagram of an embodiment of the present invention, which is an explanatory diagram of a chain list of elements in a storage device and related registers during a list processing operation before an interrupt. FIG. 3 is an explanatory diagram of the chained list and registers of FIG. 2 when restarting the list processing operation after an interrupt. 30... Send/receive queue 31-33...
...Sent/received message, 34...Header, 37...Busy bit field, 38
...Interrupt operation field, 39...
Interrupt address fields, 31a-33a, 35.
...Address field.

Claims (1)

[Scope of Claims] 1. Each element includes an encoded address field specifying the address of the next element, and a plurality of elements ordered by the address field form a chain of elements, List processing, the starting point of which is defined by a header containing an encoded address field specifying the address of the first element of the chain, and which comprises sequentially accessing said plurality of elements located in the storage of a digital computer. In this method, the operation is interrupted and restarted, and in response to an interrupt signal indicating that the above list processing operation should be interrupted, the busy bit position in the above header is set to indicate that the above list processing operation was interrupted. At the same time, the address of the element being accessed by the above list processing operation is set to the interrupt address field in the above header, and the list processing descriptor identifying the instruction that was performing the above list processing operation is set to interrupt. When the receiver receives a command to execute a list processing operation for the chain after starting the specified interrupt processing, the busy flag in the header of the chain is stored in the operation field. reading the state of the bit and comparing the descriptor identifying the received instruction with the descriptor stored in the interrupt action field in the header of the chain, and determining whether the state of the busy bit is a list for the chain; If the descriptor indicating that the processing operation has been interrupted and identifying the received instruction matches the descriptor stored in the interrupt operation field,
Restarting the requested list operation with the element located at the address stored in the interrupt address field of the header, and confirming that the state of the busy bit indicates that the list operation for the chain has been interrupted. and the descriptor identifying said received instruction does not match the descriptor stored in said interrupt operation field, prohibits the initiation of said requested list processing operation and sets the state of said busy bit to An interrupt method comprising initiating said requested list processing operation from the first element of said chain if the list processing operation for said chain indicates that it has not been interrupted.