JPS5826389A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make the operation stable, by setting an operation time of precharge/sense amplifier in the unit of column lines corresponding to an output buffer circuit in response to the potential change with the output of a row decoder to be selected. CONSTITUTION:A dummy row line DWL having the same resistance and capacitance as a row line WL is commonly provided for memory cell arrays 11-1n, and circuits 21-2n to precharge collumn lines Q1-Qn of each array corresponding to an output buffer circuits of data input/output circuits 71-7n are controlled with precharnge signals PC1-PCn. The each signal PCi is generated at every change of an address signal of a row decoder 3 and controlled depending on the potential change of nodes A-E on the line WDL. Further, the row decoder 3 generates data to select the line DWL together with the line WL in response to the address at each address signal input. As a result, sense amplifiers 61-6n and the circuits 71-7n do not start operation at the same time, allowing to decrease an instantaneous peak current.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory having a plurality of outputs, and more particularly to a semiconductor memory with reduced peak current.

1 and 2 show different conventional examples of semiconductor memories having a plurality of output bits. In FIG. 1, column lines in memory cell arrays 11 to In are all precharged simultaneously by a column line precharge circuit 2 in synchronization with a precharge signal PC, and a row decoder 3
The contents of the memory cell selected by are displayed on column lines Qt-Qn. Then, the column decoder 4 selects the column selection circuit 51.
.about.5n are driven, and the data of the column line selected by the column selection circuits 51.about.5n is detected by the sense amplifiers 61.about.6n and outputted from the data input/output circuits 71.about.7n.

In FIG. 2, column line data is detected by a sense amplifier, and the output of this sense amplifier is output from column selection circuits 51 to 51.
5. is selected and output from data input/output circuits 71 to 7nK.

In the conventional semiconductor memory described above, the width of the precharge signal PC is determined by detecting that the output data of the row decoder 3 has reached the end of the row line WL (point E). . That is, since the column line WL is normally wired using straight silicon, it has a resistance of about 30Ω/hole. However, since the 5-row line WL is connected to the dirt of the memory cell (transistor/transistor), it has a considerably large load capacitance. Therefore, on the row line W L VC, the node A near the row decoder 3
Naturally, there is a difference between the data rise time of the node E and the data rise time of the node E that is far from the row decoder. Therefore, conventionally, as mentioned above, when the data on the row line reaches point E, that is, when the row line WL uniformly reaches the "1# level," precharging of the column line is continued, and The precharge signal PC was cut off after confirming that the precharge signal PC was at the level shown in FIG. 3. FIG. 3 shows an example of a precharge circuit.

However, in the semiconductor memory described above, the sense amplifiers 61 to 6n operate at the same time as precharging is stopped, and the data is transmitted to the output buffer circuits of the data input/output circuits 71 to 7n. For this reason, each sense amplifier 61
6n and the output of multiple bits of data to the outside are performed simultaneously, so the instantaneous peak current becomes extremely large. This causes noise in the power supply, and this noise also causes damage to the circuits in each part of the memory.
The margin for each production is small. In particular, when multiple bits of data are output to the outside at the same time, the external usually has 150P.
Since a large capacitance on the order of F is added, the instantaneous peak current becomes extremely large just by charging and discharging this capacitance.

The present invention has been made in view of the above circumstances, and the recharging time or the sense amplifier is adjusted for each column line corresponding to the output buffer circuit according to the potential change determined by the position from the row decoder on the selected row line. By setting the operation start time, it is possible to prevent multiple bits of data from being output at the same time, and to provide a semiconductor memory that can reduce instantaneous peak current.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 shows a part of a semiconductor memory, and unlike the conventional circuit described above, a dummy row line DWL having the same resistance and capacitance as the row line WL is provided in common for each memory cell array 11 to 1n. That's what I do. And the column line Q of the memory cell array 11-In corresponding to the output/9271 circuit of the data input/output circuits 71-7n! The operations of column line recharging circuits 21 to 2n for precharging lines 5 to 5 are individually controlled by precharge signals PC1 to PCn. In this case, precharge signal PC
I - PCn occurs every time the address signal input to the row decoder 3 changes, but the timing is such that the rise time of each one is sequentially delayed depending on the position of the corresponding memory cell array 11 to In from the row decoder 3. It is occurring in In addition, precharge signals PC1~
PCn is controlled so that the respective fall times are delayed by an I1m order in accordance with potential changes at nodes A-E on the dummy row line yl that have passed through the corresponding memory cell arrays 11 to 1n.

In this case, the row decoder 3 is configured to generate data (decode output) so as to select the dummy row line DWL along with the row line WL corresponding to the address each time an address signal is input, and also to select the dummy row line DWL. A circuit is provided to detect potential changes (data levels) at each node A-E on line DwL.

In other words, according to the above circuit, whereas the precharge time was conventionally determined at point E, the rise of the potential at each of the nodes B-E spaced apart from the row decoder 3 on the dummy row line DWL is checked. At node B, a precharge signal 48 PCby is generated, and at node C, a precharge signal pc21, . . . is sequentially generated, thereby setting each precharge time. Therefore, the data is transferred to the input/output circuits 71 to 7.
The time transmitted to the output buffer 7 of n is faster for memory cells closer to the row decoder 3, and all sense amplifiers 61 to 6n and output circuits 71 to 7n do not start operating at the same time. , the instantaneous peak current will be significantly reduced. Moreover, because conventionally data was output at the same time as node E reached the "1" level, the overall time required for data output in the circuit described above is not slower than in the past. .

It should be noted that when the address input changes as shown in FIG. 5, the potential of the dummy row line (K) changes from the "0" level to the "1 level" in the same way as the selected row line WL. In this case, Even on the same dummy row line DWL, the node A closest to the row decoder 3 rises first, and the farthest node E rises last. The pulse width of the precharge signal PCI-PCn is determined as shown in FIG. 6 in response to the rise of the -E potential.In other words, when the node B of the dummy row line DWI rises, the signal P itself falls; Suspend precharge.

As shown in FIG. 6, precharge signal PCn corresponds to the conventional precharge signal PC. Furthermore, these precharge signals PC+ -PCn attain the "1" level in synchronization with the change in the address signal, and the precharge start timings are also made to differ in consideration of the increase in instantaneous leakage current.

10- FIG. 7 shows an address buffer circuit that transmits address input data Ai to the decoder circuits 3 and 4. In this circuit, there is a transistor T1 to which chip operation signals C and E are input to r-to, a depletion type transistor Tz whose r-) and sources are interconnected, and a transistor T3 to which address data At is input to date. is connected between the power supplies VC and Vg, and the transistors T 2 + T 3 constitute the first inverter 11 . A transistor T4 to which an inverted signal CE of the signal CE is input is connected between the output terminal of the inverter 11 and the power supply vII. Similarly, the transistor T! is connected between the power supplies Vc' and Va. i-T is connected, and the transistor f-) is connected to the first inverter! ! The output of the transistor T7 and the transistor T6 constitute a second inverter I2. Between the output terminal of this inverter I and the power supply vI+, ? -) is connected to a transistor T8 to which the inverted signal CE is applied. Furthermore, transistors T9~
T12 is provided with the same jf# configuration as above, and the first buffer Bl is provided with transistors T13*T14.
However, the transistor Tt51'r18 constitutes the second buffer B2. These first. 2nd buffer B
1+B2 output end, respectively? - A transistor TITT1s is provided to which an inverted signal is applied. Further, the output of the second inverter I2 is connected to the r-to of the transistors T'ts to T'ts, and the third inverter I3
The outputs of are applied to the dates of transistors T14*Tlg, respectively.

Further, the output of the first inverter 11 is set as C11, the output of the second inverter I2 is set as DI, the output of the first buffer B is set as the address buffer output A1, the output of the second buffer B is set as the inverted address output, and the output of the NOR output AI It is said that

In the address buffer circuit described above, the chip operation signal C
When E is “1” and the inverted signal convex is “0”, the circuit operates,
Conversely, when the signal CB-"0" and CE="1", the circuit becomes inactive. Further, at this time, the current consumption flowing through the circuit is made to be approximately zero. Then, the signal CE="0"
When #, the address data At is related to <address buffer/.

The outputs A% and At are both at the "1" level. here,
First, the chip is selected (that is, CE="1")
, CFJ="0"), when the address data Ai changes, the aforementioned precharge signal PC.

~Explain how a Pen is made.

In FIG. 7, the signal Ct is an inverted signal of the address data Ai, and is delayed in time by the amount of the inverter 11 compared to the data AI. Moreover, the signal D1 is an inverted signal of the signal C1, and is an inverted signal of the signal C1. It lags behind the signal C1 by the amount of time. Output At.

At/ is delayed in time by the amount of the first buffer B1 and the second buffer of the inverter I31 and the inverter Is of the signal Di.

FIG. 8 shows an address change detection circuit, in which the drain receives the signal C1 from the inverter Il of FIG.
A transistor T19 is supplied with the signal AI from the buffer B1 shown in FIG.
The transistor Tll0 is supplied with the signal Di from the buffer B shown in FIG. 7, and the signal n from the buffer B in FIG. transistor T3
1, a trunk transistor T22 whose drain is connected to the source of the transistor T20 and whose source is connected to the power supply Vs, a nordart 8 which gates the output Ct of this transistor T19 and the output D1 of the transistor Tto, and this nord f- )8 output and the node E of the row line WL mentioned above.
A nordart 9 that darts a signal, a transistor 'hs to which the output of this nordart 9 is input to f-), and a transistor T to which the output of the nordart 8 is inputted to f-).
It has a goose 4. Note that the above-mentioned Noah f-)8°9 constitutes a flip-flop. The transistors TtseT4 are successively connected between the power supplies VceV@ to constitute a buffer circuit B3, and the output of this buffer circuit B3 becomes a precharge set signal PC8. This precharge set signal pc
s is led to a delay circuit consisting of a resistor R and a capacitor C shown in FIG.
8n is generated. Of course, as long as it is a delay circuit, it does not have to be composed of resistors and capacitors. These signals pcs1 to PC8n are connected to one NOR gate 1o constituting the corresponding flip-flip shown in FIG.
is input to the other gate 11, each node B- of the row line is inputted to
E potential is input, and precharge signals Pct to PCn corresponding to the aforementioned precharge circuits 21 to 2n are output from the output end of this clip/flip. Damn, this flip-flip is a signal pcs
, to the number corresponding to PC8n.

Next, the operation of the above circuit will be explained with reference to the signal waveform diagram of FIG. In the circuit of FIG. 7, as mentioned above, the signal Ct is delayed by the imper 511 with respect to the address input At, the signal Di is delayed by the inverter 11+It, and the signal Ct is delayed by the inverter 11+It. /J-ta I3 + barafu Bg are each delayed by the amount. When any signal C1 changes from 101 to "1", the signal ci also changes to "O" through the transistor T19.
'' to "1", and immediately after the change, in the circuit of FIG. 8, the address buffer output CI is transferred to the transistor T'.
It is discharged at zt and becomes "0". The signal C1 becomes "1" momentarily when Ai changes from "Bi" to "O".Similarly, the signal DI momentarily becomes "1" when At changes from "0" to "1". , the output of Noah gate 8 is “O”
, the output of the gate 9 becomes "1". At this time, node E
This is because the potential of is "O". The transistor T'zs is turned on, the transistor T24 is turned off, and the precharge set signal PC8 becomes "1#." Since addresses AO~ are input to the above gate 8, if any address changes, f The IJ charge set signal Pc changes to "1". This signal PC8 is converted into a signal PC81" P which is sequentially time-delayed in the circuit shown in FIG.
It becomes O2n.

On the other hand, the flip-flop in Fig. 10, signal pcs at 7''
If 1 is input to Noah 'r''-toIo, then Noah
The node B potential is input to '-to ZJ.

Therefore, if the signal pcs l becomes 11", the noa date 1
The output of 1 becomes "1", and a precharge signal Pc1 corresponding to the precharge circuit 21 is generated.

At this time, the potential at node B is "0". Similarly, from each flip-flip to each nori charge circuit 22 to 2n
Precharge signals pc1 to PCn corresponding to are generated,
As a result, a charge operation for column lines Qt to Qn is performed.

FIG. 12 shows a circuit for obtaining dummy address buffer outputs Bi and Bi input to the decoder of the dummy row line DWL.

In this circuit as well, like the circuit shown in FIG. - The address buffer output At' is at r-t of T'gt.
are respectively input, and the transistor T26 r
T27 constitutes an impertae 3'. Further, a delay circuit 12 is provided which includes a transistor ``rso'' connected in series and a capacitor C1 having one end connected to a power source 8. Similarly, the transistors T30'' and T32 constitute an inverter ``5'', and the transistors T8m*T@4 constitute an inverter ``6'', and between these inverters I, I, and I, the same transistor T35 and a capacitor ftCt' are constructed. A delay circuit 13 is provided.A transistor T36 is provided, the dart is connected to the output terminal of the inverter I4, the buffer output AI' is connected to the drain, and the source becomes the dummy address output Bl'. Dirt at the output end of E6.

However, each transistor T3? has its drain connected to the buffer output Al', and its source serves as the inverted dummy address output B1'. is provided.

A transistor T38 to which a delayed chip operation signal CED is applied to r18-- is provided between these dummy address outputs B i and B i'.

FIG. 13 shows a circuit for producing the delayed chip operation signal CED. In this circuit, the power source V e .

Transistor T39 + T2O connected between Vs
The output terminal of the inverter ・■7 and the transistor T
A delay circuit 14 consisting of a transistor T45 and a capacitor C1 similar to those described above is provided between the input terminal of the inverter 41*T4z and the input terminal of the inverter 8. Then, the chip operation signal CE is inputted to the inverter I7, and the delayed chip operation signal CED delayed by a predetermined time is outputted from the inverter I8.

In the circuit shown in FIG. 12 described above, the signal CE is "1".
At this time, the delay signal CgD is also 11".

are short-circuited by a transistor T'ss for a certain period of time in delay circuits 12 and 13, respectively, and become in-phase signals. When the buffer output A1 changes from 11' to "O", the signal A i
'Dkeko, A? 'D is @0#. These signals AI
D and 7D, like the signals Ai' and Al', erroneously become "O" and "1" at certain times, respectively. At this time, the signal n is “
1", the signals Bi and Bj return to "1".

FIG. 14 shows a general row decoder circuit that inputs address data A6-An and selects a predetermined row line WL, and FIG. 15 shows a dummy row decoder circuit that selects a dummy row line rm. It shows 1~.

The aforementioned address buffer output AI'yA? is the first
The dummy buffer outputs Bi and Bi are input to the circuit of FIG. 4 to select the row line WL, and the dummy buffer outputs Bi and Bi are input to the circuit of FIG. 15 to select the dummy digit line DwL. Here, the address buffer outputs Ai, Ai input to the row decoder in FIG.
At approximately the same time as , dummy address output Bo + Bo,
-B1 r Bi, -Bn+Bn are input to the dummy row decoder in FIG. Figure 15 is Nord 15
We have shown a decoder that selects one dummy row line by one input of each dummy address output using
(n -1-1) dummy row lines are provided, and dummy address outputs Bo, Bo, -B+ + B1,
``'One dummy row line may be selected for each by Bn+Bn.The row line W selected by the above circuit
When L changes from the "0" level to the "1 degree level," the dummy row line DWL also changes from the "0" level to the '1' level at approximately the same time, and as a result, each node B to E signal is generated. Become. This node B-E signal is input to the flip-flop shown in FIG. 10, and the precharge signal P
C1-PCn are sequentially set to the "0" level, and the precharge cycles of the column precharge circuits 21 to 2n are sequentially completed.

Next, the chip operation signal CE changes from "0" to "1".

The operation when the signal CE changes level from "1" to 0" and the chip enters the operating state will be explained with reference to the voltage waveform diagram in FIG. 16. When the chip changes from the non-operating state to the operating state. The signals CI' and C1 are generated in the same manner as described above.The precharge set signals PC81 to PC8n in FIGS. 8 to 1.θ, and the precharge signals PC1 to PCn become "1#". Everything up to this point is exactly the same. The above chip operation signal CE is from “0”
1" level, the delayed chip operation signal CED shown in FIG. 13 becomes "0" after a fixed time delay than the chip operation signal.
From “1”. Therefore, when the address buffer output AI changes from "1" to "O", the signal CED changes to "O".
There are up to 1 of m. Therefore, the signal Bl changes from “1” to “0”.
" level, but the signal old remains at "1".

After a certain period of time, when the delayed chip operation signal CED becomes "1", a signal is generated. When the signal Bi changes from "1" to the '0# level, the row decoder 3 also selects the row line by the address buffer output Ai + At. At this time, the signal Bl
changes from "1" to "0" level, and thereby the selected dummy row line changes from "0" to "1" level. Then, the node B-E potential signal of this dummy row line B■ is input to the flip-flop shown in FIG. The precharge operation in the precharge circuits 21 to 2n is completed.In other words, the chip operation signal CE changes from "O" to "1".
'' level, the above-mentioned circuit operates erratically.

FIG. 17 shows an example of operating the sense amplifier f6 in synchronization with the precharge signal PCI-PCn. In this way, the operating time of the sense amplifier 6 can be shifted, thereby reducing the instantaneous peak current. It can be further reduced. Furthermore, when the precharge operation for the column lines Qn, Qn is completed and the information of the selected memory cell is present on the column lines Qn, Qn, the precharge signals PC, ~PCn that operate the sense amplifier 6 are output. No, the operation of this sense amplifier 6 can also be made faster.

In the above embodiment, the row line, that is, the dummy row line DWL is “0”.
” to “1” level and set the nori charge period, but in the present invention, the dummy row line changes to “1” level.
The recharging period may be determined by detecting a change from the level to "0" level. At this time, the drain of the transistor T311 in FIG. 12 is connected to the signal Bi+Bi or the signal Bn in FIG. 15 instead of the signal AI.
, Bn is input to r-), and if the series-connected transistors are connected in parallel, the dummy row line DWL changes from °゛O'' to 11# level when the row line wr is selected. , this dummy row i1 DWT.

Precharging can be stopped by each node B-E signal,
All you have to do is drive a sense amplifier.

Of course, if the falling edge of the dummy row line y is input to the inverter, a signal having the same phase as the node BE signal can be obtained, and if this is used, the circuit described above can be used as is. Furthermore, in this embodiment, the precharge signals PC1 to PCn are determined based on the number of output buffer circuits, but if this is further divided and the number of output buffer circuits is made equal to or greater than the number of output buffer circuits, the peak current can be further reduced. Of course, if you don't need to worry about the peak current so much, you can reduce the number of output buffers.

As explained above in 1-1, according to the present invention, the precharge time or the sense amplifier voltage is adjusted for each column line corresponding to the output buffer circuit according to the potential change determined by the position from the row decoder on the selected row line. Since the operation time is set, it is possible to prevent multiple bits of data from being output at the same time and output them in a staggered manner, thereby reducing instantaneous peak current and power supply noise, resulting in stable operation. Semiconductor memories that can operate in a variety of ways can be readily available.

[Brief explanation of drawings]

FIGS. 1 and 2 are circuit configuration diagrams of a conventional semiconductor memory,
Figure 3 is a configuration diagram of the precharge circuit in Figures 1 and 2;
4 to 15 show a semiconductor memory according to an embodiment of the present invention, FIG. 4 is a circuit configuration diagram of the semiconductor memory, and FIGS. 5 and 6 are dummy rows of the memory of FIG. 4. Figure 7 is a diagram of the waveform of the line and precharge signal, and Figure 7 is a block diagram of the address buffer circuit used in the memory 25 of Figure 4.
The figure is a block diagram of an address change detection circuit used in the memory of FIG. 4, FIG. 9 is a block diagram of a grid charge signal generation delay circuit, and FIG. 10 is a block diagram of a grid charge signal generation circuit.
11 is a time chart for explaining the operation of the semiconductor memory in FIG. 4, FIG. 12 is a configuration diagram of the address buffer circuit for dummy row decoder, and FIG. 13 is a diagram of the delay chip operation signal generation circuit in FIG. 12. 14 is a general circuit diagram of the row decoder in Figure 4, Figure 15 is a circuit diagram of the dummy row decoder in Figure 4, and Figure 16 is the memory in Figure 4 in the tick operation state. FIG. 17 is a configuration diagram showing an example of a sense amplifier circuit to which the present invention is applied. 1...Memory cell, 2...Column line precharge circuit,
3... Row decoder, 6... Sense amplifier, 7...
Data input/output circuit (output buffer circuit), 8 to 11...
・Noah gate, 12-14...Delay circuit, WL...
Row line, DwL...Dummy row line, Qn, Qn-column line, 26-PC...Precharge signal. -27-

Claims (5)

[Claims] (1) A plurality of row lines, a row decoder that selects the row line in response to an address input, a plurality of memory cells that are driven reciprocally by the row lines and stores data, and read data from the memory cells. a plurality of column lines for receiving the data, a precharging means for precharging each of the column lines, a plurality of sense amplifiers for detecting the data on the column lines, and a device for outputting the data detected by the sense amplifiers. A plurality of output buffer circuits, and in order to output data to the plurality of output buffer circuits, a precharging time of the precharging means is set according to a potential change determined by a position from a row decoder on a selected row line. A semiconductor memory characterized by comprising a precharge time setting means. (2) The semiconductor memory according to claim 1, wherein the precharge time setting means sets the precharge time for each column line corresponding to the output buffer circuit. (3) The precharge time setting means includes a circuit that starts a precharge operation in synchronization with a change in the address input, and a circuit that detects a change in potential of the selected row line and ends the precharge operation. A semiconductor memory according to claim 1, characterized in that the semiconductor memory comprises: (4) The precharge time setting means includes a delay circuit that shifts the start of the precharge operation for each column line by II order in synchronization with a change in the address input. 2. Semiconductor memory according to item 2. (5) The precharge time setting means includes an address buffer circuit that receives an address input and generates a plurality of signals having a predetermined timing difference, and an address buffer circuit that receives an output signal of the address buffer circuit and detects a change in the address input. an address change detection circuit that generates a precharge set signal for generating a precharge signal; a delayed chip operation signal generation circuit that receives a chip operation signal and generates a delayed chip operation signal that is delayed by a predetermined timing; and the address buffer circuit. An address buffer output signal and an inverted address buffer output signal are derived from the address buffer circuit, and when the chip operation signal input is "1", the input from the address buffer circuit is delayed by a predetermined timing to produce a delayed address buffer output signal and a delayed inverted address. The signals from the address buffer circuit whose switching is controlled by the buffer output signal are respectively led out to two output terminals, and the signals led from the delay chip operation signal generation circuit are connected between the two output terminals f-). A circuit to which the controlled f-) circuit is connected, a dummy row line decoder to which signals from two output terminals of this circuit are guided, and a dummy row line decoder driven by the output of this decoder and included in the plurality of row lines. Patent Claim (6): A dummy row line, and a circuit that detects a predetermined point potential on the dummy row line and controls the end timing of the precharge operation. a row decoder that selects a row line; a plurality of memory cells that are selectively driven by the row lines and store data; a plurality of column lines that receive data read from the memory cells; a plurality of sense amplifiers for detecting data on the column line; a plurality of output parallel circuits for outputting data detected by the sense amplifier; 1. A semiconductor memory comprising: means for sequentially setting the sense amplifiers to an operating state in accordance with a potential change determined by a position.