JPS5824820B2 - Hiyoji Seigiyohoushiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display control method in, for example, an electronic desktop calculator.

Conventionally, the drive control of the display part of an electronic desktop calculator is as follows:
Dynamic (time division) drive systems are commonly used.

However, when dynamic drive is adopted for drive control of the display section, the duty and the withstand voltage of the display drive elements forming the drive circuit must be carefully considered.

That is, if a bright display state is to be obtained using the same display element, the duty must be increased or the withstand voltage of the display driving element must be increased to increase the voltage.

Conventionally, however, the display drive circuit has been implemented as an LSI, and the withstand voltage of the display drive element is closely related to the size of the chip area in which the circuit is implemented as an LSI.

That is, when trying to increase the withstand voltage of a display drive circuit in order to increase display brightness, the chip area must be increased, which reduces the degree of integration when integrated into an LSI, causing problems in miniaturization and cost.

The present invention has been made in view of the above points, and it is possible to increase the display brightness without increasing the withstand voltage of the display drive circuit, and it is useful for improving the degree of integration of LSI, thereby reducing the size and cost of computers. The object of the present invention is to provide a display control method that is extremely advantageous in this respect.

In other words, in electronic desktop calculators, one of the calculation registers usually doubles as a display register, and the configuration of the calculation register generally includes a data storage section, a counter section used during calculations, a calculation flag section, and a decimal point counter section. It consists of arithmetic control data storage sections such as, etc., and the data of each section is stored in the above-mentioned register while being cyclically held.

What is actually displayed in the display cycle is the contents of the display data storage section, and there is no need to display the contents of the other arithmetic control data storage sections even if they are read, so they are not displayed at that timing. Not yet.

The present invention improves the duty cycle in the display cycle and increases the display brightness by displaying display data even at the timing when information unnecessary for display is read from the arithmetic register.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 also serves as a display register. For example, 15
The first to third storage units 118 to 11 are digit calculation registers.
It consists of G.

The first to third storage units 113 to 11C each have 5
It has a digit configuration, and constitutes a 15-digit shift register in total.

The first storage section 11a stores, for example, count data, calculation flags, and decimal point data used in calculations, and the second and third storage sections 11b and 11C store display data.

The contents of the arithmetic register 11 are the bit clock pulses φ1. Sequential information 1 by φ2
The bits are shifted and cyclically stored, and the outputs of the respective storage sections 118-11C are input to the first input terminals of AND circuits 128-12C.

Then, the outputs of the AND circuits 12a to 12C are sent to the shift register 14 via the OR circuit 13 as a clock pulse φ.
The buffer register 15 is read sequentially in synchronization with
will be forwarded to.

The data stored in this buffer register 15 is sent to each digit segment of a display section (not shown) via a segment decoder 16.

Further, 17 is a control counter that controls the output of the arithmetic register 11, and includes, for example, a delayed flip-flop 18a,
It is mainly composed of 18b.

The flip-flops 18a and 18b are an AND circuit 1
The output of the flip-flop 18a is synchronized with the clock pulse φ shown in FIG. It is applied to the input terminal of the flip-flop 18b via the OR circuit 21.

Further, the output of the flip-flop 18b is applied to the NOR circuit 20, and is also applied to its own input terminal via the NOR circuit 22 and the OR circuit 21.

Furthermore, the NOR circuit 22 is supplied with the output of a delayed flip-flop 23 that controls the control counter 17.

This flip-flop 23 operates in synchronization with a clock pulse suit outputted every word time as shown in FIGS. added to.

Thus, the output of the control counter 17 configured as described above, that is, the output of the flip-flop 18a, is applied to the second input terminals of the AND circuits 12b and 12G, and is also applied to the second input terminal of the AND circuit 12a via the inverter 25. 2 is added to the input terminal.

On the other hand, the output of the flip-flop 18b is
2b and the third input terminal of the AND circuit 12C via the inverter 26. In addition, 30 is a digit control unit for a display unit having, for example, a 10-digit display element, and is, for example, a digit control unit in quinary notation. counter 31,
AND circuits 32□ to 32□.

, this AND circuit 32□=32,o consists of a delayed flip-flop 33 that performs gate control.

The quinary counter 31 receives a digit clock pulse φ.

is counted and outputs signals C1 to C6.The output signal of this counter 31 is sent to an AND circuit 32. ~32,
.

is applied to one input end of On the other hand, the flip-flop 33 has an input terminal supplied with the output of the flip-flop 18b, and receives a digit clock pulse φ.

The output is sent to the AND circuit 32.
,~32. AND circuits 326-32, through impark 34.

is applied to the other input terminal of And the above-mentioned AND circuits 32, to 32,.

Signals P1 to pto outputted from the digits become digit signals for selecting each digit of the display section.

Further, the output signal C5 of the counter 31 is applied to the AND circuit 19 together with the digit clock pulse φ9,
The output of this AND circuit 19 becomes the clock pulse φ.

Next, the present invention configured as described above will be explained in detail.

The arithmetic register 11 receives bit clock pulses φ1. The contents of each bit of each digit are sequentially output in synchronization with φ2.

The data read from this arithmetic register 11 is returned to its own input side, and the bit clock pulse φ1. Shift circulation is performed in synchronization with φ2.

On the other hand, the control counter 17 operates in synchronization with the clock pulse φ outputted from the AND circuit 19, and its operation is controlled by the output of the flop flip 23.

Furthermore, the quinary counter 31 receives a digit clock pulse φ
.

count signal 01 as shown in Figure 3.
~C5 are output sequentially.

Now, for example, as shown in FIG. 4, the output power of the flip-flop 18a of the control counter 17 becomes "Oj", the output of the flip-flop 18b becomes "1", and the output of the flip-flop 23 becomes "1". When the calculation cycle ends and the display cycle begins, the output of the flip-flop 18a is 0'' and the output of the inverter 25 is !
1191 and the gate of the AND circuit 12a is opened, so that the contents of the first digit of the arithmetic register 11 are transferred to the shift register 14 via the AND circuit 12a/A and the OR circuit 13 at the timing of the digit pulse D1 by the bit clock pulse φ1. are read sequentially by

Each digit of the arithmetic register 11 consists of 4 bits, and the most significant 3 bits are serially read into the shift register 14, and when the next 4th bit is output from the OR circuit 13, it is buffered together with the contents of the shift register 14. The data are read into the register 15 in parallel by the digit clock pulse φ9.

When the contents of the first digit are read into this buffer register 15, a segment signal is outputted from the segment decoder 16 according to this contents and sent to the display section.

A segment signal is output in accordance with the data read out from the arithmetic register 11 in this manner, and the data read out from the arithmetic register 11 corresponds to the digit clock pulse φ.

Since it is read into the buffer register 15 in synchronization with 1
There will be a delay of several orders of magnitude.

Also, in synchronization with the digit pulse D1, the quinary counter 3
Although the signal C1 is output from 1, no display is performed because no segment signal has been output yet as described above at this point.

On the other hand, when the output of the flip-flop 18b of the control counter 17 becomes '1', this '1' signal is sent to the flip-flop 33, and the next digit clock pulse φ
.

The flip-flop 33 is set by the AND circuits 32□ to 32. Open the gate.

Therefore, from the quinary count 31, the next digit pulse D2
When the signal C2 synchronized with is output, the AND circuit 321
A digit signal P1 designating the first digit display tube of a display section (not shown) is outputted from and sent to the display section.

At the time when this digit signal P1 is output, the segment signal for the first digit data read from the arithmetic register 11 is sent to the display section.
To the digits.

The contents of the first digit of the calculation register 11 are displayed.

Thereafter, the contents of the arithmetic register 11 are read up to the fifth digit in the same manner, and when the count signal C6 is output from the quinary counter 31, the next digit clock pulse φ is generated.

At the time when φ is applied, the AND circuit 19 outputs a clock pulse φ as shown in FIG.

The control counter 17 is controlled by this clock pulse φ.
The outputs of the flip-flops 18a and 18b both become '0'' at the timing of the digit pulse D6 as shown in FIG.
becomes.

When the output of the flip-flop 18b becomes 0'', the output of the flip-flop 33 becomes 0'' by the next clock pulse φ9.
The output of the flip-flop 33 becomes "0" at the timing of the digit pulse D7.

Therefore, the gates of AND circuits 32□-325 are closed, and the gates of AND circuits 326-321o are opened.

Therefore, from now on, the count signals C2 to C from the quinary counter 31
6. When C1 is output, the AND circuit 326 ~
Digit signals P6 to PIO are output from 321o,
Data is displayed from the 6th digit to the 10th digit of the display section.

At this time, when the count signal C6 is output from the quinary counter 31, the clock pulse φ6 and the clock pulse φe are output from the AND circuit 19 in synchronization with the digit clock pulse φ.

When the clock pulse φ□ is applied when the outputs of the flip-flops 18a and 18b of the control counter 17 are both 0" and the output of the flip-flop 23 is 1", the "1" signal on the flip-flop 18a side is read. It will be done.

As a result, at the timing when the digit pulse I)tt is applied, the output of the flip-flop 18a is
``The flip-flop 18b becomes nO?l, the gate of the AND circuit 12C opens, and the AND circuits 12a and 12b
gate closes.

At this point, the second storage section 11 of the calculation register 11 is first
The contents of the 6th to 10th digits stored in b are the 1st
The contents of the sixth digit are read out via the AND circuit 12c.

Furthermore, at this point, the output of the flip-flop 33 is 0"
The output of the inverter 34 becomes 1'', and the gates of the AND circuits 326 to 321o are opened.

Therefore, AND circuits 326 to 32, according to the counting operation of the quinary counter 31.

Digit signals P6 to P1o are outputted from the digits, and the 6th to 10th digits are displayed on the display section.

That is, first storage section 11a of calculation register 11
Since there is no need to display the arithmetic control data stored in the sixth
The 10th to 10th digits are displayed.

When the display for one word time is thus completed, a 60'' signal is read into the flip-flop 23 by the clock pulse φ.

In this state, the contents of the first to tenth digits in the arithmetic register 11 are read out and displayed in the same way as in the previous case, that is, as shown in FIG.

However, in this case, when the quinary counter 31 outputs the count signal C6 when the ninth digit is displayed, the AND circuit 19 outputs the clock pulse φ in synchronization with the digit clock pulse φ.

At this point, as shown in FIG. 4, the outputs of the flip-flops 18a and 18b of the control counter 17 as well as the flip-flop 24 are all +10 ff+, and in this state, when 70 pulses φ are applied, the outputs of the flip-flops isa and isb are Both "'1" and "1" are read.

Therefore, when the next digit pulse D1 is applied, the flip-flop 18a.

Both outputs of 18b become 1''', opening the gate of AND circuit 12b and closing the gates of AND circuits 12a and 12C.

At this point, the contents of the first to fifth digits have been shifted to the second storage section 11b of the arithmetic register 11, so the contents of the first to fifth digits are read out via the AND circuit 12b. .

At this time, the output of the flip-flop 18b is applied to the flip-flop 33 as a digit clock pulse φ.

Since it is read in synchronization with
gate is opened and digit signals P1 to P5 are output.

Therefore, the first to fifth digits are displayed at the next timing when the digit pulses DIl to D15 are applied.

In the above embodiment, the state of the flip-flop 18a is "
0'', the state of flip-flop 18b is 11191, the state of flip-flop 33 is 1", flip-flop 2
Although the explanation has been given using an example in which the calculation cycle ends when 3 is 1'' and the display cycle begins, the present invention is not limited to this. The flip-flop 18b may be 1", the flip-flop 33 may be 0", and the flip-flop 23 may be 0'0.Additionally, the present invention allows the flip-flop group to be displayed from an arithmetic cycle in any state. Even if the display enters a full cycle, after repeating several cycles, it will become a cycle as shown in FIG. 4, and the predetermined display cycle will continue.

Furthermore, the present invention is not limited to the above embodiments,
Of course, various changes can be made without departing from the spirit of the invention.

As described above, in the present invention, the display operation is performed even when data unnecessary for display is read from the arithmetic register 11, so the duty cycle in the display cycle can be improved, and therefore the display driving circuit can be Display brightness can be increased without increasing breakdown voltage, and a display control method that is extremely advantageous in terms of size reduction and cost can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment, and FIG. 4 is a diagram explaining the operation of the embodiment. . 11... Arithmetic register, 15... Bumper register, 17... Ternary counter, 30...
... Digit control section.

Claims (1)

[Claims] 1. An arithmetic register that has an arithmetic control data storage section and a display data storage section and holds data in circulation, and display data that is read out from the output of the arithmetic register at the optical display data read timing and is displayed in a time-division manner by sequentially selecting the display data. and the means to
A display control characterized by comprising means for dividing the arithmetic register into a plurality of parts and extracting the display data that is circulated and held in the register from the dividing point at the arithmetic control data readout timing and displaying the data in a time-divisional manner. method.