JPS5824748B2 - Clock with battery life warning display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a battery life warning display method for an electronic watch.

The biggest drawback of electronic watches is that the battery life is finite and the user cannot know in advance when the life will end. The voltage detection circuit 1 detects a voltage drop.

When a drop in battery voltage is detected, the display state of the time display means is changed (this is a so-called battery life warning display method that warns that the battery life is nearing the end of its life. Yes, follow.

In the current battery life warning display method 1, some batteries last for about a week after the warning display, while others run out in one day, so even though the warning display is displayed, the batteries end up being used up. This resulted in the clock stopping for one hour until it was replaced, so a system for displaying battery life warnings with more leeway was desired.

SUMMARY OF THE INVENTION In order to meet the above-mentioned demand, it is an object of the present invention to provide a watch with a battery life warning display having a sufficient margin.

To achieve the above object, the present invention provides sampling of the battery voltage detection circuit at relatively heavy loads, relatively light loads, and I/O.
Here, each sampling 1 of the battery voltage detection circuit is performed.
The feature is that a different battery life warning display is displayed for each operation.

The present invention will be described in detail below with reference to FIG.

FIG. 1 is a block diagram of an electronic timepiece according to the first aspect of the present invention, and FIG. 2 shows a waveform diagram of each part in FIG.

In Fig. 1, 1 is a crystal resonator having a natural frequency of 32768 Hz, 2 is an oscillation circuit, and 3 is a frequency dividing circuit, and the frequency dividing circuit 3 is a 16-second frequency divider]. The oscillation frequency is divided by one signal having a period of 2 seconds.

Reference numeral 4 denotes a drive waveform shaping circuit, which inputs the output signals from each frequency divider of the frequency dividing circuit 3 and a control signal from a battery voltage detection circuit described later, and outputs the driver 5 and the driver 5 connected to the output terminals 01Q21. A pulse motor 7 is driven via a terminal 01, and a hand movement display device 8 (which displays the time) generates a heavy load sampling signal, which will be described later, from a terminal 01.

Note that 9, 10° and 11 are the hour hand, minute hand and second hand, respectively.

12 is a battery for power supply, 13 is a battery voltage detection circuit for detecting a voltage drop of the battery 12, and two data type flipflops (hereinafter abbreviated as DFF) 14.15
and P channel MOS transistors 16 and 1, and the drain terminal of the MOS transistor 16 is connected to the D
The data terminals D1 of the FFI 4 and the DFF 15 are connected to the Vdd terminal of the battery 12 via the level adjustment resistor 17, and the source terminal of the MOS transistor 16 is connected to the Vss terminal of the battery 12. ing.

Reference numeral 18 denotes a sampling pulse shaping circuit, which generates a light load sampling signal z2 from each output terminal F9 and F15 of the frequency dividing circuit 3.

Each sampling signal is connected to the sampling terminal z1 of DFFl4, and to the sampling terminal 2 of DFFl5, and to the gate terminal 1 of the MOS transistor 16 via an OR gate 19. has been done.

Further, the output terminal Q1 of DFFl4 is connected to the control terminal C11 of the driving waveform shaping circuit 4, and further connected to the control terminal C11 of the driving waveform shaping circuit 4.
The output terminal Q2 is connected to the control terminal C21 via an AND gate 20.

The operation of the battery voltage detection circuit 13 in the above configuration 1 will be explained.

When the light load sampling pulse z2 generated by the sampling pulse shaping circuit 18 at a timing when the heavy load pulse motor 7 is not driven is applied to the gate terminal 1 of the MOS transistor 16 via the OR gate 19, the light load sampling pulse z2 is simultaneously applied to the gate terminal 1 of the MOS transistor 16. A signal is applied to the sampling terminal of DFF15.

At this time, if the voltage of the battery 12 is high, the MOS transistor 16 is sufficiently turned on by the sampling pulse F2, so the data of the DFF15 connected to the dividing point between the MOS transistor 16 and the level adjustment resistor 17 is The level at the terminal becomes logic ``0'', and therefore the output terminal Q2 remains at the logic ``0'' level.

Then, as the life of the battery 12 approaches and the voltage decreases, the sampling pulse S26 (MOS transistor 16 cannot be sufficiently turned on) and D
Since the level of the data terminal of FFl5 becomes logic "1", the logic "1" level of the output terminal Q2 is written as a battery life warning signal.

Similarly, it is time to drive the pulse motor 7.

The result of voltage detection based on the heavy load sampling pulse z11 generated during the sampling is written to the output terminal Qt+ of the DFIJ4.

The voltage level at which the battery voltage detection circuit 13 operates can be set to an arbitrary value by adjusting the level adjustment resistor 17.

Therefore, in the battery voltage detection circuit 13, only one operation level is set using one level adjustment resistor 17], so when the battery 12 approaches the end of its life and its internal resistance increases, a heavy load of 1 Since a voltage drop occurs, first the heavy load sampling pulse is
A dual detection structure is adopted in which a battery life warning signal is written to the output terminal Q11 of Fl4, and when the battery voltage drops by one, an electronic life warning signal is also written to the output terminal Q21 of DFF15.

Next, the operation of the electronic timepiece will be explained based on the waveforms shown in FIG. 1 and FIG. 1.

As shown in FIG. 2A, the 32768Hz reference signal oscillated by the oscillation circuit 21 is frequency-divided by the frequency divider circuit 31, and as shown in FIG.
This is 64Hz, and the F15 terminal is 1Hz.

[F16 terminal] This generates a signal of 0.5 Hz, etc.

Then, the drive waveform shaping circuit 4 receives the signal from the frequency dividing circuit 3, and generates a pulse motor drive signal of a different waveform between the output terminals 01.0□ according to the condition 1 of the control terminals C1 and C2, Driving the pulse motor 7 (hand movement display device 8) At the same time as displaying the time, the motor drive signal z1 generated at the output terminal 011 as shown in FIG. 13 samplings were conducted.

The sampling pulse shaping circuit 18 also includes a frequency dividing circuit 3.
The light load sampling pulse z2 shown in FIG. 2g (shown in FIG.

Next, the operation of the drive waveform shaping circuit 4 will be explained.

First, during normal operation when the voltage of the battery 12 is high, DFF14 and DFF1 constituting the battery voltage detection circuit 13 are
5, the control terminals C1 and C2 of the drive waveform shaping circuit 4 are at logic t1011, and in this state 1, the output terminals 01, 0□
In between, alternating pulses at 1 second intervals as shown in FIG. 2 are generated as a pulse motor drive signal, and the second hand 11 of the time display device 8 is moved at a constant speed at a 1 second cycle.

Next, when battery 12 is nearing the end of its life, heavy load sampling 1
When the DFFl41 battery life warning signal is written from this, only the control terminal C1 becomes logic "1" and in this state, a pulse motor drive signal as shown in Fig. 2i (I) is generated and the hand movement display device The second hand 11 of No. 8 is moved in two steps at a two-second cycle, and a first warning of battery life is given.

Next, when the battery 12 approaches its lifespan by 1, the DFF 14
When one battery life warning signal is written, the control terminal C1
, C2 are both 1 logic ej I II, and this state I
In this case, a pulse motor drive signal as shown in FIG. It is something.

FIG. 3 shows a battery voltage detection circuit having operation level setting means, and the same numbers as in FIG. 1 indicate the same members.

In FIG. 3, ST is a set terminal provided for setting the operating level of the battery voltage detection circuit 13, and 30 is a set terminal provided for the clock ICI.
(16384Hz) AND gate 31.
32 is an OR gate.

In FIG. 3, when a logic ``1'' level voltage is applied to the set terminal ST, the gate terminal of the MOS transistor 16 is always set to 1 sampling state via the OR gate 31, and the AND gate 30 is Turning on 1
This higher speed sampling pulse, but OR gate 3
Since the voltage is supplied to the sampling terminal of the DFF 14 via the voltage input terminal 2, the battery voltage detection circuit 13 is in a continuous sampling state.

Therefore, the operating level of the battery voltage detection circuit 13 is set.) This is the power supply terminal VDD of the clock IC.

■Between SS and between set terminal ST and power supply terminal VB2 1
This is the voltage ES (1.4V to 1.4V) at the level you want to operate.
5V) is applied to the output terminal 01 of the drive waveform shaping circuit 4,
Adjust the level adjustment resistor 17 while monitoring 0□,
The resistance value l when the battery life warning signal shown in FIG. 2 11 is obtained at the output terminals 01 and 02 is the level adjustment resistor 1.
Set 7.

As described above, in the present invention, the battery life warning is performed in stages, so that when the user is in the first battery life warning state as described above, the user must purchase a replacement battery, When the first warning state I occurs, it becomes possible to replace the battery, and it is possible to provide a battery life warning with sufficient margin to one user.

Furthermore, since the present invention performs stepwise detection of battery voltage by changing the load current during sampling, the essential (
Only this one detection circuit is required, and only one external resistor is required for level adjustment, so compared to the conventional battery voltage detection method, external installation requires an increase in the number of parts and assembly man-hours. There isn't.

Furthermore, in this embodiment, the case of a watch with a hand movement display is shown, but the present invention is not limited to this, and it is also possible to use a digital display watch with a single liquid crystal display device. If the heavy load sampling pulse,
When the lighting lamp is turned on (this method is generated), and in the case of a digital display using a light emitting diode, when the display is turned on (this method generates a heavy load sampling pulse,
In the case of a digital display watch, it is sufficient to generate a heavy sampling pulse when switching the display.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a hand movement display timepiece according to the present invention, Fig. 2 is a waveform diagram of each part of Fig. 1 I, and Fig. 3 is a circuit diagram of a battery voltage detection section according to another embodiment. show. 2... Oscillation circuit, 3... Frequency dividing circuit, 4
... Drive waveform shaping circuit, 7 ... Pulse motor, 8 ... Hand movement display device, 12 ...
・Battery, 13... Current voltage detection direction 1, 16.
・・・～・”+(・,)Strans・dista, 17・・・・
...Level adjustment resistor 1;″l;.

Claims (1)

[Claims] 1. In an electronic timepiece having a reference oscillator, an electronic circuit, a time display means, a battery, a voltage detection circuit for detecting a voltage drop in the battery, and a sampling means for intermittently activating the battery voltage detection circuit, the sample link The means is characterized in that sampling is performed under relatively heavy loads and relatively light loads, and a different battery life warning display is displayed for each sampling (operation of the voltage detection circuit for each sampling). Clock with warning display.