JPS58225463A - Access processing system - Google Patents

Abstract

PURPOSE:To avoid generation of an access request of a long access processing time, by giving preferable conditions with the second decision of priority to the access request of a channel processor CHP which lost its priority after once obtaining it. CONSTITUTION:The priority is decided by a CHP priority deciding circuit 13 for the 1st stage of a CHP access request. The CHP access request selected by the circuit 13 takes part in the decision of priority for the 2nd stage through a primary priority deciding circuit 16. If this CHP access request is not selected with the 2nd stage process, a high priority is secured for the request. Then this request is immediately selected when the 2nd stage is reset to the 1st stage.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an access processing method in a data processing system, particularly when determining the priority of access requests.
For access requests that have been selected in advance and cannot be processed for some reason during the processing process, the request is made to participate in determining the priority order again, and at that time, a high priority is given to the access request The present invention relates to an access processing method that prevents long access requests from occurring.

TECHNICAL BACKGROUND FIG. 1 shows an example of the configuration of a data processing system to which the present invention is applied. In the same figure, 1.2 is the two central processing units 1icPUo, CPUuJ), 3
．． 4, four channel processing devices CHPo to CHPs are omitted. Further, 5 is a memory control unit MCU of a nocturnal line system, and 6 is a memory unit MSU.

7 is, for example, a set-associative type rough memory BS, 8 is its directory, and 9 is a priority determining circuit.

MCU is CP Uo + CP Us + CHPo
~Accepts access requests to the MSU from each CHPm at any time, and performs storage control using a buffer method using the directory and BS.Also, when accepting multiple access requests at the same time, the priority A decision circuit selects one according to a certain priority decision logic.
Select one access request and execute it.

C as a priority determination method for each access request.
The priority between HP and CPU is that CHP is higher <L, C
The priority between the PU and CPU is determined according to the priority determination logic determined by the device, and some of them have higher priority than those from loopback. The outline and one problem will be explained below.

When the MCU receives access requests from multiple CHPs and multiple CPUs, it determines their priority and sequentially processes the selected access requests in a pipeline.
The method for determining priorities in the MCU is to first
For the access requests, first priority determination is performed between CH2 to select one access request, and then the selected CHP access request and the access requests of multiple CPUs are re-pipelined. A second priority determination is made between the loopback access requests for use, one access request is selected, and the selected access request is sequentially input into the pipeline. Execute processing.

At this time, the CHP access request selected in the first priority determination has the priority obtained as invalid (NULL) as follows.
IFY).

(In the second priority determination stage, when an access request from loopback collides with an access request from loopback, the loopback access request must be given priority in order to use the pipeline again, and CHP access Since both requests and requests are set to have a high priority, CHP access cannot be given priority, and the priority obtained in the first priority determination is invalidated.

(In the second priority order determination, the bank of the backup memory BS used by CHP access is
When the bank is busy due to other accesses being processed by U, or when a control condition exists that prohibits CHP access, the priority obtained in the first priority determination is invalid. Become.

(1) CH that obtained priority in the second priority order determination
After the P access is input to the pipeline, when there is no data to be accessed in the backup memory BS (buffer NOT FOUND), the MC
If there are the same number of accesses to the buffer NOTFOUND being processed by U as the number of main memory access ports and the main memory is being accessed, the main memory access port becomes busy. After the timing of the pipeline that identified this busy status, subsequent pipeline processing is disabled (NULLIFY), and the CHP access is
Let's start over again from determining the first priority.

(4) *In the set associative type buffer memory BS, the set conflict detection function
When it turns out that the set address of the buffer memory BS used by the preceding access is the same set address as the CHP access, a set match occurs.
Access to the same set, that is, CHP access, is prohibited, subsequent pipeline processing is disabled, and that CHP
As for access, repeat the steps 9 again starting from the first priority order determination.

If the invalidated CHP access request as described above conflicts with another CHP access request when the first priority order is determined again, it would normally be processed first. There is a possibility that the CHP access request that should have been made will be lost due to a later CEP access.

Therefore, a problem arises in that the access processing time for CHP access requests that should originally have been processed in advance becomes even longer due to the effect that the CHP access requests that come after the overtaking are processed first by the MCU.

In addition, as another method, CHP accesses whose priority rights were invalidated at the second priority determination stage are given priority at the second priority determination stage, instead of being reset from the first priority determination stage. There is a way to keep it until you can get it. In this case, hardware is required to hold the access request whose priority has been invalidated, and the second CHP access request is
This requires hardware for a control circuit for allowing waiting CHP accesses to participate in the second priority determination.

Object and Structure of the Invention An object of the present invention is to increase the priority level when a CHP access request whose priority has been invalidated once participates in the first priority determination process, and to In order to avoid losing to access requests, the access processing time for CHP access requests that have been prioritized and invalidated is reduced.
The goal is to shorten it as much as possible.

The present invention has a configuration for this purpose, in which an access processing device that processes access requests from a plurality of access request devices by determining priorities, simultaneously receives a plurality of access requests from the plurality of access request devices. When the access request is assigned, the priority order is determined, one access request is selected from among them, and processing is started by giving priority. If it becomes impossible to continue the processing midway, the access request is A method is provided to invalidate the priority right to return the access request to a state in which it is accepted, and then reset the determination of the priority order, and to participate in the determination of the next priority order for the access request whose priority right has been invalidated once. When access requests are requested, the access requests are given a high priority and processed in competition with other access requests at that time.

Examples of the invention The present invention will be explained in detail below based on examples.

FIG. 2 shows the configuration of an embodiment of the memory control device MCH to which the present invention is applied. Note that, for convenience, only circuit portions related to the present invention are shown in the figure.

In the same figure, 11 is a CHP boat, CHPo~
'Accept address and control signals from CHPs. Reference numeral 12 denotes a CHP selector, which is controlled by a CHP priority determining circuit (described later). 13 is a CHP priority determination circuit υ, which first selects one REQ for the access request signal REQ from CHPo=CHPs,
The RBQ signal of the selected channel (denoted as SCH) is further output for priority determination with other access requesting devices. 13α is a status display table provided for each CHP, which displays the access request processing status of each CHP, the boat busy status, and the like.

Note that details will be described later.

14 is the CPU boat, CPUo + CPUt
1 selected channel SCH and from a loopback control circuit LB (not shown). Reference numeral 15 is a CPU selector, which is controlled by a main priority determining circuit, which will be described later.

16 is the main priority determining circuit j5, CPU selector 1
5 input target CP Uo = CP Ul p SC
For HIL B, determine the priority of REQ signals from them. 16α is a flag indicating the priority order among CPUs. The signal POK output from circuit 16 to circuit 13 indicates that SCH has not been selected.

17 is a pipeline (F), showing only the stages of Tx*Tz+Ts. TIV I T2V * TsV is a valid signal of each stage.

Reference numeral 18 denotes a circuit having the aforementioned set conflict detection function. Reference numeral 19 denotes an invalidation control circuit that detects and invalidates a condition that makes it impossible to process an access request that has started execution. 20 is a prohibition gate, and the above circuits 18 and 19
When instructing that processing cannot be continued (NULLIFY), the valid signal is inverted and an execution impossible signal EXEC is output.

As the basic ranking determination logic of the CHP priority determination circuit 13, any suitable logic such as boat number order, prespecified order, cyclic change method, etc. can be used. On the contrary,
A means is added to raise the priority in re-priority determination while once obtaining the priority. Furthermore, the priority determination logic of the main priority determination circuit 16 is such that CPU<S CH<
The two methods are to follow the LB ranking, and to follow the display of flag 16α for CPUs.

Next, regarding the control method of priority determination processing for priority invalid access requests in the CHP priority determination circuit 13, which is characterized by the present invention, FIGS. This will be explained in detail with reference to FIG.

FIG. 3 shows an example of the configuration of status display cubes 13α provided for managing access requests from each CHP. The first bit indicates "1#" (REQUEST) when an access request is issued.The second bit indicates that one access request has been accepted and the priority determination process and pipeline process are in progress. Indicates that boat 11 is busy (PORT BUSY
). The 3rd to 6th bits are status codes that indicate the control status during priority determination processing and pipeline processing in the boat for accepted access requests (ACCEPTED O, 1, 2, 3). .

FIG. 4 is a state transition diagram of the state display table 13G shown in FIG. 3), which consists of nine states in total.

First, when [ooooooo3 is in the reset state and the access request RBQ is accepted, the process moves to [1ooooo].

ζThe first stage of priority determination processing is performed in the CHP priority determination circuit 13, and when the priority is acquired here, that is, when the access request is selected (p)[n
onol, on the other hand, when not selected, O has [tx
Waits until it is selected in the oooool state.

CHP selected by the CHP priority determination circuit 13
The access request then participates in the second stage of priority determination processing in the main priority determination circuit 16, and when selected here (CPOK), the access request moves to [1101011] and is executed (CPOK).
EXEC), it moves to [100100].

If the access request REQ for the finished cutting machine is accepted, the process returns to [1ooooOI. On the other hand, if there is no next access request (REQ), the process returns to [Ooo ooo, l.

However, when the CHP access request is not selected in the second stage of processing (POI, [1110117
, where it is given high priority. Therefore, it is selected from the first stage (P(Higk)), and [1111
11,1 and undergoes the second stage processing again. If it is selected here (POK), the previous [110101,1
The transfer will be executed. However, if it is not selected (
(Purchase), [111011.
K) Repeat.

On the other hand, when entering execution CEXEC from [110101), if the CHP access request becomes unexecutable (EXEC), it is moved to [111010] and given a high priority in the first stage (P (HIGH)). to make a selection, and move to the second step [111111'l]. The following is the same as the previous case.

Also, if access requests from three or more CHPs are received at the same time,
If the access request exists in the CU and each access request cannot continue processing (NULLIFY), and a situation occurs in which the process repeats from the first stage priority determination and 9 corrections, two high priority There may be cases where access requests that have been given a priority (CP (HIGH)) compete with each other and one of them is not selected (P CHIGH)), but in the next cycle, a higher priority is given to the access request that was not selected. remains assigned (P(HIGH)), so it is selected (P(HIGH)) and undergoes the second stage processing again. The above state transitions are shown in Figure 3 (xno
Not selected from x (P(HIGH)) [11101
11 and [111011, not selected from l (
P(HIGH)) is shown when [1l10111 is busy.

In this way, after the second stage priority determination process,
Even if the priority is lost, it can be controlled so that it is selected immediately upon returning to the first stage.

FIG. 5 is a timing diagram of an operation example showing logical conditions for generating the state transition of the state display table shown in FIG. 4 and control contents based on the generated state display.

In Fig. 5, α indicates the four-cycle period, and E-El1
4 is the first clock period of the CHP. CPU Oyohi MC
The clock period of U is half of that between E and E. b is the FORT BUSY period, 0 is the MCU internal baud/busy period, d is the access request R
The period of existence of EQ, C is the period during which it has priority P or P(HIGH) given in the first stage, f to ! indicates the status display code. The solid line portion represents 11'', and the blank portion represents 10''.

Further, "No" indicates the processing result of the first stage CHP priority determining circuit 13, and SEL REQ indicates that REQ has been selected. My friend is the second stage main priority determination circuit 16
represents the processing result CPU-P. A dotted line indicates a negative result, and a solid line indicates a positive result. And l indicates the output signal POK or the presence or absence of POK, and the door indicates the operating state of the pipeline according to the result. n exemplarily indicates the correspondence with FIG. 4.

The zero marks in the figure represent input logic conditions for activating control operations, and the control operations activated as a result of vertically connecting and combining these conditions are indicated by arrows. For example, in ■, REQ="l', P="1".

Under the manual conditions of ACPTD O=”0” and ACPTD1=”O’, output [5ELREQ] and at the same time output ACPT
This shows that Dl and 2 are set to 11''.

In ■, 5ELREQ="1" and CPU-P="O"
, that is, a POK signal is generated from non-selection in the second stage, and a status code [10111 is generated from POK and the status code [onol]. And in ■, it is impossible to execute at the Ts stage of the pie line■
This shows that a signal is generated and the status code is rewritten to [1010].

Effects of the Invention As described above, according to the present invention, a CHP access request that once acquired priority but lost priority due to some reason will be given priority over other CHP access requests in re-priority determination. By providing advantageous conditions, the chances of re-execution increase and the process can be made smoother.

[Brief explanation of drawings]

Figure 1 is a typical configuration side view of the data processing system, Figure 2
Fig. 3 is an explanatory diagram of the status display table, Fig. 4 is a state transition diagram of CHP priority determination control using the status display table, and Fig. It is a timing diagram of an example of operation. In the figure, 11 is a CHP boat, 12 is a CHP selector, 1
3 is a CHP priority determination circuit, 14 is a CPU boat, 1
5 is a CPU selector, 16 is a main priority determination circuit, 16
α is a flag indicating priority among CPUs, and 17 indicates a pipeline. Junior high school 10

Claims (1)

[Claims] In an access processing device that prioritizes and processes access requests from multiple access requesting devices, when accepting multiple access requests from the multiple access requesting devices at the same time, Determine the priority order, select one access request from among them, give priority and start processing, and if it becomes impossible to continue the process halfway, the priority of the access request is invalidated and access is granted. If the access request whose priority has been invalidated is to participate in determining the next priority, the priority An access processing method characterized in that processing is performed by increasing the number of access requests and competing with other access requests at that time.