JPS58224557A - Pulse defect phase detection circuit - Google Patents

Abstract

PURPOSE:To eliminate erroneous operation and erroneous inoperation even if the frequency of a used power source is largely varied by adding a simple logic circuit to the defect detector of an APPS of a narrow band double pulse output. CONSTITUTION:Only a main pulse is produced by an AND circuit 32-a from double pulses, and is set to the set signal of a flip-flop 31, and the main pulse of the phased delayed by 120 or 180 deg. from the previous signal is set to the reset signal of the flip-flop 31. The AND of the set signal of the flip-flop 31 and the output of an oscillator 33 is taken by the AND circuit 32-a, and the output is counted by a counter 34. A comparator 35 outputs a signal when the counted value of the counter 34 exceeds the prescribed value, and the signal is externally outputted through an output circuit 36.

Description

DETAILED DESCRIPTION OF THE INVENTION An object of the present invention is to easily increase the frequency of the power supply used by adding an AND circuit to the open-phase detection circuit of the narrow-width double pulse output APPS that has been used in the past. It is an object of the present invention to provide a pulse phase loss detection circuit that does not malfunction or malfunction even when the phase fluctuation occurs.

FIG. 1 shows a block diagram of a thyristor converter control circuit. Conventionally, a pulse phase loss detection circuit 2 has been connected to the APPS output circuit in order to monitor the output pulses of the APPS1, but it has the following drawbacks. There was a risk of death.

In other words, conventional pulse phase loss detection circuits measure the time interval from one pulse to the next pulse, and if the time interval is longer than a predetermined time (a constant value determined by a circuit constant), an abnormality (phase loss) is detected. A method was adopted in which the signal was output to the outside.

FIG. 2 shows a block diagram of a conventionally used pulse input phase detection circuit, and FIG. 3 shows an operation time chart of the circuit shown in FIG. 2.

Conventionally used pulse phase loss detection circuits are classified into analog and digital types, but their operating principles are the same.

In the analog method, a CR charging/discharging circuit is used, and when a pulse is applied to the input terminal, the capacitor is instantaneously discharged, and when the input signal is 00, the capacitor is charged with a time constant determined by the circuit constant. If charging and discharging are repeated cyclically and the input pulse has an open phase,
Stops discharging the capacitor and increases its terminal voltage,
A detection signal is output by making the comparator reference voltage VB larger than υ.

The digital method has the same principle as the analog method, but C
The only difference is that an oscillation circuit and a counter are used instead of the fL photodischarge circuit, and a digital comparator is used as a comparator.

APPS is used as a control device with a small fluctuation range of the toe stain source frequency.
When APPS was used, the detection function was sufficiently satisfied;
The fluctuation range of the power supply frequency is -60% to +5% of the rated value.
It will be about 0%. ), the output pulse interval of APPS changes widely, which may cause malfunction or malfunction depending on the setting of the comparison voltage (■8) in the analog system and the comparison data DsO value in the digital system. was there.

In addition, in the case of large voltage fluctuation, the above-mentioned comparison value Vs
, Da may not be able to satisfy the function no matter how selected.

In order to eliminate the above-mentioned drawbacks, the present invention eliminates the method of measuring pulse intervals and changes the circuit configuration so that open phase detection can be realized depending on the presence or absence of pulse signals.

FIG. 4 shows a part of the pulse open phase detection circuit of the present invention. The difference from the conventional method is that an AND circuit 32-a is added before the flip-flop 31 to select only the main pulse from a double pulse consisting of a main pulse and an auxiliary pulse, and The point is that a flip-flop is connected that uses the output of the circuit as a set signal and a reset signal.

FIG. 5 shows an operation time chart of the circuit of the present invention, taking the Up phase as an example. The two inputs of the AND circuit 32-a are Up.
The output is the main pulse signal of the Up phase as shown in FIG.
By using the P phase main pulse signal b' as a reset signal, the flip-flop is repeatedly set and reset.

The following operation is similar to the conventional digital method, and is an AN between an oscillator and a 7-lip, 70-tub set output.
Phase loss is detected by taking D, counting by a counter, and comparing the counted value with reference data DI+, but the basic operation is quite different.

That is, when a phase input occurs in any phase, there is always one or more flip-flops to which only a set pulse is input and a reset signal is not input. In the conventional system, since the input signal is the sum of six-phase pulses, there is no flip-flop as described above.

Therefore, the detection time can be arbitrarily selected as long as it is 1 part 3 or more of one period of the minimum power supply frequency used, and therefore malfunctions unlike the conventional system do not occur. Conversely, even if the power supply frequency becomes high (if pulse loss occurs continuously), there is a flip-flop that continues to output the set output, so no malfunction will occur.

Note that the portions indicated by dotted lines in FIGS. 5c, e, and f show the operation when the signal b' (Vp phase main pulse) used as the reset pulse has an open phase.

As described above, by adopting the circuit of the present invention in the APPS pulse phase loss detection circuit, it is possible to achieve
If it is possible to detect a pulse phase loss of the variable frequency APP8 having a narrow width double pulse output, it will be very advantageous in terms of maintenance of the 1-mu control device.

Figure 6 shows a modification of the circuit in Figure 4.Instead of counting the pulses of the oscillation circuit with a counter, a method is used in which the period during which the set signal of the flip-flop is output is directly measured with a timer. I'm taking it. This method can also satisfy the same function as the circuit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the Zyristor conversion device. FIG. 2 is a block diagram of a conventionally used pulse phase loss detection circuit. Third
The figure is a time chart showing the operation of FIG. 2. FIG. 4 is a configuration diagram of a pulse phase loss detection circuit according to the present invention. FIG. 5 is a time chart showing the operation of FIG. 4. FIG. 6 shows a modification of the pulse phase loss detection circuit of the present invention. 31...Flip-flop, 32-a...AN
D times M, 32-b...AND circuit, 33...Oscillation circuit, 34...Author /M -272- Kaya1 at p

Claims (1)

[Claims] 1. Set signal for one phase pulse of APPS which has narrow width double pulse output consisting of main pulse and auxiliary pulse,
a flip-flop whose reset signal is a noculus delayed by 0° from the pulse; an AND circuit that ANDs the set signal of the flip 70-tube and the output of the oscillation circuit; and a counter that counts the output of the AND circuit; a comparison circuit that issues a signal when the counted value of the counter exceeds a certain value;
An AND circuit configured to extract only the main pulse from the double pulse is added to the pulse phase loss detection circuit consisting of a signal output circuit for outputting the output of the comparator circuit to the outside, and the above-mentioned 7-lip 70-tube Set one main pulse from the AND circuit to the signal, the signal is υ120° or 180°
By adding the main pulse of the delayed phase as a reset signal, the APPS pulse phase loss detection circuit is configured to prevent malfunctions and malfunctions even if the power supply frequency changes widely.