JPS58223962A - Shading compensating device - Google Patents

Abstract

PURPOSE:To attain accurate shading compensation even at a synthesized point, by selecting the synthesized point of plural photoelectric converting elements or a picture element near the point as a sampling point. CONSTITUTION:A reflected light is introduced to plural photoelectric converting elements 6, 6' and the output is synthesized at a synthesized circuit 10. The synthesized output is sampled in a timing predetermined at a 1st timing circuit 9 and a sample-and-hold circuit 11 to obtain a shading compensation coefficient relating to the sampling picture element at an operation processing circut 13 and it is stored in a storage element 16. An interpolation circuit 19 obtains the shading compensating coefficient of non-sampling picture element from the shading compensation coefficient of a sampling picture element read out from the element 16. Further, the synthesized point of the plural photoelectric converting elements 6, 6' or the picture element of the vicinity is selected as the sampling point.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to shading correction support for correcting shading characteristics of photoelectric conversion elements such as CCl).

Illuminate the recording surface of the original with a lamp and reflect the reflected light!
) A recording device that uses a photoelectric conversion element such as a solid state transducer or a 7-diode array through a mirror or lens and re-records an image based on the output signal of the photoelectric conversion element is already widely known. (There is.

In this type of recording device, even when reading a document surface with uniform reflection m degrees, the output waveform of the photoelectric conversion element does not become flat. A shading phenomenon is observed in which the output of pixels at the edges becomes smaller. The causes of this include the following.

(b) Attenuation and light effect by the lenses of the optical system The amount of light passing through the lenses of the optical system decreases at the periphery according to Rinn's fourth power law, and even if tJ' half angle of view is 2
At 0 degrees, the peripheral light is 78% of the central light.

(b) Non-uniform sensitivity of photoelectric conversion elements Photoelectric conversion elements such as solid-state image carriers (CCI) and diode arrays may have non-uniform sensitivities due to manufacturing reasons.

(c) Illuminance unevenness and illuminance changes of the irradiation lamp For example, a fluorescent lamp is used as the original irradiation lamp, but the length of the lamp is finite, and the illuminance is lower because the luminance at both ends is lower than at the center. Also, as fluorescent lamps are used, both ends may turn black.
The illumination surface distribution also changes depending on the installation.

Conventionally, various compensation measures have been taken to compensate for this shift. For example, uniform reflection m
The anti-OA light on the polished surface is guided to the photoelectric conversion element, and its output fF
The i number is converted to Δ/I') and stored in a storage element, and the stored contents are read out when reading the original to create a shading waveform. This correction accuracy is quite good, but the A/D
The time required for the conversion operation of the converter becomes shorter as the driving frequency of the photoelectric conversion element becomes higher, which poses the problem of not being able to handle high-speed reading. In addition, the number of pixels in the photoelectric conversion sensor 4 increases 1')
There is also the problem that memory devices are becoming increasingly popular.

IkoC1 In order to solve these problems, Japanese researchers published a patent application (Shading correction device) in December 1982/1983, and when photoelectrically converting the uniform-anti-sword f4 degree plane,
A shading correction coefficient for a limp pixel is obtained by limping the conversion output of a specific pixel, and at the time of sheeting correction, a correction coefficient for a non-limp ring pixel is obtained by an interpolation method and applied to the original image signal or the original image I! ! High-speed reading is possible by increasing the halftone reproducibility of the signal using the D-tone f method and applying a dither threshold value of 1 to 1 to convert the signal into τ binary values, and obtaining an output after shading correction. did.

By the way, in order to increase the resolution of reading, if a reading device is configured to convey an image using a plurality of imaging lenses and photoelectric conversion elements and synthesize the outputs, the Collin's fourth power law of the imaging lens will cause For example, when two photoelectric conversion elements are used, the shading waveform becomes like curve a in FIG. 1, and a seam occurs at the combining point. For this reason, the above method
.

In the correction method that calculates the shading correction coefficient for the sampling pixel from the number value, and then calculates the complementary i coefficient of l for the non-1 numbered pixel during correction, the shading correction coefficient for the pixel near the synthesis point (seam) is A problem arises in that the -γ-ing compensation IF coefficient (correction coefficient by interpolation method; curve b indicated by a broken line in the figure) is significantly different from the ideal compensation it coefficient (curve C indicated by a solid line r).

A conceivable solution to this problem is to perform shading correction on each photoelectric conversion element to make the level uniform before combining them, but this requires a 2-ft correction device and is expensive.

The present invention was made in view of the 1-distribution point, and by selecting, as a sampling point, a composite point of a plurality of photoelectric conversion elements or a pixel in the vicinity thereof, accurate data can be obtained even at the composite point (seam). The present invention provides a 1.-shading correction i1E device that provides a shading correction coefficient of 7''.

The present invention will now be described in detail with reference to the drawings.

FIG. 2 is an explanatory diagram showing the main parts of a document reading device with a movable document table. This device irradiates a document 2 placed on a document table 1 with a lamp 3, and makes the reflected light enter a photoelectric conversion element 6.6' via a reflection R4 and an imaging lens 5.5'. It obtains image signals, and is provided with a white reflective surface 7 in the non-image area in front of the document table 1, and a lens 5° 5'.
The photoelectric conversion elements 6 and 6' are connected to each other, respectively.
The reason why two photoelectric conversion elements 6 and 6' are used in this way is as described above.
This is to read the original 2 at high resolution Q[. For example, △4
When reading a document in the vertical direction at 16 dat/mm, the photoelectric conversion element has 210 (nun) x 16 (
As is clear from the calculation of 81 dat/mm>, 336
A device with 0 or more pixels with warts is required, which is difficult to achieve with the photoelectric conversion element of A-1, but if two photoelectric conversion elements of 2048 pixels are used, the above resolution can be easily achieved. Incidentally, the sub-scanning is performed by moving the document table 1 in the direction of the arrow.

FIG. 3 is a block diagram of an embodiment of the shading correction coefficient of the present invention which takes the output of the reading device as input.

In the figure, 8 is a photoelectric conversion element 6. A first control circuit 9 outputs a driving clock of the CV, a signal for synthesizing the output of the photoelectric conversion element 6. ) A first timing circuit that sets the timing for lean-pulling the output of the photoelectric conversion elements 6 and 6' when the white reflective surface 7 is scanned, based on the drive L1 outputted from sI. be. 10 is a synthesis circuit that synthesizes the output image signals of the photoelectric conversion elements 6 and 6' according to the timing of the synthesis signal given from the first control circuit 8; 11 is a synthesis circuit that synthesizes the output image signals of the synthesis circuit 10 with the timing of the synthesis signal given from the first control circuit 8; 9, a ripple hold circuit that performs rinsor hold based on the output signal; 12, a 1)/△ converter that converts the digital input into an output; 13, the output image signal VX, D/D, of the ripple hold circuit 11; An arithmetic processing circuit that calculates the output Vy of the △ converter 12, 1/I is a reference (voltage V r and the arithmetic processing circuit 13
There is a comparator that compares the output vO of . Further, 15 starts its operation with the output of the first timing circuit 9, and according to the output of the comparator 14, the MSB of the 1]/△ converter 12
A second control circuit 16 is set by the second control circuit 15 to set each bit from 1 to LSB. :D/
A storage element such as a RAM into which digital inputs to the △ converter 12 are successively inputted, 17 is a second timing circuit that outputs a timing signal for southward input to the storage element 16, and 1B is the storage element 16. This is a third timing circuit that outputs a timing signal for reading from. In addition, 19 indicates the series of limp pixel read out from the memory element 16.
- an interpolation circuit that calculates a shading correction coefficient for a non-zumbling pixel by an interpolation method from the aying correction coefficient;
Reference numeral 20 denotes an interpolation timing circuit that sets the timing of calculation and transmission of shading correction coefficients in the interpolation circuit 19. Furthermore, S+, S2, Ss, and S4 are switches controlled by a switching signal from the first control circuit 8,
When storing the shading correction coefficient, it is switched to contact a, and when reading an original, it is switched to contact s.

Next, the operation of the shape ink correction device having the above configuration will be explained.

The operation of storing the button correction coefficient will now be explained. During this operation, the switches 81 to S4 are switched to contact a.

In the first timing circuit 9, the ψ photoelectric conversion element 6.6' shown in FIG. 4(a) outputted from the first control circuit 8,
Based on the drive clock and the photoelectric conversion start signal shown in FIG. 12B, a sample and hold signal as shown in FIG. In FIG. 4 (Ll), a section P is a shading correction coefficient storage period, and a section Q is a document reading period -C.

On the other hand, the synthesis circuit 10 synthesizes the outputs from the photoelectric conversion elements 6 and 6', that is, the shading waveform obtained by photoelectrically converting the white reflective surface 7 into a series of signals, and synthesizes the outputs from the photoelectric conversion elements 6 and 6' into a series of signals, The output is overturned to 11. To be specific,
The output waveform of the photoelectric conversion element 6゜6' is Δ' in Fig. 5, and there is some overlap, but the output of the combining circuit 10 is one No. Become.

The 4J sample hold circuit 11 converts the shading waveform output from the synthesis circuit 10 into the L signal of the ripple hold signal.
Lean pulling is performed at the level, held at 1 level, and output to the arithmetic processing circuit 13.

The timing of switching to the photoelectric conversion element (31) S1 et al. 6' during synthesis in the sampling interval 1 synthesis circuit 10 is as follows:
The settings are made so that the following condition 1'1 is satisfied.

(1) The number of pixels used when synthesizing the photoelectric conversion element 6 and the number of pixels used when synthesizing the photoelectric conversion element 6' should be an integral multiple of the ring-ring interval.

(2) The sum of the number of pixels used when synthesizing the photoelectric conversion element 6 and the number of pixels used when synthesizing the photoelectric conversion element 6' must be greater than or equal to the total number of pixels.

For example, t! of an A4 manuscript! L (210mm>16dO
Resolution of t/n+n+ (total required number of pixels 3360)
r When reading using two 2048-pixel photoelectric conversion elements, set the -1 clause f'l to full IζFl according to the rimping interval 1/64 (one rimbling for 61 pixels). Next, it is possible to set the following.

0) The combination of the number of pixels used in the photoelectric conversion element 6.6' is 2.
048 (64X32) and 1344 (64x21>.

■The combination of the number of pixels used in the light weight conversion elements 6 and 6' is 16.
44 (64X26) and 1728 (6/X 27).

Among these settings, the setting of h in (2) uses the central signal, so the slope of the shape C leg is small, and the correction rate when corrected by rimbling is good.

The control circuit 15 also starts operating in synchronization with the ring 1 low signal. Then, first D/(□,
△Converter 12 (DMSB is O, 6°5, D/
△ 1/2 FS (full wool) signal V from converter 12
y is output, and this signal VV and number hold circuit 1
The first 4 non-pull value of the waveform VX = V + (see Figure 5) which operation V
O==VI·Vy is performed in the arithmetic processing circuit 13. This output VO is compared with a reference voltage vr in a comparator 14, and when vr>vO, an H level is output, and when Vr<VD, an L level is output from a comparator 1/I. The control circuit 15 outputs M S when the output of the comparator 14 is 1 level.
B is left unchanged and the process proceeds to the lower bits, and conversely, when it is at L level, the MSB is turned off and the process proceeds to the lower bits. Thereafter, similar operations are performed up to the LSB.

This operation is performed in synchronization with the internal timing circuit 11 of the second control circuit 15, and an example of the timing circuit -1- is shown in FIG. Here, the resolution of the D/Δ converter 12 is 8 bits. Incidentally, the start signal is generated from the Linnorhold signal.

When the setting from MSB to LSB is completed, a conversion completion signal is output from the second control circuit 15 to the second timing circuit 17. This causes the second timing circuit 17 to write the setting digital output of the second control circuit into the storage element 16.

The following ten operations are performed repeatedly by the number of samples (m times of VX = V, .about.Vm) based on the Norhold signal (see FIG. 5).

By the way, the γ digital setting for the above operation is Vr
==VQ.

That is, it is designed to satisfy the condition ■×·Vy=Vr−constant. Therefore, Vy is the shading coefficient itself, and corresponds to the curve 0 in FIG. Therefore, the shading correction coefficients for all limping pixels are written in the memory element 16.

Next, the operation during document reading (shading correction) will be explained.

In response to the stop signal from the control 911 circuit 8 shown in FIG. 4 ([1), at time t1, switches $1 to S4 open contact a
to contact 1). After that, the next time the start signal is output [? In the meantime, the data VOI and VO2 of the shading correction coefficients at the first and second 4 non-1 ring points are read out from the storage element 16, and the interpolation circuit 19'T'' processing is performed. Since a detailed circuit example of one circuit has been shown, the interpolation process will be explained based on this figure. First, the first data V o+ of the correction coefficient γ− is held in the latch 21, and the second The data VOI are held in the latch 22 (see FIGS. 5 and 8 for Vm and Vro).The performance section 23 stores these data VOI.

The next dividing circuit 24 which calculates the difference in VO2 (\10+-Vo+) and panorizes this calculates the difference ΔV+- between pixels based on the number n of non-limping pixels between sampling pixels.
Find (Vo+ -Vm)/(n-11). These series of calculations are performed 0 times between times 11 and 12. At the start of document reading t? Then, switch S5 is switched to contact a, C' 63, and latch 27 is set to data VOI.
It holds C.

Therefore, the first data V o+ is])/△ converter 1
It is output to 2. At the next timing, switch S
At the same time as 5 is switched to the contact point, ΔV is applied to the wrap 25.
+ is held, and the operator 26 outputs Vll+-ΔV1. The wrap 27 holds this and connects the D/A converter 12.
Output to.

As a result of updating the memory contents of the controller 127, a new calculation (V*+-△V+)-∆V1・■o1 is performed in the calculation unit 26.
-2ΔV1 will be generated. The wrap 27 holds this again and outputs it to the D/Δ converter 12. Furthermore, next to the
Operation (\101-2ΔVl) -8V + -V o
+-38V I Ka, JJ Sah, []7'△Converter 1
2 is output. Thereafter, calculations are similarly repeated in synchronization with the drive clock of the second control circuit 8, and the calculation results are output to the 1)/'Δ converter 12. The arithmetic processing based on the interpolation method described in item 1- is performed using a timing signal from the interpolation timing circuit 20.

Incidentally, at the time point C1 when △V1 is held at lap 25
Two pieces of correction coefficient data necessary for the next interpolation calculation are read out from the storage element 16, and V2 for the next change is determined by the same calculation as in the case of ΔV+. In this way, ΔV
The reason why the calculation process of + and the calculation process of Δ\12 are performed in parallel is to shorten the processing time by the interpolation circuit 19. Interpolation calculation using the newly calculated change is also quickly performed.

The shading correction coefficient outputted from the interpolation circuit 19 by the twin operations is converted into the D/A converter 12 t'ab'], and then sent to the document reading signal VX outputted from the sample hold circuit 10 and the arithmetic processing circuit 13. It is then calculated and output as a corrected image signal vO.

In addition, when performing the above correction operation, let vkI and Vkz be the four adjacent summation values of the shading correction coefficient when two photoelectric conversion elements are used, as shown in 0 in FIG. Therefore, vkI > Vk2. vk, <
Vk2. Vk I>Vk2, Vk1<Vk
2 Toftwal. Ikoi 1 P, in the region of Vk + <Vk 2, the input part 2
The calculation contents of 3 are Vk 2 - Vk I, and 11 part 26
The calculation contents of Vk++ΔV, the interpolation timing circuit 20
'r: Switching with.

By performing the shading correction as described above by 1j for each scan, shearing can be completely corrected even when a plurality of photoelectric conversion elements are used to increase resolution. Furthermore, since the correction coefficient is not calculated from the 1-y' ink waveform for all pixels, but the shading correction coefficient is calculated using a predetermined rimbling density, the allowable processing time is greatly reduced, and Compared to the method of determining correction coefficients, high-speed reading is possible.

In the above embodiment C, the sampling interval when calculating the ink correction coefficient is 1/64 (one time per 64 art collections).
However, the sampling interval does not need to be constant, and can be changed as appropriate depending on the amount of change in the shading waveform or the resolution of document reading.

In addition, for abnormal pixels of the photoelectric conversion element, if the correction coefficient is calculated separately, a more accurate shading correction i can be obtained.
f becomes possible.

In the above embodiment, a C-multiplication circuit is used as the arithmetic processing circuit 13, and the image signal is directly corrected. It may be corrected. The case of correcting the dip threshold will be described below. 4× shown in FIG.
Taking as an example the daily matrix of No. 4 (0, 8, 2, 10, . . . is a dither threshold value), the value before correction of the dither threshold value is shown only for the first row of the dip matrix as shown in Fig. 10. The image becomes as shown in (C) of (A).The output (image signal) of the charging conversion element at this time when C1 uniformly captures an image of the one-time reflection surface is shown by the dashed-dotted line in Figure 10 (A). It should be constant as shown in a), but due to shading it actually becomes like the dashed double-dashed line (b). Therefore,
-If this is binarized using the dark value before correction, the first
The result is as shown in the upper column of Figure 0 (b), which is affected by shading. Here, the black circles in FIG. 10 ([1) are signals to be printed by binarization, and the white circles are signals C that are not to be printed. In this case, the first part of Figure 9? If the solid line (C) is changed to the broken line (d) by correcting it according to the i-th threshold shading of the j-th, the binarized output will be as shown in Fig.
As shown in the lower column of b), the same result as when the output (b) of the photoelectric conversion element in FIG. 10(a) is corrected to (a >) can be obtained.

This delay threshold value may be corrected based on the following equation.

j゛Irregular threshold value/Seeding correction coefficient-Dither threshold value after compensation iE To execute this, the arithmetic processing circuit 12 shown in FIG.
It is necessary to configure, for example, as shown in FIG. 1-1. In FIG. 11, it goes without saying that ■× is an image signal and Vy is a shading correction coefficient. This arithmetic processing circuit 13 stores in advance a group of values between I and I constituting an I/I risk in a storage unit 131, sequentially reads them out and gives them to the UD/Δ converter 132, and converts them to the UD/Δ converter 132. 1 output \/d is input to the divider circuit 133, and this is input to the divider circuit 133, which
Divide by the agonizing correction coefficient vy, and its calculation unity \ld/
VV is input to the non-inverting input terminal of the comparator 13/I, and the image signal Sometimes, the value of \l×・Vy is required, so the configuration is such that the value V×・Vy can be output from the multiplying circuit 135 to the analogue.In other words, when calculating the shading correction coefficient, switch SW is turned a. The switch SW is connected to the contact 1) during dither processing.

Note that without using the ])/△ converter 12 in FIG. 3, the input of A is directly applied to the allocation circuit 13:3 in FIG.
If a dip threshold value within 1 is directly given to the division circuit 133, and the image signal Vx is A/D converted and used, the daily threshold value can be corrected by digital arithmetic.

In this way, the shading correction device can be manufactured easily and at low cost.

Note that the limit of correction accuracy is determined by the processing circuit after correction. For example, when expressing halftones by the dither method, it is determined by the size of the t-trix.

Further, in the embodiment -1, an example was explained in which the uniform reflection surface was white and provided in the non-image area C1, but the present invention is not limited to this.

Furthermore, instead of the merging point itself, pixels in the vicinity thereof may be limbed.

As described below, in the present invention, even when a plurality of photoelectric conversion elements are used, the shading correction can be accurately calculated, Image quality can be improved. The present invention is particularly effective when reading at high resolution.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of shading waveforms, Fig. 2 is an explanatory diagram of main parts showing an example of a document reading device with a movable document table, Fig. 3 is a 10-step diagram showing an embodiment of the present invention, and Fig. 4 is a timing chart for explaining the shading coefficient storage operation f1, FIG. 5 is an explanatory diagram showing shading waveforms and shading compensation coefficients, and FIG. 6 is a timing chart for setting each bit of the D/A converter p-t. 7 is a block diagram showing an example of the detailed configuration of the interpolation circuit, and FIG. 8 is an explanatory diagram showing calculation of the shading correction coefficient by the interpolation method.
FIG. 9 is an explanatory diagram showing an example of an iripantrix, FIG. 10 is an explanatory diagram of divisorization using the scaler matrix of FIG. FIG. 2 is a configuration diagram of a processing circuit. 1... Original table 2... Original 33... Runno 4... Reflector 5.5'... Imaging lens 6.6'... Photoelectric conversion element 8.15... Control circuit 9.17.18...Timing circuit 10...Composition circuit 11...Ripple hold circuit 12...D/A converter 13...Arithmetic processing circuit 14
...Comparator 16...Memory element 19...Interpolation circuit 20...Interpolation timing circuit Patent applicant: Konishi Rokushasou Kogyo Co., Ltd. Patent attorney Fuji Ijima Jiraku 1st day 20 77÷ ＼ −6,6'

Claims (1)

[Claims] The reflected light from the reflecting surface with a uniform reflection of 11 degrees is guided to a plurality of photoelectric conversion elements through each imaging lens, and the output of the photoelectric conversion elements is lean-bred at a predetermined timing, and the sample is It is configured to calculate the slitting correction coefficient for the limp pixel from the value, and use the interpolation method when reading the document to find the slipping correction coefficient for all used pixels. In addition, the J-shielding correction apparatus is characterized in that, as the sampling point, a combination point of the plurality of photoelectric conversion elements or a pixel in the vicinity thereof is selected.