JPS58223928A - Echo canceler - Google Patents

Abstract

PURPOSE:To eliminate the effect of nonlinear characteristics of a D/A converter, by optimizing approximately an impulse response at each input series pattern. CONSTITUTION:A transmitted data series having a length corresponding to continued time of impulse response of an echo path is split into plural groups and each is nputted to memories 6001, 6002 by designating a transmitted data series split to each group as an address. The output data of each memory is converted into an analog signal by D/A converters 7001, 7002 and added respectively and outputted as an echo replica. Then, the difference between a signal received as (echo + receiving signal + noise) and the echo replica is converted into a digital signal at a converter 1100 and a scaling circuit 2000 via a sampling and holding 1000, a prescribed scaling is executed by the circuit 2000 and produced as an error signal. The sum between the output signal of each memory and the error signal is supplied as an input signal of each corresponding memory to update the content of memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an echo canceller device for canceling echoes caused by impedance mismatch in 2-wire/4-wire conversion.

Currently, the so-called integrated service digital network (ISDN;
ated Services Digital Net
-work), active research is underway in various places. We are also developing technology to realize two-wire bidirectional digital transmission using existing subscriber cables that have been introduced for the purpose of transmitting analog voice signals.
This is one issue for constructing 5DN.

An echo canceller device is known as a known means for realizing two-wire bidirectional digital transmission.

FIG. 1 is a block diagram showing an example of the configuration of a conventional echo canceller device. In the figure, reference numerals 1 and 2 are an input terminal and an output terminal, respectively, reference numeral 3 is a transmitter, reference numeral 4 is a receiver 1, reference numeral 5 is an adaptive digital filter (ADF), and reference numeral 6 is a D/
A converter (ADO), reference number 7 is subtracter, reference number 8 is sample hold (SH), reference number 9 is A/D
4 converter (ADO), reference numeral 10 indicates a low pass filter (LPF), % reference numeral 11 indicates a hybrid circuit (HYB), and reference numeral 1212 indicates a transmission line.

It is now assumed that the circuits of FIG. 1 are connected oppositely via a two-wire transmission line. For subscriber cables, one is installed on the station side and the other on the subscriber side. moreover,
Here, in order to simplify the explanation, baseband transmission is assumed and the explanation will be made as a subscriber side device.

A transmission signal from a subscriber terminal is input to a transmitter 3 and an adaptive digital filter 5 via an input terminal 1. Here, it is assumed that the transmitted signal has already been subjected to a scrambler operation so that there is no correlation with the received signal. The transmitting section 3 is an interface circuit between the subscriber terminal and the two-wire transmission line 12, and is composed of a unila/bipolar conversion circuit, a band-limiting filter, a buffer amplifier, etc. as necessary. The output of the transmitter 3 is sent to the two-wire transmission line 12 via the hybrid circuit 11, and at the same time, it is also input to the LPFIO as an echo due to a circuit malfunction or impedance mismatch in the hybrid circuit 110.

On the other hand, a received signal sent from the other party (in this case, the office side) is also input via the two-wire transmission line 12 and the hybrid circuit 11 via the LPFIO. Now, the echo signal is e (company) (where k is the index indicating the time), and the received signal is 8
(g), If the noise received by the received signal B (b) on the two-wire transmission line 12 is n (sha), then the LPFIO output signal U (sha)
is expressed as the following equation.

u(k)=e(k)+s(k)+n(k)...
(1) Here, the purpose of the echo canceller is to generate a replica ■(k) of the echo signal e(k) in equation (1),
The goal is to eliminate echo signals. In FIG. 1, a closed loop circuit consisting of an adaptive digital filter 5, a D/A converter 6, a subtracter 7, a sample hold 8, and an A/D converter 9 is used to adaptively perform echo processing.
By generating the replica ■(k), r(k) shown in the following equation can be obtained as the output signal of the sample hold 8.

r(k)=e(k)−■(k)+a(k)+n(k)・
(2) Here, (k) is the output signal of the D/A converter 6, and is input to the subtracter 7. Further, in equation (2), {e(k)-■(k)} is called a residual echo. The receiving section 4 is comprised of a bipolar/unipolar conversion circuit, a Nyquist filter, a line equalizer, a power amplifier, etc., as required.

FIG. 2 shows an example of the configuration of the adaptive digital filter 5 shown in FIG.

In FIG. 2, reference numerals 50 and 51 are input terminals, reference numerals 52o, 52 . , . . . , 52N-2 is a delay element, reference numeral 53. ．． 53. , . . . , 53N- are coefficient generation circuits, reference numbers 54°, 54. ,..., 54N
-1 indicates a multiplier, reference numeral 55 indicates an adder, and reference numeral 56 indicates an output terminal. In Figure 2, input terminal 5
The input signal a(k) supplied to the input terminal 0, the input signal r(k) supplied to the input terminal 51, and the output signal A(k) supplied to the output terminal 56 are respectively of the adaptive digital filter 5 in FIG. input/output signal a(b) r/
(g) and money! (G) is supported. The input signal a (b) supplied to the input terminal 50 is simultaneously supplied to the delay element 52°, the multiplier 54°, and the coefficient generation circuit 53o. On the other hand, the delay elements 52°+"21+..., 52N-2 are connected in cascade in this order, and the connection point has a configuration as shown in FIG. 2. That is, the delay elements 52
The output signal a(k-m-1) of the delay element 52m+-
+, multiplier 54mFt and coefficient generation circuit 53m-LI
K is supplied at the same time. However, m is a natural number. In addition, the input signal r'(k) supplied from the input terminal 51 is
Coefficient generation circuit 53°, 53. , ・.

53N-, are simultaneously input. Furthermore, the coefficient generation circuit 5
3m receives input signals r'(k) and a(k-m) and outputs a coefficient cm(k), which becomes an input signal to a multiplier 54m. Also, N multipliers 54°, 54. , 54.1...

The output signals of 54N- and 54N- are all added together by an adder 55 and are supplied to an output terminal 56.

In this way, an echo replica ζl(g) can be generated from the input signal a(g) based on the value of the error signal 1'(ri).Delay elements 52o, 521, . . .
The delay amount of 52N-2 is T seconds, which is the same as the sending data rate, and can actually be realized by flipping 70 tubes. In the coefficient generation circuit Am, the coefficients are updated by an adaptive algorithm such as the steepest descent method so as to minimize the error signal -@1' (g). Note that FIG. 2 basically shows the configuration of a transversal filter, and when the coefficients converge, each coefficient is transferred to the transmitting section 3. F
[Y: This is an approximation of the impulse response of an echo path consisting of 811 and LPFIO.

Next, problems with FIG. 1, which shows the configuration of a conventional echo canceller, will be explained. In FIG. 1, an adaptive digital filter 5, a D/A converter 6, a subtracter 7, a sample hold 8, and an A/D converter 9
In a closed-loop circuit consisting of
The level of e(k)-e(g)) becomes large, which becomes a problem. In particular, the nonlinear characteristics of the D/A converter 6 have a significant effect on the above problem. The nonlinear elements of the D/A converter can be divided into quantization noise and nonlinear characteristics specific to the D/A converter. Here, the influence of quantization noise can be ignored by making the number of bits of the D/A converter sufficiently large. However, the nonlinear characteristics inherent to a single unit can be reduced to some extent by circuit adjustment;
This requires a large number of man-hours and becomes a factor in increasing costs.

Furthermore, in order to reduce the nonlinear characteristics that cannot be reduced by one-circuit adjustment, fine adjustment by laser trimming or an additional circuit to compensate for the nonlinear characteristics is required, which increases cost or circuit size.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an echo canceller device with less performance deterioration due to the nonlinear characteristics of a D/A converter.

Another object of the present invention is to provide an echo canceller device that does not require circuit fine adjustment of the D/A converter.

Furthermore, another object of the present invention is to provide an echo canceller device that has a small hardware scale and is suitable for LSI implementation.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

In the figure, reference numerals 100 and 200 are an input terminal and an output terminal, respectively, reference numeral 300 is a transmitter, reference numeral 400 is a receiver, reference numerals 500, . 500. ,...
・5°006 is a delay element with a delay of T seconds, reference number 600
．． and 600. is rewritable memory, reference number 70
01 and 700. is a D/A converter (D/A), reference number 800 is an adder, reference number 900 is a subtracter, reference number 1000 is a sample hold (S/H), reference number 1
100 is A/D converter (A/D), reference number 120
0. and 12002 is an adder, reference number 1300 is a reduced pass filter (LPF), reference number 1400 is a hybrid circuit (HY3), reference number 1500 is a 2a transmission line,
Reference numerals 2000 each indicate a scaling circuit.

In Figure 3, for ease of explanation, the adaptive
An example is given in which the number of taps in the filter is 8, and a case is shown in which the 8 taps are divided into two. However, as explained below, there are no limitations on the number of taps and the number of divisions. There isn't. To further simplify the explanation, we will first explain very simple encoding, in which binary code ``0'' is converted to +1 and ``θ'' is converted to -IK, and other codes are For example, bipolar codes, pi-phase codes, etc. will be described later.Also, in order to simplify the explanation, the operation rate of the digital signal processing section will be explained as being the same as the input/output data rate. An interpolation type in which the operation rate and data rate are different will be described later.Next, the operation shown in FIG. 3 will be explained in detail.

In Figure 3, the binary code “0” or “1”
The data series is supplied to the input terminal 100 and sent to the transmitter 30
0 and becomes the input signal of the delay element 5001. Transmission section 30
0 is an encoding circuit, which converts the binary code “0” to +1 “
1" corresponds to -1, and is sent to the two-wire transmission line 1500 via the hybrid circuit 1400. On the other hand, the speed of the binary code data sequence supplied to the input terminal 100 is T seconds. Yes, delay elements 5001, 50
02, . . . , 5006, and these delay elements can be realized by flip-flops operating at a clock speed of T seconds. The data series supplied to the input terminal 100 and the output data series of the delay elements 5001, 5002, 5003 are input as address signals to the memory 6001. In addition, delay elements 5004, 5005, 50
Each output data series of 06 and 5007 is stored in the memory 600.
It is input as the second address signal. The data outputs of the memories 6001 and 6002 are each connected to an adder 1200s.
and 12002, and at the same time, the D/A
The signals are also input to converters 7001 and 7002 and converted into analog signals. D/A converter 700] and 70
Two analog signals, which are the outputs of 02, are added by an adder 800 and then input to a subtracter 900. Adder 800
The output signal of is the echo replica ■(k) explained in Figure 1.
corresponds to

On the other hand, the output of the transmitter 300 is transmitted to the hybrid circuit 1400.
Due to circuit failure, the echo becomes an echo and is also input to the LPF 1300. Also, the received signal sent from the other party via the two-wire transmission line 1500 and the hybrid circuit 1400 is
It is input to LPF1300. Therefore, LPF1300
The output signal u(k) of is expressed by equation (1) as before.
It is represented by Similarly, the signal r(k) output to the sample hold 1000 via the subtracter 900 is expressed by the equation (
2). The output signal of sample hold circuit 1000 is input to receiving section 400 and A/D converter 1100. The receiving section 400 includes a Nyquist filter, fixtures such as lines, a buffer amplifier, a code inverse conversion circuit, and the like. A signal sent from the other party appears at the output terminal 200 as a binary code sequence by the receiving section 400.

The output signal of the sample and hold 1000 is converted into a digital signal by an A/D converter 1100, and is subjected to constant scaling via a scaling circuit 2000 to an edge adder 1200. and 12002. Furthermore, the output signals of adders 12001 and 12002 become inputs to memories 6001 and 6002, respectively.

In FIG. 3, the memory 600s stores the error signal A/
Based on the output signal of the D converter 1100, the input terminal 1
It operates to approximate the impulse response of the echo path for 0 to 3 T seconds from the time when data is input to 00, and the signal output as part of the echo replica is input to the D/A converter 7001. Here, the echo path includes the transmitter 300, the hybrid circuit 1400, and the LPF 130.
It means a path consisting of 0. Similarly, Memo 1J60
02 operates to approximate the impulse response of the echo path for 4T to 5T seconds from the time when data is input to the input terminal 100, based on the output signal of the A/D converter 1100, which is an error signal. The output signal is input to the D/A converter 7002. Therefore, in the block diagram shown in FIG. 3, a replica of an echo for 7T seconds can be generated.

As shown in FIG. 3, the feature of the present invention is that the approximation of the impulse response is optimized for each input sequence pattern, so that the influence of the nonlinear characteristics of the D/A converter can be removed.

In other words, the nonlinear characteristics of the D/A converter can be absorbed by the method of implementing the optimization algorithm of the present invention.

To explain this feature more clearly, delay elements 5004, 5005, 5006 and 5007, memory 6002. D/A converter 7002, adder 1200
2 and the adder 800, the D/A converter 7001
Consider a configuration in which the output of is directly supplied to the negative input of subtractor 900. At this time, for each 4-bit input data series input as an address of the memory 6001, 3T
Optimization of echo replicas for seconds is performed. That is, the output signal of the memory 6001 is converted into an analog signal by the D/A converter 7001. By the subtracter 900, the D/A
After the difference between the output signal of converter 7001 and the output signal of LPF 1300 is taken, it is input to sample hold 1000 and supplied to A/D converter 1100 as an error signal. Furthermore, the error signal is converted into a digital signal subjected to a certain scaling by an A/D converter 1100 and a scaling circuit 2000, and then sent to an adder 120.
01 is input. Therefore, the output data of the memory 6001 is added to the output signal of the adder 12001, which is an error signal, and input to the memory 6001, and the content of the set address is rewritten and optimization is performed. in this way,
Since optimization is performed for each transmission data pattern when generating an echo replica, the D/A converter 700. The nonlinear characteristics of will be absorbed by the optimization process.

For example, if the address of the memory 60o1 is 8 bits, the address of the memory 60o1 in FIG. , D/A converter 700□adder 1200. And the adder 800 becomes unnecessary. However, in actual systems, it is known that the echo path impulse response time is approximately 16 to 32 T seconds, and in this case, the memory capacity and the number of address bits can range from 16 to 32 bits. This increases the hardware scale.

It will be explained below that according to the present invention, such drawbacks can also be overcome. A key feature of the present invention is to divide a transmission data sequence with a length corresponding to the duration of an echo path impulse response into a plurality of groups, and input the transmission data sequence divided into each group into each memory as an address. . The output data of each memory is converted into an analog signal by a D/A converter, and then all are added together and output as an echo replica. Therefore, the difference between the signal received as (echo + received signal plus noise) and the echo replica is converted into a digital signal by an A/D converter and a scaling circuit via a sample hold, and then subjected to a certain scaling in a scaling circuit. and is generated as an error signal. The sum of the output signal of each memory and the error signal is supplied as an input signal to the corresponding memory, and the contents of the memory are updated. In this way, updating of the contents of each memory is optimized so that the error signal is small. Since the digital outputs of each memory are each converted into analog signals and then added together, the nonlinear characteristics of each D/A are absorbed during the optimization process, and the advantage that they are not adversely affected is preserved. it is obvious. - For example, if we prepare four memories with an echo path impulse response duration of 31'l' seconds and an output pitch of Nm (where m is an integer) and divide them equally, the number of addresses for each memory will be 8 bits. , the total memory amount is (28xm x
4) It becomes a bit. On the other hand, since the number of addresses without division is 32 bits, the total memory amount is (
232x m ) bits. Therefore, by using the present invention, the amount of memory can be reduced by -222 times, making it possible to significantly reduce the hardware scale. In the embodiment of the present invention shown in FIG. 3, in order to simplify the explanation, the number of taps is 8 and the memory is divided into two. However, as mentioned above, the number of taps is divided into two. It is clear that the present invention does not impose any restrictions on the method of division and the like.

Note that in FIG. 3, the memory 600. and 6002
D/A converters 7001 and 700 . Although a configuration is shown in which one A/D converter is installed, it is also possible to use one A/D converter multiplexed in a time-division manner by preparing two sample and hold circuits for the output of the D/A converter. It is clear that the time-division multiplexing of the A/D converter can be applied even if the number of memory divisions increases.0 Since the embodiment of the present invention shown in FIG. 3 did not mention the transmission line code, the following describes will be described in detail. Sending data expressed in binary code is converted into a code format suitable for the characteristics of the two-wire transmission line and is sent out. The transmitter 300 in FIG. 3 performs this function. Generally, it is desirable that the code format be one that does not depend on the stochastic nature of the input information and does not have a DC component, that is, a balanced code. Bipolar (AMI) codes, Biphase codes, WAL2 codes, and the like are known as commonly used balanced codes. When the data rate is 1/T bit/S, the band for transmitting these codes is 1 for AMI codes.
/THz, Biphase code, and WAL 2 code require a band of 2/THz or more.

Therefore, the sample and hold circuit 1000 in FIG.
, A/D converter 1100 and D/A converter 70
The sampling frequency of 01 7002 is required to be 2/THz or 4/THz or more. Also, along with this, the adder 12
001, 12002 and memory 6001, 6002 are also 2
/THz or 4/THz or higher. Furthermore, since the bipolar code alternately inverts and outputs +1 or -1 pulses every time a binary "1" occurs, an operation corresponding to this is also required.

FIG. 4 is a block diagram showing another embodiment of the present invention. In this embodiment, a bipolar code is used as the transmission path code. In this figure, the same reference numerals as in FIG. 3 have the same functions. There are two points that differ from Figure 3. The first point is that the timing signal generation circuit indicated by the reference numeral 1600 and its output signal, the timing signal indicated by the reference numeral 1600', are output from the memory 60.
0. and 600 are input as addresses.

The second point is that the polarity display signal with reference numeral 300' indicating the polarity of binary "1" in the unipolar/bipolar conversion of the transmitter 300 is memo +7600. and reference number 1700
600 through a 4T second delay element shown by .

First, the transmitter 3001 polarity display pin (pi) 30 in FIG.
0' and delay element 1700 will be explained. FIG. 5 shows a circuit showing an example of implementation of the transmitter 300, and in the figure, reference numerals 300. ．． 300° and 3003 are AND gates, reference number 300. is a D-type flip-flop, and reference numeral 3005 is a subtracter. Also shown in the figure is a flip 70 knob 30 designated by the reference numeral 300'.
The Q output of 04 corresponds to the polarity indicating signal indicated by the same reference numeral in FIG. The operation of the circuit shown in FIG. 5 will be described with reference to the timing chart shown in FIG. and game) 3001 has the data rate (
1/T) bit/second transmission data and a clock indicated by ■ are input. The timing of the output is shown in FIG. When the second sister (2) is input as the clock of the flip-flop 3004, a 7Q output as shown in (2) in FIG. 6 is obtained. The output of the flip-flop 3004 is an inversion of the signal shown in FIG. Therefore, 300. and 30
When the difference between the two outputs of 03 is obtained by the subtracter 3005, the final output becomes a bipolar code as shown in FIG. If you compare ■ and ■ in Figure 6, it is clear that "1" and "0" in 1■ correspond to +1 and -1 of the bipolar code, respectively, so ■ can be regarded as a polarity indicating signal. . However, when the binary code of the sending signal is "0", it has no meaning. As is clear from FIGS. 5 and 6, the polarity display signal 300' changes every T seconds when the transmitted data continues to be "1". In Figure 4, polarity display 3
00' is the address A4 of the memory 6001, and is also sent to the memory 600.00 through the delay element 1700. address B4
is entered as . Here, memories 600° and 600.
Consider ignoring address bits A5 and B5. Let's consider memory 6001. As a specific example, the following correspondence relationship will be explained.

<When A4="1"> A4 A3 A2 A1 A01
1 0 1 0 +
1 -1 (When A4="0") A4 A3 A2 A1 A0 0
1 0 1 0 -1
+1 As is clear from the example shown above, even if the address pits A0 to A3, which input the transmission data series, have the same pattern, the unipolar/bipolar conversion differs depending on the binary value of the polarity display signal. It is necessary to make a clear distinction. Therefore, in the present invention, A4 is added as an address bit, and address bits A0 to A0 of memory 6001 are added.
Even when A3 has the same pattern, different memory cells are selected by address bit A4.

Note that when A0=A1=A2=A3="0", there is no need to distinguish between the binary values of address bit A4, but it is sufficient to inhibit A4 at this time. Of course, it is clear that distinguishing the binary value of address bit A4 at this time does not affect normal operation. Similarly, the above explanation can be applied to address bit B4 of memory 6002 in FIG. 4. However, the address bit B4 is the polarity display signal 300' delayed by 4T seconds (4 bits), and this delay amount is the number of bits of the transmission data series input as the address of the memory 6001,
In FIG. 4, they correspond to 4 bits A0 to A3.

In the above explanation, a bipolar code was assumed as the transmission line code, but if a code that depends on past multiple sample values is adopted as the transmission line code, the control signal according to the code conversion rule should be memorized at +7600° and 600. can be input as address bits. The address bits added at this time may be multiple bits.

Next, we will explain the timing signal 1600'K generated by the timing generation circuit 1600 of FIG. This is to cancel echoes for transmission line codes whose power spectrum extends to the band. In the example shown in Figure 4, a bipolar code is assumed as the transmission path code, and the power spectrum can be regarded as approximately 1/THz band, so the operation speed of the echo canceller is 2/THz.
It is necessary to operate at a T Hz sampling frequency, ie every T/2 seconds. In FIG. 4, the memory 600
．． and A among the addresses input in 6002, respectively. -A, and B0 to B4 address bits are T
While changing every second, the address pin) As and B5
changes every T/2 seconds. These timing charts are shown in Fig. 7 (2) and (2).

FIG. 7 (■) shows a timing chart of addresses A0 to A4 or B0 to B4, which changes every T seconds in accordance with the data rate. On the other hand, in the timing chart for address A5 or B5 shown in FIG.
The timing signal 16 of FIG. 4 changes every 2 seconds.
00' is generated by the timing generation circuit 1600.

With this configuration, the D/A converter 700. and 700, sample hold 1000
．． A/D converter 1100. Scaling circuit 200
0. Adders 12001 and 1200t s Furthermore, the sampling frequency of memories 6001 and 600 is set to 2/T.
Hz, and it is possible to eliminate echoes up to a band of 1/THz. Note that in the embodiment of the present invention shown in FIG. 4, it is assumed that the operation speed of the echo canceller is twice the data speed, but if the number of address bits to be added is increased in accordance with this ratio, the echo It becomes possible to operate the canceller at a speed that is an integral multiple of the data rate.

Although the embodiment of the present invention shown in FIG. 4 shows an example of a configuration using two memories, it is of course also possible to configure it with a general plurality of memories as explained in FIG. 3. be. Furthermore, as explained in FIG. 3, time division multiplexing of the D/A converter is of course also possible.

As described in detail above, according to the present invention, there is little performance deterioration due to the nonlinear characteristics of the D/A converter, and therefore,
It is possible to provide an echo canceller device that does not require circuit fine adjustment of a D/A converter.

Further, according to the present invention, since the hardware configuration is mainly based on a rewritable memory, it is suitable for LSI implementation, and an echo canceller device with small hardware scale can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration example of a conventional echo canceller device, and FIG. 2 is a detailed block diagram of the adaptive digital filter shown in FIG. 1. In FIG. 1, reference numeral 1 is an input terminal, reference numeral 2 is an output terminal,
Reference numeral 3 is the transmitting section, reference numeral 4 is the receiving section, reference numeral 5
is an adaptive digital filter, reference number 6 is D
/A converter, reference number 7 is subtractor, reference number 9 is A
/D converter, reference numeral 10 is a reduced pass filter, reference numeral 11 is a hybrid circuit, and reference numeral 12 is a two-wire transmission line. Also in FIG. 2, reference numerals 50 and 5
1 is an input terminal, reference numbers 520, 521,..., 53
N-1 is a coefficient generation circuit, reference numbers 540, 541, etc.
. , 54N-1 is a multiplier, and reference numeral 55 is an adder. FIGS. 3 and 4 are block diagrams showing one embodiment of the present invention. In both figures, reference numeral 100 is an input terminal, reference numeral 200 is an output terminal, reference numeral 300 is a transmitter, reference numeral 400 is a receiver, reference numerals 5001, 5002,
..., 5007 is a delay element of T seconds, reference number 6001
and 6002 are memory, reference numbers 7001 and 7002
is a D/A converter, reference number 800 is an adder, reference number 900 is a subtracter, reference number 1000 is a sample hold, reference number 1100 is an A/D converter, reference number 1
2001 and 12002 are adders, reference numeral 1300 is a reduced pass filter, reference numeral 1400 is a hybrid circuit, reference numeral 1500 is a two-wire transmission line, reference numeral 2000
Reference number 1600 is a scaling circuit, reference number 1600 is a timing signal generation circuit, reference number 1600' is a timing signal, reference number 1700 is a 4T second delay element, reference number 300'
is a polarity indicating signal. FIG. 5 shows an example of implementation of the transmitting section of FIG. 4, in which reference numbers 3001, 3002 and 30
03 is an AND gate, reference numeral 3004 is a flip-flop, and reference numeral 3005 is a subtracter. 6 shows an operation timing chart of the block diagram of FIG. 5, and FIG. 7 shows a timing chart of address signals of the memories 6001 and 6002 of FIG. 4, respectively.

Claims (1)

[Claims] In an echo canceller device for eliminating leakage of transmission signals from 4 wires to 2 wires to a 4 wire receiving side due to impedance mismatch of a hybrid circuit for 2 wire/4 wire exchange, a transmission data series and the transmission data A plurality of delayed transmission data sequences obtained by delaying the sequence one sample at a time are divided into a plurality of groups, and the signals divided into the plurality of group regions are rewritten in a plurality of times corresponding to the plurality of groups. each of the plurality of memories outputs the contents of the memory cell selected by the address as a memory output signal, and each of the plurality of memory output signals is individually converted into an analog signal. After converting into a signal, an echo replica is generated by adding all the plurality of memory output signals as analog signals, and after subtracting the echo replica from the received signal including the echo inputted through the hybrid circuit. The digital signal, which has been converted into a digital signal again and subjected to a scaling operation, is used as one input,
The apparatus is characterized in that the output signals of a plurality of two-man power adders each having the output of each of the plurality of memories as the other input are inputted as contents of the corresponding memory cells of the plurality of memories. echo canceller device.