JPS58223360A - Semiconductor circuit - Google Patents

Semiconductor circuit

Info

Publication number
JPS58223360A
JPS58223360A JP10715782A JP10715782A JPS58223360A JP S58223360 A JPS58223360 A JP S58223360A JP 10715782 A JP10715782 A JP 10715782A JP 10715782 A JP10715782 A JP 10715782A JP S58223360 A JPS58223360 A JP S58223360A
Authority
JP
Japan
Prior art keywords
current
imax
power source
fuses
output buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10715782A
Other languages
Japanese (ja)
Inventor
Yoji Yasuda
安田　洋史
Masami Masuda
正美 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10715782A priority Critical patent/JPS58223360A/en
Publication of JPS58223360A publication Critical patent/JPS58223360A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE:To contrive not to generate malfunctions, etc. by preventing the induction of power source noises by a method wherein the circuit is so constituted that a large current over a certain value can not flow because of fuse cutting. CONSTITUTION:N pieces of MOS transistors TRT1-Tn are commonly connected in gate inputs and drain output ends respectively, and all the dimensions of these TRT1-Tn are W/n (W is the dimension of an output buffer). Fuses F1-Fn are provided between the source ends and a power source terminal 11 respectively, and the allowable current values of these fuses F1-Fn are set at Imax/n, Imax/(n-1),...Imax(Imax is the value of current flowing the output buffer not to induce power source noises). Such a constitution enables the current which induces the noise to the power source not to flow by cutting a suitable number of pieces of fuses, even when the possibility that the large current flows is generated.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は集積回路の出力バッファ等、大容量駆動源とし
て適する半導体回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor circuit suitable as a large capacity drive source such as an output buffer of an integrated circuit.

〔発明の技術的背景及びその問題点〕[Technical background of the invention and its problems]

一般にメモリー、マイクロプロセッサ等の半導体装置に
おいて、出力バッファは外部装置の大容量負荷を高速に
ドライブする必要があるため、非常に大きなコンダクタ
ンスを有し、従って大電流が流れることになる。例えば
第１図に示す如く出力トランジスタ１のディメンジ１ン
（幅）をＷに設定した場合、そのコンダクタンスｇｍは
Ｗに比例する。従って ｇｒｎ＝ＷＸｆ で与えられる。ここでｆはトランジスタのダート酸化膜
厚、基板濃度等のゾロセスパラメータに依存する因子で
ある。In general, in semiconductor devices such as memories and microprocessors, output buffers are required to drive large capacity loads of external devices at high speed, so they have very large conductance, and therefore large currents flow through them. For example, when the dimension (width) of the output transistor 1 is set to W as shown in FIG. 1, its conductance gm is proportional to W. Therefore, it is given by grn=WXf. Here, f is a factor that depends on Zorothes parameters such as the dirt oxide film thickness of the transistor and the substrate concentration.

ところで出力トランジスタに大電流が流れた時、半導体
装置内の電流レベルにノイズを誘起しそれが種々の誤動
作の原因となるため、そのような危険性の起こらないよ
う出力バッファの最大電流値を設定せねばならない。仮
に電源ノイズを防ぐために出力バッファのコンダクタン
スをどの程度の値に設定しなければならないかが計算で
きても、実際のデバイスのコンダクタンスはプロセス依
存性が大きいため、製造条件によるコンダクタンスのば
らつきが大きく、従って設計通りの対処が得られないと
いうｈｉＪ能性がある。例えば電源ノイズを誘起しない
ための出力バッファを流れる電流の最大値をＩｍ□、及
びその時の出力バッファのディメンジョンをＷとし、コ
ンダクタンス’ｆｃ（１ｍａｘとする。いま出力バッフ
ァのディメンジョンをＷに設定したが、プロセスのばら
つきによｈｆＯ値がｆ′に変化してしまったとする。こ
の時出力バッファのコンダクタンスは となシ、ｆ’＞ｆならばｇ′ｏ＞ｇｍａＸとなり、電源
にノイズが誘起されることになる。By the way, when a large current flows through the output transistor, noise is induced in the current level within the semiconductor device, which can cause various malfunctions, so the maximum current value of the output buffer must be set to prevent such risks from occurring. I have to do it. Even if it were possible to calculate the value to which the output buffer conductance should be set in order to prevent power supply noise, the actual device conductance is highly process-dependent, so there would be large variations in conductance due to manufacturing conditions. Therefore, there is a possibility that the response as designed cannot be obtained. For example, the maximum value of the current flowing through the output buffer to avoid inducing power supply noise is Im□, the dimension of the output buffer at that time is W, and the conductance 'fc (1max).Now, the dimension of the output buffer is set to W. , suppose that the hfO value changes to f' due to process variations.At this time, the conductance of the output buffer remains unchanged, and if f'>f, then g'o>gmaX, and noise is induced in the power supply. It turns out.

〔発明の目的〕[Purpose of the invention]

本発明は上記実情に鑑みてなされたもので、電源ノイズ
が生じないような対策を回路的に施こすことによシ、種
々の誤動作等を防止し得る半導体回路を提供しようとす
るものである。The present invention has been made in view of the above circumstances, and aims to provide a semiconductor circuit that can prevent various malfunctions by taking circuit measures to prevent power supply noise from occurring. .

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するために、トランジスタをい
くつかのトランジスタの並列配置構造とし、これらトラ
ンジスタの電極と電源間に許容電流値の異なると一一ズ
を直列接続するととにより、大電流が流れた時、順次各
ヒユーズが切断し、それに接続するトランジスタが機能
を失っていき、結果として成る値以上の大電流が流れ得
ない構造としたものである。In order to achieve the above object, the present invention has a structure in which several transistors are arranged in parallel, and transistors with different allowable current values are connected in series between the electrodes of these transistors and the power supply, thereby generating a large current. When the current flows, each fuse is sequentially disconnected and the transistors connected to it lose their functions, so that a large current larger than the resulting value cannot flow.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例を説明する。第２
図においてＴ！、Ｔｌｌ、・・・Ｔｎは、ｒ−ト入力ど
うし及びドレイン出力端どうしをそれぞれ共通にしたｎ
個のＭＯＳ　）ランノスタで、これらトランジスタ’ｒ
ｔ　、Ｔ２．・・・Ｔｎのディメンジョンは全てｗ／ｎ
である。トランジスタＴＩ＋Ｔ２．・・・Ｔｎのソース
端と電源端子ｊ１との間にはそれぞれヒユーズＦ！　ｔ
　ＦＩＩ　＋・・・Ｆｎが設けられ、これらヒユーズＦ
ｌ、Ｆ、、・・・Ｆｎの許容電流値はそれぞれＩｍ＆Ｘ
／”　ｒ　’　ｍ１ｌＸ／（”　Ｉ）　＋　””ｍａＸ
と設定されている。An embodiment of the present invention will be described below with reference to the drawings. Second
T in the figure! , Tll, .
MOS) In the runnostar, these transistors'r
t, T2. ...Tn's dimensions are all w/n
It is. Transistor TI+T2. ...A fuse F! is connected between the source end of Tn and the power supply terminal j1, respectively. t
FII +...Fn are provided, and these fuses F
The allowable current values of l, F,...Fn are Im&X, respectively.
/"r'm1lX/("I) + ""maX
is set.

第２図の構成において、プロセスパラメータｆの値が正
常であれば、全トランジスタＴＩ、ＴＬ・・Ｔｎのコン
ダクタンスの和は、 とな）、従って第２図の出力バッファを流れる電流は■
ｙｒｔａ工であシ、問題はない。In the configuration shown in Figure 2, if the value of the process parameter f is normal, the sum of the conductances of all transistors TI, TL...Tn is () Therefore, the current flowing through the output buffer in Figure 2 is
It's a YRTA engineer, no problem.

もしプロセスのばらつきによシ １ｍ＊ｘ〈■＜　　　　ＩｍｍＸ −１ の電流が全トランジスタに流れたとする。この時各トラ
ンゾスタＴｌ　ｅ　ＴＲ＋・・・ＴｎＫｉｌ：の電流が
流れることになシ、トランジスタＴＩに接続されている
ヒーーズＦｌが切断する。従ってトランジスタＴ、はそ
の機能を失ない、トランジスタの個数はｎ個から”ｎ−
１”個に減少する。従って全トランジスタを流れる電流
は（ｎ　−１）／ｎ倍に減少し、 つまり ５− −１ ”　ＩｎａＸ　＜　Ｉ　＜　’　ｍｌＸとなる。即ち全
トランジスタに流れる電流値は■ｍ□以下であるため、
電源にノイズは誘起されない。Suppose that a current of 1m*x<■<ImmX-1 flows through all transistors due to process variations. At this time, no current flows through each transistor Tl e TR+ . . . TnKil:, and the heater Fl connected to the transistor TI is cut off. Therefore, the transistor T does not lose its function, and the number of transistors increases from n to "n-
Therefore, the current flowing through all the transistors decreases by a factor of (n-1)/n, that is, 5--1'' InaX < I <' mlX. In other words, since the current value flowing through all transistors is less than ■m□,
No noise is induced in the power supply.

更に大きな電流 −Ｉ　ｍｉｘ　＜　Ｉ　＜　−Ｉ　ｒＱ、ｘ−Ｉｎ−２ が全トランジスタに流れたとする。この時各トランジス
タＴ１ｙＴ！＋・・・Ｔｎにはの電流が流れることにな
シ、トランジスタＴＩ＋Ｔ、に接続されているヒ＝−ズ
Ｆ　１　＋　Ｆ　１　　が切断する。従ってトランジス
タの個数はｎ個から“ｎ　−２”個に減少するため１、
全トランジスタを流れる電流Ｕ（ｎ−２）／ｎ　倍に減
少しつ壕シ ６− となる。即ち全トランジスタを流れる電流値はＩ　ｍ１
ｌＸ以下であるため、やはシこの場合も電源にノイズは
誘起されない。Suppose that an even larger current -I mix < I < -I rQ, x-In-2 flows through all transistors. At this time, each transistor T1yT! +...Tn does not allow a current to flow through it, but the fuse F 1 +F 1 connected to the transistor TI+T disconnects it. Therefore, the number of transistors decreases from n to “n −2”, so 1,
The current flowing through all the transistors decreases by a factor of U(n-2)/n, resulting in a current of 6-. In other words, the current value flowing through all transistors is I m1
Since it is less than 1X, no noise is induced in the power supply even in this case.

更に大きな電流が全トランジスタに流れた時も、同様に
してＴ１　＋　Ｔ！　＊　Ｔ３に接続されているヒーー
ズが切断し、電源にノイズが誘起されることはない。Similarly, when a larger current flows through all transistors, T1 + T! *The heater connected to T3 is disconnected and no noise is induced in the power supply.

以下同様にして、プロセスの変動によりｆＯ値が変化し
、いかに大きな電流が流れる可能性が住じても、適当な
本数のヒユーズが切断することにより、決して電源にノ
イズを誘起するｌユどの電流は流れ得ないようにするこ
とができるものである。In the same way, no matter how large the current may flow as the fO value changes due to process variations, if an appropriate number of fuses are blown, the current will never induce noise in the power supply. can be prevented from flowing.

なお本発明は上記実施例に限られることなく種々の応用
が可能である。例えば上記の表穴は、説明上便宜的に用
いたものであ）、各トランジスタに接続されているヒー
ーズの許容電流値などは、決して上記の表穴どう漫の正
確な値が要求されるものではなく、おおむね上記の如き
傾向に合致していればよい。またヒユーズの許容電流値
を各ヒユーズ毎に変化させるには、ヒユーズとして用い
る材料の形状２寸法などを設定することにより可能であ
る。Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, the above table hole is used for convenience of explanation), and the permissible current value of the heater connected to each transistor does not require accurate values of the above table hole width. Rather, it suffices if it roughly matches the above trends. Further, the allowable current value of the fuse can be changed for each fuse by setting the shape, two dimensions, etc. of the material used for the fuse.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、ヒユーズ切断により
成る値以上の大電流が流れ得にい構造としたので、電源
ノイズの誘起が防止でき、誤動作などの生じることのな
い半導体回路が提供できるものである。As explained above, according to the present invention, the structure is such that it is difficult to allow a large current to flow in excess of the value caused by blowing a fuse, so that it is possible to prevent the induction of power supply noise and provide a semiconductor circuit that does not cause malfunctions. It is.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は出力トランジスタ回路図、第２図は本発明の一
実施例の回路図である。 Ｔ　１　”−Ｔｎ・・・ＭＯＳ　）ランノスタ、Ｆ！〜
Ｆｎ・・・ヒユーズ、１１・・・電源端子。FIG. 1 is a circuit diagram of an output transistor, and FIG. 2 is a circuit diagram of an embodiment of the present invention. T 1 ”-Tn...MOS) Rannosta, F! ~
Fn...fuse, 11...power terminal.

Claims (1)

【特許請求の範囲】[Claims] ダート入力どうし及びドレイン出力どうしをそれぞれ共
通にした複数のＭＯＳ　）ランジスタを設け、これら各
ＭＯ８トランジスタのソース端と電源との間に、互いに
許容電流値の異なるヒユーズを設けたことを特徴とする
半導体回路。A semiconductor characterized in that a plurality of MOS (MOS) transistors each having a common dirt input and a common drain output are provided, and a fuse having a different allowable current value is provided between the source end of each MO8 transistor and a power supply. circuit.
JP10715782A 1982-06-22 1982-06-22 Semiconductor circuit Pending JPS58223360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10715782A JPS58223360A (en) 1982-06-22 1982-06-22 Semiconductor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10715782A JPS58223360A (en) 1982-06-22 1982-06-22 Semiconductor circuit

Publications (1)

Publication Number Publication Date
JPS58223360A true JPS58223360A (en) 1983-12-24

Family

ID=14451939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10715782A Pending JPS58223360A (en) 1982-06-22 1982-06-22 Semiconductor circuit

Country Status (1)

Country Link
JP (1) JPS58223360A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0333733A1 (en) * 1986-11-13 1989-09-27 Concha Corporation Trimmable microminiature force-sensitive switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0333733A1 (en) * 1986-11-13 1989-09-27 Concha Corporation Trimmable microminiature force-sensitive switch

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