JPS58220472A - Charge detector - Google Patents

Charge detector

Info

Publication number
JPS58220472A
JPS58220472A JP10332382A JP10332382A JPS58220472A JP S58220472 A JPS58220472 A JP S58220472A JP 10332382 A JP10332382 A JP 10332382A JP 10332382 A JP10332382 A JP 10332382A JP S58220472 A JPS58220472 A JP S58220472A
Authority
JP
Japan
Prior art keywords
charge
electrode
voltage
main
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10332382A
Other languages
Japanese (ja)
Inventor
Tetsuo Yamada
哲生 山田
Nobuo Suzuki
信雄 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10332382A priority Critical patent/JPS58220472A/en
Publication of JPS58220472A publication Critical patent/JPS58220472A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices
    • H01L29/765Charge-coupled devices
    • H01L29/768Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76816Output structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To obtain a charge detector of wide dynamic range with high sensitivity by forming a sub capacity element row adjacent to a main capacity element on a semiconductor substrate and providing stepwise difference or a slope at the voltage produced by the main and sub elements. CONSTITUTION:Electrodes 21-27 of 2-layer structure are formed in an insulating layer 2 adjacent to a floating diffused layer 7, and the voltage of a power source 30 is divided by resistors 31-37 row and applied to them. In this case, the surface voltage of the substrate is decreased stepwisely from the electrode 21, and a voltage distribution P arises. When charge Q is transferred from a CCD to the voltage well of the layer 7 to store QS, the excess is sequentially filled in the regions 41-47 of the voltage well under the electrodes 21-27, CFD1,... are sequentially added to the capacity CFD0 of the layer 7, the sensitivity 1/CFD0 is gradually decreased, but the charge storage quantity is increased, thereby obtaining a wide dynamic range. When the voltage of a floating diffused layer 7 varies by DELTAVFO to the varied amount DELTAQS of the input signal change, the sensitivity is DELTAVFD/DELTAQS=1/CFD0, and the DFD6 is formed to small value. According to this configuration, a charge detector which has wide dynamic range with effectively high sensitivity can be obtained, and nonlinear conversion characteristics are suitably selected by the size of a sub capacity element or the like.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、たとえばカメラのオートフォーカス装置にお
けるコントラスト検出素子として用いられ、半導体基板
上で電荷信号入力を検出して電圧信号として出力するフ
ローティング容量形の電荷検出装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a floating capacitor type device which is used as a contrast detection element in an autofocus device of a camera, for example, and which detects a charge signal input on a semiconductor substrate and outputs it as a voltage signal. The present invention relates to a charge detection device.

〔発明の技術的背景〕[Technical background of the invention]

この種の従来の電荷検出装置としては、たとえば第1図
(邑)に示すようなフローティング拡散層形のものが知
られておシ、この装置は同一(共通)の半導体基板上に
形成された電荷結合装置(COD)から転送されてきた
電荷信号入力の検出に適している。すなわち、1はたと
えばP形の半導体基板、2は絶縁層、3および4は上記
絶縁層2内に形成されたCCD電極、5は上記CCD 
[極3.4に転送パルスを印加するための配線、6は絶
縁層2内に形成されて一定電圧が印加される出力ダート
電極、7は前記基板1の表面に形成されたフローティン
グ拡散層(n領域)、8は同じく基板表面に形成され基
準電圧電源16に電位設定されたリセットドレイン(n
”K散層)、9は上町リセットドレイン8と前記フロー
ティング拡蔽層2との間を電気的に断続するためのリセ
ッ)f−)電極であシ、絶縁層2内に形成されている。
As a conventional charge detection device of this type, a floating diffusion layer type device as shown in FIG. 1 is known, and this device is formed on the same (common) semiconductor substrate. It is suitable for detecting charge signal input transferred from a charge coupled device (COD). That is, 1 is, for example, a P-type semiconductor substrate, 2 is an insulating layer, 3 and 4 are CCD electrodes formed in the above-mentioned insulating layer 2, and 5 is the above-mentioned CCD.
[Wiring for applying a transfer pulse to the pole 3.4, 6 is an output dart electrode formed in the insulating layer 2 and to which a constant voltage is applied, 7 is a floating diffusion layer formed on the surface of the substrate 1 ( n region), 8 is a reset drain (n region) which is also formed on the substrate surface and whose potential is set to the reference voltage power supply 16.
9 is a reset (f-) electrode for electrically disconnecting between the Uemachi reset drain 8 and the floating diffusion layer 2, and is formed in the insulating layer 2.

17はソースフォロワ回路部であシ、これは絶縁層2内
に形成され、前記フローティング拡散層7の電位が与え
られる入カグート電極10と、基板10表面に形成され
直流電源15によシミ圧設定されたドレイン11と、出
力拡散層12と、抵抗素子13と、基板電位に接地され
るソース14とかリセットノ母ルスを印加する手段が設
けられている。
Reference numeral 17 denotes a source follower circuit section, which is formed in the insulating layer 2 and includes an input cathode electrode 10 to which the potential of the floating diffusion layer 7 is applied, and a source follower circuit section formed on the surface of the substrate 10 and used to set the stain pressure by a DC power supply 15. A drain 11, an output diffusion layer 12, a resistive element 13, a source 14 grounded to the substrate potential, and means for applying a reset pulse are provided.

次に、上記電荷検出装置の検出動作を第1図(b)の電
位分布図を参照して説明する。リセ、トグート電極9に
所定の高電圧のリセットノ9ルスが印加されると、この
電極9下の障壁電位は図示Paの如く深くなり、フロー
ティング拡散層7の電位がリセットドレイン8の電位に
設定される。そして、リセッ)?−)電極9が通常電位
に戻ると、この電極9下の障壁電位は図示PIの如く浅
くなシ、フローティング拡散層7は電気的に切υ離され
てフローティング状態になる。このため、CODから転
送されてきた電荷Qは、出力f−)電極6に印加された
電圧によシ出力ゲート電極6下のチャネルに形成された
電位障壁P1を越えてフローティング拡散層7へ流れ込
み、この流入電荷Q、によυフローティング拡散層7の
電位が変化する。この電位の変化がソースフォロワ回路
部17によシ出力信号電圧の変化として取り出される。
Next, the detection operation of the charge detection device will be explained with reference to the potential distribution diagram of FIG. 1(b). When a predetermined high voltage reset pulse is applied to the reset electrode 9, the barrier potential under this electrode 9 becomes deeper as shown in the figure Pa, and the potential of the floating diffusion layer 7 is set to the potential of the reset drain 8. be done. And reset)? -) When the electrode 9 returns to the normal potential, the barrier potential under the electrode 9 is not shallow as shown in PI, and the floating diffusion layer 7 is electrically separated and becomes a floating state. Therefore, the charge Q transferred from the COD flows into the floating diffusion layer 7 over the potential barrier P1 formed in the channel below the output gate electrode 6 due to the voltage applied to the output f-) electrode 6. , this inflow charge Q changes the potential of the floating diffusion layer 7. This potential change is extracted by the source follower circuit section 17 as a change in the output signal voltage.

上記電荷検出装置において、信号検出感度ηおよび最大
検出電荷量(ダイナミックレンジ)Q@rmxはそれぞ
れフローティング拡散層7が有する静電容量C,IJ(
図中01 + cm I am I C4の合計)で決
定され、次式に示すような関係を有する。
In the above charge detection device, the signal detection sensitivity η and the maximum detection charge amount (dynamic range) Q@rmx are the capacitances C and IJ(
01 + cm I am I C4 in the figure), and has a relationship as shown in the following formula.

Q@ n’laX = CFD  (VRD  −φ、
)         ・・・(2)但し、v8:信号電
圧 Q、:信号電荷 vRD=リセットドレイン8のt位 φB :出力ダート電極6下またはリセy)f)電極9
下の各チャネ ルミ位の内の高い方の電位。
Q@n'laX = CFD (VRD -φ,
) ...(2) However, v8: Signal voltage Q, : Signal charge vRD = t position of reset drain 8 φB : Below output dart electrode 6 or recess y) f) Electrode 9
The higher potential of each lower channel potential.

したがって、上式(1)、(2)から分るように、70
−ティング拡散層7の静電容量CFDを小さくすれば、
感度ηは高くなるがダイナミックレンジQ、maxは小
さくな9、逆に前記CFDを大きくすれば、感度ηは低
くなるがダイナミックレンジQ6烏Xは大きくなる。
Therefore, as seen from the above equations (1) and (2), 70
- If the capacitance CFD of the tinging diffusion layer 7 is reduced,
The sensitivity η becomes high but the dynamic range Q and max are small9.Conversely, if the CFD is increased, the sensitivity η becomes low but the dynamic range Q6 becomes large.

〔背景技術の問題点〕[Problems with background technology]

上述したように、従来の電荷検出装置は、感度特性とダ
イナミックレンジ特性とが相反関係にあり、高感度で広
いダイナミックレンジが要求される場合、たとえば画像
信号のコントラストを検出するために順次入力される信
号電荷を容X累子によシ加算して総和(積分)出力を検
出する場合には、前記従来の装置では実現不可能であっ
た。
As mentioned above, conventional charge detection devices have a conflicting relationship between sensitivity characteristics and dynamic range characteristics, and when high sensitivity and a wide dynamic range are required, for example, when the charge detection device is sequentially input to detect the contrast of an image signal. In the case of detecting the summation (integral) output by adding the signal charges of the capacitance X to the capacitor, it was impossible to realize this with the conventional device.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みて表されたもので、実効的に
高感度でダイナミックレンジが広く、複数個の信号電荷
束の加算出力回路とが非線形増幅回路等に好適する電荷
検出装置を提供するものである。
The present invention has been developed in view of the above circumstances, and provides a charge detection device that has effectively high sensitivity and a wide dynamic range, and whose addition output circuit for a plurality of signal charge fluxes is suitable for a nonlinear amplifier circuit, etc. It is something to do.

〔発明の概要〕[Summary of the invention]

すなわち、本発明の電荷検出装置は、半導体基板上に形
成された主容量素子に隣接して少なくとも1個の副容量
素子を設け、上記主容量素子および副容量素子に対応し
て半導体基板表面近傍に形成される電位に段差あるいは
傾斜を持たせるように副容量素子を形成したことな特徴
とするものである。
That is, in the charge detection device of the present invention, at least one sub-capacitance element is provided adjacent to a main capacitance element formed on a semiconductor substrate, and a portion near the surface of the semiconductor substrate is provided corresponding to the main capacitance element and the sub-capacitance element. The sub-capacitance element is characterized in that the sub-capacitance element is formed so that the potential formed therein has a step or a slope.

したがって、前記主容量素子に入力される信号電荷量の
増加に伴ってその一部が副各量素子へ移動し、仁の副容
量累子への電荷移動量は前記入力電荷量の増加に伴って
不連続的おるいは連続的に増加する。このためト1人力
電荷量が小さいときは副容量素子への電荷移動はなくて
感度が高く、つまシ実効感度が高く、電荷量が大きいと
きは副容量素子への電荷移動によシ広いダイナミックレ
ンジを有することになる。
Therefore, as the amount of signal charge input to the main capacitance element increases, part of it moves to the sub-capacitance element, and the amount of charge transferred to the sub-capacitance element increases as the amount of input charge increases. It increases discontinuously or continuously. Therefore, when the amount of charge is small, there is no charge transfer to the sub-capacitance element, resulting in high sensitivity, and the effective sensitivity is high, and when the amount of charge is large, there is no charge transfer to the sub-capacitance element, resulting in a wide dynamic range. It will have a range.

〔発明の実施−〕[Practice of the invention-]

以下、図面を参照して本発明の実施例を詳細に説明する
Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は、本発明を適用したフローラ(ング拡散層形電
荷検出装置の第1実施例を示すもので、同図(、)は平
面構成を概略的に示し、同図(b)は断面構造を概略的
に示し、同図(c)はチャネル電位の分布状態を示して
いる。第2図の電荷検出装置は、第1図を参照して前述
した電荷検出装置に比べて、フローティング拡散層7、
換言すれば主容量素子に隣接して副容量素子列を設け、
主容量素子および副容量素子列が形成する電位に段差を
持たせるようにした点が異なシ・その他は同じであるか
ら第2図中第1図と同一部分は同一符号を付してその説
明を省略する。
FIG. 2 shows a first embodiment of the Flora diffusion layer type charge detection device to which the present invention is applied. The structure is schematically shown, and FIG. 2(c) shows the channel potential distribution state.The charge detection device in FIG. 2 is different from the charge detection device described above with reference to FIG. layer 7,
In other words, a sub-capacitive element row is provided adjacent to the main capacitive element,
The difference is that the potentials formed by the main capacitance element and the sub-capacitance element row are made to have a step difference.Others are the same, so the same parts in Fig. 2 as in Fig. 1 are given the same reference numerals and explained. omitted.

上記副容量素子列は、絶縁層2内にメーパーラップした
二層構造で並設され、それぞれたとえば多結晶ポリシリ
コンで形成された複数の電極21〜27と、これらのM
O8形電極21〜27に電源3θの電圧を電圧分割抵抗
素子31〜37列で分割して得られる各分割電圧を対応
して印加する手段とから構成されている。この場合、主
容量素子に近い側の電極21から遠い側の電極27に向
って印加電圧が階段状の変化で小さくなシ、したがって
各電極21〜27下の半導体基板表面電位は電極21か
ら電極21に向って階段状の変化で小さくなシ、第2図
(、)に示すようなチャネル電位分布Pが得られる。
The above-mentioned sub-capacitance element array is arranged in parallel in a two-layered structure in which the sub-capacitance elements are mapped in the insulating layer 2, and each includes a plurality of electrodes 21 to 27 formed of, for example, polycrystalline polysilicon, and these M
It consists of means for applying each divided voltage obtained by dividing the voltage of the power source 3θ by the voltage dividing resistor elements 31 to 37 rows to the O8 type electrodes 21 to 27 in a corresponding manner. In this case, the applied voltage changes stepwise and becomes smaller from the electrode 21 on the side closer to the main capacitance element to the electrode 27 on the side farther from the main capacitor. 21, a channel potential distribution P as shown in FIG. 2 (,) is obtained.

次に、wJ2図の電荷検出装置の動作を説明する。先ず
、リセットr−)電極9にノヤルス電圧が印加され、フ
ローティング拡散層7がリセットドレイン8の電位に設
定されたのちフローテーイング状態になる。次に、出力
ダート電極6に電圧が印加され、この電極6下のチャネ
ルが開き、その電位障壁PIを越えてCODから信号電
荷Qがフローティング拡散層7に転送されてその電位井
戸の第2図(6)に示す領域40に蓄積される。この電
荷の蓄積は、フローティング拡散層7の固定電荷Q。に
加えられる。そして、CCD電極3.4のクロックパル
ス印加によ、9、CODから次々に信号電荷Qが拡散層
7に転送される場合には、第2図(c)に示すようにフ
ローティング拡散層7の電位井戸に電荷Q、が蓄積され
ると共K、過剰となった電荷が副容量素子の電極21〜
27下の電位井戸の領域41〜47をjI次満たしてい
く(図では44まで)ようになる。
Next, the operation of the charge detection device shown in Fig. wJ2 will be explained. First, a Noyals voltage is applied to the reset r-) electrode 9, and after the floating diffusion layer 7 is set to the potential of the reset drain 8, it enters a floating state. Next, a voltage is applied to the output dirt electrode 6, the channel under this electrode 6 opens, and the signal charge Q is transferred from the COD to the floating diffusion layer 7 over the potential barrier PI, as shown in the second diagram of the potential well. It is accumulated in the area 40 shown in (6). This charge accumulation is a fixed charge Q of the floating diffusion layer 7. added to. When the signal charges Q from 9 and COD are transferred to the diffusion layer 7 one after another by applying a clock pulse to the CCD electrode 3.4, the floating diffusion layer 7 is transferred as shown in FIG. 2(c). When charges Q and K are accumulated in the potential well, the excess charges are transferred to the electrodes 21 to 21 of the sub-capacitance element.
The potential well regions 41 to 47 below 27 are filled to the jI order (up to 44 in the figure).

仁の場合、・入力信号電荷量が小さいときに、信号電荷
が前記領域40に蓄積されている状態での信号電荷蓋の
変化ΔQ8に対するフローティング拡散層7の電位変化
Δv、Dは、フローティング拡散層7が有する静電容量
CFD(lの逆数で与えられる。すなわち、感度は次式
で示される。
When the input signal charge amount is small, the potential change Δv, D of the floating diffusion layer 7 with respect to the change ΔQ8 in the signal charge cap in a state where the signal charge is accumulated in the region 40 is the floating diffusion layer 7 has a capacitance CFD (given by the reciprocal of l. That is, the sensitivity is expressed by the following formula.

したがって、上記容量CFDOが小さければ大きな感度
が得られる。そして、前述したように拡散層7の蓄積電
荷Q、が増加して電極21下の電位井戸の領域411で
蓄積電荷が広がると、電極21とチャネルとの間の静電
容量CFDIが新九に加わシ、感度は となる・さらに、蓄積電荷が領域42〜47.へと順次
広がると、各電極22〜27と各チャネルとの間の静電
容量CFDI ’= CFDが順次加わり、感度は ・・・(5) ΣCFDn H=Q となって、徐々に低下する。
Therefore, if the capacitance CFDO is small, high sensitivity can be obtained. As described above, when the accumulated charge Q in the diffusion layer 7 increases and the accumulated charge spreads in the potential well region 411 under the electrode 21, the capacitance CFDI between the electrode 21 and the channel increases to a new value. When the charge is added, the sensitivity becomes ・Furthermore, the accumulated charges are in the regions 42 to 47. When the capacitance CFDI'=CFD between each electrode 22 to 27 and each channel is sequentially increased, the sensitivity becomes...(5) ΣCFDn H=Q and gradually decreases.

これに対して、信号電荷蓄積量は、上述したj5に静電
容量CFD、〜CFD、が順次加わる毎に大きくなシ、
静電容量CFD6〜CFD?の全体で非常に広いダイナ
ミックレンジが得られる。上述したような静電容量CF
De〜CFD?の関係は第3図の等価回路で示される。
On the other hand, the signal charge accumulation amount increases as the capacitance CFD, ~CFD, is sequentially added to j5 described above.
Capacitance CFD6~CFD? A very wide dynamic range can be obtained throughout. Capacitance CF as mentioned above
De~CFD? The relationship is shown in the equivalent circuit of FIG.

すなわち、先ずリセットゲート電極9下のチャネルに相
当するスイッチR8が一時メンになってCFDOがリセ
ット用電源16の電位に設定され、次に入力信号電荷Q
がC++FDO に蓄積され始め、この蓄積につれて電極21〜27下の
チャネルに相当するスイッチsw1〜SW。
That is, first, the switch R8 corresponding to the channel under the reset gate electrode 9 is temporarily turned on and CFDO is set to the potential of the reset power supply 16, and then the input signal charge Q
begins to accumulate in C++FDO, and as this accumulation occurs, switches sw1-SW corresponding to the channels below electrodes 21-27.

が順次閉じてCFDI〜CFD7が順次並列に接続さ゛
れてい〈。なお、E1〜E、は前記′抵抗素子31〜3
7列の各分割電圧に相当する。
are closed sequentially, and CFDI to CFD7 are sequentially connected in parallel. In addition, E1 to E are the above-mentioned 'resistance elements 31 to 3.
This corresponds to each divided voltage in seven columns.

上述したような電荷蓄積に伴なうフローティング拡散層
7の電位変化は、従来と同様にソースツメロワ回路部1
7によシミ圧変化信号に変換されて外部に取シ出される
。ここで、第2図の電荷検出装置の信号電荷入力対電圧
信号出力特性の一例を第4図に示す。すなわち、前述し
たように静電容i c、D□〜CFD?が順次接続され
る入力信号電荷区間毎に入出力特性の傾斜(感度)が小
さくなシ、全体として非線形特性を呈している。
The potential change of the floating diffusion layer 7 due to charge accumulation as described above is caused by the source lower circuit section 1 as in the conventional case.
7, it is converted into a stain pressure change signal and taken out to the outside. Here, an example of the signal charge input versus voltage signal output characteristics of the charge detection device shown in FIG. 2 is shown in FIG. That is, as mentioned above, the capacitance i c, D□~CFD? The slope (sensitivity) of the input/output characteristic is small for each input signal charge section to which the input signal charge sections are sequentially connected, and the overall characteristic is nonlinear.

ところで、一般に信号電荷の検出感度は、信号電荷量が
小さい場合に高いことが必要であシ、電荷量の増大と共
にその要請は小さくなる。すなわち、感度は小信号電荷
時の感度で表現できる。したがって、前記実施例の電荷
検出装置は、入力信号電荷量が小さいときに感度が高い
ので実効的に高感度であシ、しかも信号蓄積容量の最大
値が非常に大きくなるので飛躍的に広いダイナミックレ
ンジを実現できる。
By the way, in general, the detection sensitivity of signal charges needs to be high when the amount of signal charges is small, and this requirement becomes smaller as the amount of charges increases. That is, the sensitivity can be expressed as the sensitivity at the time of small signal charge. Therefore, the charge detection device of the above embodiment has high sensitivity when the amount of input signal charge is small, so it has effectively high sensitivity.Moreover, since the maximum value of the signal storage capacitance is very large, it has a dramatically wider dynamic range. Range can be realized.

第5図は、本発明の第2実施例に係る電荷検出装置の断
面構造を概略的に示すと共にそのチャネル電位の分布状
態を示している。この第2実施例は、前記第1実施例に
比べて、副容量素子として絶縁層2内に抵抗性電極50
を設けると共に、この電極50の拡散層7に近い側の一
端から他端へ向けて電源51から電1流■。を流して上
記電極50の2端子間に電位傾斜を形成するようにした
点、およびチャネル領域が半導体基板1と反対導電形の
n層から成る埋め込みチャネル52構造を用いた点が異
なる。このような構成によれば、上記電極50に対向す
る半導体基板表面近傍に、第5図中に示すように拡散層
7に近い側から遠い側に向って連続的にチャネル電位が
小さくなるような傾斜を有するチャネル電位分布Pが形
成される。したがって、フローティング拡散層7に入力
した信号電荷が増加するにつれて、拡散層7の電位井戸
の領域40に次いで電極50下のたとえば図示の領域5
3を連続的に満たし、さらに連続的に電極50下のより
広い領域を満たしていくようになる。図では電極50下
の電位井戸を左側から右側へ満たしていくよう忙なる。
FIG. 5 schematically shows the cross-sectional structure of a charge detection device according to a second embodiment of the present invention, and also shows the distribution state of its channel potential. This second embodiment is different from the first embodiment in that a resistive electrode 50 is provided within the insulating layer 2 as a sub-capacitance element.
At the same time, a current (1) is applied from a power source 51 from one end of the electrode 50 near the diffusion layer 7 to the other end. The difference is that a potential gradient is formed between the two terminals of the electrode 50 by flowing a current, and that a buried channel 52 structure is used in which the channel region is composed of an n-layer having a conductivity type opposite to that of the semiconductor substrate 1. According to such a configuration, a channel potential is formed in the vicinity of the surface of the semiconductor substrate facing the electrode 50 such that the channel potential decreases continuously from the side close to the diffusion layer 7 to the side far away from the diffusion layer 7, as shown in FIG. A channel potential distribution P having a slope is formed. Therefore, as the signal charge input to the floating diffusion layer 7 increases, the potential well region 40 of the diffusion layer 7 is followed by the region 5 below the electrode 50, as shown in the figure.
3 is continuously filled, and a wider area under the electrode 50 is further continuously filled. In the figure, the potential well below the electrode 50 is filled from left to right.

この過程において、if実施例と同様に検出感度は徐々
に低下し、広いダイナミックレンジが実現される。この
場合、第2寅施例の入出力特性は第6図に示すように滑
らかな非線形性を呈し、感度が連続的に変化する点で第
1実施例の入出力特性とは若干異なる。なお、第2実施
例の感度は次式で示される。
In this process, the detection sensitivity gradually decreases as in the if embodiment, and a wide dynamic range is realized. In this case, the input/output characteristics of the second embodiment exhibit smooth nonlinearity as shown in FIG. 6, and are slightly different from the input/output characteristics of the first embodiment in that the sensitivity changes continuously. Note that the sensitivity of the second embodiment is expressed by the following equation.

但し、ΔCFDは電極60下のチャネルとの間の単位長
さ当シの静電容量、tは上記チャネルの静電容量対向部
分の長さである。
However, ΔCFD is the capacitance per unit length between the channel under the electrode 60 and t is the length of the capacitance opposing portion of the channel.

第7図は、本発明の第3実施例に係る電荷検出装置を示
すもので、これは副答tht素子として一定の虐定電圧
が印加される単一の電極70を絶縁層2内に形成すると
共に、このMO8形電極70に対向する半導体基板表面
に各々不純物濃度が異なるn形不純物層71,72,7
Jを形成し、この不純物濃度の差によりヂャネル内に図
示の如く拡散層7から遠のくにつれて階段的に電位が小
さくなるような電位分布Pを形成するようにした点が前
記各実施例と異なる。このような構成によれば、拡散層
1に入力する電荷が増加するにつれて図示の如く領域4
0.’14゜75・・・tI@次満たしていくので、第
1実施例に準じた入出力特性が得られる。この第3実施
例によれは、電極70の形成およびその電圧供給が簡単
であるという特長がある0 第8図は、本発明の第4拠m例に係るフローティングf
−)形電荷検出装置管示すもので、その%徴は電荷を検
出する主容量素子としてフローティングf−)構造を用
いている点にあり、その他は第1実施例とほぼ同様であ
る。すなわち、絶縁層2内にフローティングダート電極
goを形成し、このダート電極80をソースフ  ゛オ
ロワ回路部170入力グートに接続し、上記フローティ
ングゲート電極80を予め所定電位に設定するためのリ
セッ11”−)回路85を設けている。このような構成
によれば、フローティングe−)電極80下のチャネル
に入力される電荷量の増加につれてこのff−)電極8
0の電位が湾動すると共に、電極21〜25下の階段状
電位分布Pに応じて電荷の蓄積領域81〜85が順次広
がっていくので、第1実施例に準じた入出力特性が得ら
れる@但し、第4実施例では、フ四−ティングe−)電
極80とチャネルとの間の静電容量と、チャネルが有す
る静電容量との比によって検出感度が定まる。
FIG. 7 shows a charge detection device according to a third embodiment of the present invention, in which a single electrode 70 to which a constant abuse voltage is applied is formed in the insulating layer 2 as a sub-response tht element. At the same time, n-type impurity layers 71, 72, 7 having different impurity concentrations are formed on the surface of the semiconductor substrate facing the MO8-type electrode 70.
This embodiment differs from the previous embodiments in that the difference in impurity concentration forms a potential distribution P in the channel in which the potential decreases stepwise as the distance from the diffusion layer 7 increases as shown in the figure. According to such a configuration, as the charge input to the diffusion layer 1 increases, the area 4 increases as shown in the figure.
0. Since '14°75...tI@' is satisfied, input/output characteristics similar to those of the first embodiment can be obtained. This third embodiment has the advantage that the formation of the electrode 70 and the voltage supply thereto are simple. FIG.
-) type charge detection device, the main feature of which is that a floating f-) structure is used as the main capacitance element for detecting charge, and other aspects are substantially the same as those of the first embodiment. That is, a floating dirt electrode go is formed in the insulating layer 2, this dirt electrode 80 is connected to the input gate of the source follower circuit section 170, and a reset gate 11'' is used to set the floating gate electrode 80 to a predetermined potential in advance. ) circuit 85 is provided. According to such a configuration, as the amount of charge input to the channel under the floating e-) electrode 80 increases, this ff-) circuit 85 increases.
As the zero potential shifts, the charge accumulation regions 81 to 85 gradually expand in accordance with the stepped potential distribution P below the electrodes 21 to 25, so that input/output characteristics similar to the first embodiment can be obtained. However, in the fourth embodiment, the detection sensitivity is determined by the ratio of the capacitance between the electrode 80 and the channel and the capacitance of the channel.

なお、本発明の電荷検出装置を実現するための製造工程
としては、たとえば通常のCCD製造工程を用いれは容
易であシ、COD 勢の電荷転送=−と−Q :f−j
町−の半導体基板上に形成することができるので好都合
である。
Incidentally, as a manufacturing process for realizing the charge detection device of the present invention, it is easy to use, for example, a normal CCD manufacturing process.
This is advantageous because it can be formed on an ordinary semiconductor substrate.

また、前記各実施例は、信号電荷として電子を用いるれ
チャネル形構造を示したが、これらに対して不純物を逆
導電形に変更すると共に印加電圧の極性を逆に変更する
ことにょシ、正孔をキャリアとしたpチャネル形構造と
しても、前記実施例と同様な効果が得られることは勿論
である。
In addition, although each of the above embodiments shows a channel type structure using electrons as signal charges, it is possible to change the impurity to the opposite conductivity type and to reverse the polarity of the applied voltage. It goes without saying that the same effects as in the above embodiments can be obtained even with a p-channel structure in which holes are used as carriers.

〔発明の効果〕〔Effect of the invention〕

上述したように本発明のフローティング容量形(フロー
ティング拡散層形、フローティングゲート形を含む)電
荷検出装置によれば、実効的に高感度でダイナミックレ
ンジが広く、しかも入力電荷対出力電圧の非線形変換特
性は副容つゝ 量素子の寸法形状とか電極数とが電極印加電圧等を適宜
選択することによシ多種多様な設定が可能である。
As described above, the floating capacitance type (including floating diffusion layer type and floating gate type) charge detection device of the present invention has effectively high sensitivity and a wide dynamic range, and also has nonlinear conversion characteristics of input charge to output voltage. A wide variety of settings can be made by appropriately selecting the size and shape of the subcapacitance element, the number of electrodes, and the voltage applied to the electrodes.

したがって、特に複数の信号電荷入力の総和を求めると
共に非線形増幅(あるいは圧縮)を行なうために本発明
装置を用いた場合忙は、広いダイナミックレンジで信号
を検出しながら非線形変換を同時に行なうことができる
ので非常に有効である。
Therefore, especially when the device of the present invention is used to calculate the sum of multiple signal charge inputs and perform nonlinear amplification (or compression), it is possible to simultaneously perform nonlinear conversion while detecting signals over a wide dynamic range. Therefore, it is very effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は従来の電荷検出、装置の概略的
断面構造、チャネル電位分布を説明するために示す図、
第2図は本発明に係る電荷検出装置の第1実施例を示す
もので、同図(、) 、 (b) 、 (c)は概略的
平面構成、概略的断面構造、チャネル電位分布を説明す
るために示す図、第3図は第2図の要部の等価回路を示
す図、第4図は第2図の装置の入出力特性を示す図、第
5図は本発明の第2実施例に係る概略的断面構造および
チャネル電位分布を示す図、第6図は第5図の装置の入
出力特性を示す図、第7図および第8図はそれぞれ本発
明の第3実施例および第4実施例に係□る概略的断面構
造およびチャネル電位分布を示す図である。 1・・・半導体基板、2・・・絶縁層、3.4・・・C
CD電極、6・・・出力f−)電極、7・・・フローテ
ィング拡散層、8・・・リセットドレイン、9・・・リ
セ、トff−ト電極、17・・・ソースツメロワ回路部
、21〜27.70・・・MO8形電極、16.301
51・・・電源、31〜37・・・抵抗、50・・・抵
抗性電極、80・・・フローティングr−)電極、86
・・・リセットダート回路、40.41〜44゜53.
74,76、III〜84・・・電荷蓄積領域、P・・
・チャネル電位分布(電位井戸分布)、Q・・・入力電
荷、Q、・・・蓄積電荷、Qo・・・固定電荷。 出願人代理人  弁理士 鈴 江 武 彦1 。 1[1図 (a) (b) 第5図    J1′s重電荷− υ 福+電荷−− 第7図
FIGS. 1(a) and 1(b) are diagrams shown to explain conventional charge detection, a schematic cross-sectional structure of the device, and channel potential distribution,
FIG. 2 shows a first embodiment of the charge detection device according to the present invention, and FIG. 3 is a diagram showing the equivalent circuit of the main part of FIG. 2, FIG. 4 is a diagram showing the input/output characteristics of the device in FIG. 2, and FIG. 5 is a diagram showing the second embodiment of the present invention. FIG. 6 is a diagram showing the input/output characteristics of the device of FIG. 5, and FIGS. FIG. 4 is a diagram showing a schematic cross-sectional structure and channel potential distribution according to Example 4. 1... Semiconductor substrate, 2... Insulating layer, 3.4... C
CD electrode, 6... Output f-) electrode, 7... Floating diffusion layer, 8... Reset drain, 9... Reset, top electrode, 17... Source lower circuit section, 21- 27.70...MO8 type electrode, 16.301
51... Power supply, 31-37... Resistance, 50... Resistive electrode, 80... Floating r-) electrode, 86
...Reset dirt circuit, 40.41~44°53.
74, 76, III-84...charge accumulation region, P...
- Channel potential distribution (potential well distribution), Q...input charge, Q...accumulated charge, Qo...fixed charge. Applicant's agent: Patent attorney Takehiko Suzue1. 1 [Figure 1 (a) (b) Figure 5 J1's heavy charge - υ Fuku + charge - Figure 7

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板上に形成された主容量素子と、この主
容量素子に電荷を入力する入力手段と、前記主容量素子
を断続的に所定電位に設定する手段と、前記主容量素子
に隣接して少なくとも1個形成され前記入力手段から前
記主容量素子に入力される信号電荷の増加に伴なって移
動してくる一部の電荷を蓄積し、この信号電荷の増加に
伴なって不連続あるいは連続的に蓄積電荷が増加する副
容量累子と、前記主容量素子の電位変化管取υ出す手段
とを具備することを特徴とする電荷検出装置。
(1) A main capacitive element formed on a semiconductor substrate, an input means for inputting charge to the main capacitive element, a means for intermittently setting the main capacitive element to a predetermined potential, and a main capacitive element adjacent to the main capacitive element. The main capacitance element is formed with at least one capacitive element, and stores a portion of the charge that moves as the signal charge increases, which is input from the input means to the main capacitance element, and discontinuously moves as the signal charge increases. Alternatively, a charge detection device characterized by comprising a sub-capacitance resistor in which accumulated charge increases continuously, and means for taking out a potential change tube of the main capacitance element.
(2)前記副容量素子は、複数個のMO8形電極と、こ
の各電極に相異なる電圧を印加する電圧印加手段とを具
備し、前記各電極に絶縁層を介して対向する半導体基板
表面近傍に階段状電位井戸を形成してなることを特徴と
する特許請求の範囲第1項記載の電荷検出装置。
(2) The sub-capacitance element includes a plurality of MO8 type electrodes and voltage application means for applying different voltages to each of the electrodes, and is located near the surface of the semiconductor substrate facing each of the electrodes with an insulating layer interposed therebetween. 2. The charge detection device according to claim 1, wherein a stepped potential well is formed in the charge detection device.
(3)前記副容量素子は、1個のMOB形電極と、この
電極に所定の電圧を印加する電圧印加手段と、前記電極
に絶縁層を介して対向する半導体基板表面に形成され各
々不純物濃度が異なる複数の不純物層とを具備すること
を特徴とする特許請求の範囲第1項記載の電荷検出装置
(3) The sub-capacitance element includes one MOB type electrode, a voltage applying means for applying a predetermined voltage to the electrode, and an impurity concentration formed on the surface of the semiconductor substrate facing the electrode via an insulating layer. 2. The charge detection device according to claim 1, further comprising a plurality of impurity layers having different impurity levels.
(4)前記副容量素子は、半導体基板表面上の絶縁層内
に形成された1個の抵抗性電極と、この電極の両端間に
電流を流す手段とを具備し、前記電極に対向する半導体
基板表面近傍に傾斜状電位井戸を形成してなることを特
徴とする特許請求の範囲第1項記載の電荷検出装置。
(4) The auxiliary capacitance element includes one resistive electrode formed in an insulating layer on the surface of a semiconductor substrate, and means for passing a current between both ends of this electrode, and a semiconductor device facing the electrode. 2. The charge detection device according to claim 1, wherein an inclined potential well is formed near the surface of the substrate.
JP10332382A 1982-06-16 1982-06-16 Charge detector Pending JPS58220472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10332382A JPS58220472A (en) 1982-06-16 1982-06-16 Charge detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10332382A JPS58220472A (en) 1982-06-16 1982-06-16 Charge detector

Publications (1)

Publication Number Publication Date
JPS58220472A true JPS58220472A (en) 1983-12-22

Family

ID=14350977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10332382A Pending JPS58220472A (en) 1982-06-16 1982-06-16 Charge detector

Country Status (1)

Country Link
JP (1) JPS58220472A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166561A (en) * 1987-12-22 1989-06-30 Nec Corp Charge transfer device
WO2009049808A1 (en) * 2007-10-11 2009-04-23 Max-Planck-Gesellschaft Zur F\Rderung Der Wissenschaften E.V. Depfet transistor having a large dynamic range

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166561A (en) * 1987-12-22 1989-06-30 Nec Corp Charge transfer device
WO2009049808A1 (en) * 2007-10-11 2009-04-23 Max-Planck-Gesellschaft Zur F\Rderung Der Wissenschaften E.V. Depfet transistor having a large dynamic range
US8461635B2 (en) 2007-10-11 2013-06-11 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. DEPFET transistor having a large dynamic range

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