JPS58220472A - Charge detector - Google Patents

Abstract

PURPOSE:To obtain a charge detector of wide dynamic range with high sensitivity by forming a sub capacity element row adjacent to a main capacity element on a semiconductor substrate and providing stepwise difference or a slope at the voltage produced by the main and sub elements. CONSTITUTION:Electrodes 21-27 of 2-layer structure are formed in an insulating layer 2 adjacent to a floating diffused layer 7, and the voltage of a power source 30 is divided by resistors 31-37 row and applied to them. In this case, the surface voltage of the substrate is decreased stepwisely from the electrode 21, and a voltage distribution P arises. When charge Q is transferred from a CCD to the voltage well of the layer 7 to store QS, the excess is sequentially filled in the regions 41-47 of the voltage well under the electrodes 21-27, CFD1,... are sequentially added to the capacity CFD0 of the layer 7, the sensitivity 1/CFD0 is gradually decreased, but the charge storage quantity is increased, thereby obtaining a wide dynamic range. When the voltage of a floating diffused layer 7 varies by DELTAVFO to the varied amount DELTAQS of the input signal change, the sensitivity is DELTAVFD/DELTAQS=1/CFD0, and the DFD6 is formed to small value. According to this configuration, a charge detector which has wide dynamic range with effectively high sensitivity can be obtained, and nonlinear conversion characteristics are suitably selected by the size of a sub capacity element or the like.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a floating capacitor type device which is used as a contrast detection element in an autofocus device of a camera, for example, and which detects a charge signal input on a semiconductor substrate and outputs it as a voltage signal. The present invention relates to a charge detection device.

[Technical background of the invention]

As a conventional charge detection device of this type, a floating diffusion layer type device as shown in FIG. 1 is known, and this device is formed on the same (common) semiconductor substrate. It is suitable for detecting charge signal input transferred from a charge coupled device (COD). That is, 1 is, for example, a P-type semiconductor substrate, 2 is an insulating layer, 3 and 4 are CCD electrodes formed in the above-mentioned insulating layer 2, and 5 is the above-mentioned CCD.
[Wiring for applying a transfer pulse to the pole 3.4, 6 is an output dart electrode formed in the insulating layer 2 and to which a constant voltage is applied, 7 is a floating diffusion layer formed on the surface of the substrate 1 ( n region), 8 is a reset drain (n region) which is also formed on the substrate surface and whose potential is set to the reference voltage power supply 16.
9 is a reset (f-) electrode for electrically disconnecting between the Uemachi reset drain 8 and the floating diffusion layer 2, and is formed in the insulating layer 2.

Reference numeral 17 denotes a source follower circuit section, which is formed in the insulating layer 2 and includes an input cathode electrode 10 to which the potential of the floating diffusion layer 7 is applied, and a source follower circuit section formed on the surface of the substrate 10 and used to set the stain pressure by a DC power supply 15. A drain 11, an output diffusion layer 12, a resistive element 13, a source 14 grounded to the substrate potential, and means for applying a reset pulse are provided.

Next, the detection operation of the charge detection device will be explained with reference to the potential distribution diagram of FIG. 1(b). When a predetermined high voltage reset pulse is applied to the reset electrode 9, the barrier potential under this electrode 9 becomes deeper as shown in the figure Pa, and the potential of the floating diffusion layer 7 is set to the potential of the reset drain 8. be done. And reset)? -) When the electrode 9 returns to the normal potential, the barrier potential under the electrode 9 is not shallow as shown in PI, and the floating diffusion layer 7 is electrically separated and becomes a floating state. Therefore, the charge Q transferred from the COD flows into the floating diffusion layer 7 over the potential barrier P1 formed in the channel below the output gate electrode 6 due to the voltage applied to the output f-) electrode 6. , this inflow charge Q changes the potential of the floating diffusion layer 7. This potential change is extracted by the source follower circuit section 17 as a change in the output signal voltage.

In the above charge detection device, the signal detection sensitivity η and the maximum detection charge amount (dynamic range) Q@rmx are the capacitances C and IJ(
01 + cm I am I C4 in the figure), and has a relationship as shown in the following formula.

Q@n'laX = CFD (VRD -φ,
) ...(2) However, v8: Signal voltage Q, : Signal charge vRD = t position of reset drain 8 φB : Below output dart electrode 6 or recess y) f) Electrode 9
The higher potential of each lower channel potential.

Therefore, as seen from the above equations (1) and (2), 70
- If the capacitance CFD of the tinging diffusion layer 7 is reduced,
The sensitivity η becomes high but the dynamic range Q and max are small9.Conversely, if the CFD is increased, the sensitivity η becomes low but the dynamic range Q6 becomes large.

[Problems with background technology]

As mentioned above, conventional charge detection devices have a conflicting relationship between sensitivity characteristics and dynamic range characteristics, and when high sensitivity and a wide dynamic range are required, for example, when the charge detection device is sequentially input to detect the contrast of an image signal. In the case of detecting the summation (integral) output by adding the signal charges of the capacitance X to the capacitor, it was impossible to realize this with the conventional device.

[Purpose of the invention]

The present invention has been developed in view of the above circumstances, and provides a charge detection device that has effectively high sensitivity and a wide dynamic range, and whose addition output circuit for a plurality of signal charge fluxes is suitable for a nonlinear amplifier circuit, etc. It is something to do.

[Summary of the invention]

That is, in the charge detection device of the present invention, at least one sub-capacitance element is provided adjacent to a main capacitance element formed on a semiconductor substrate, and a portion near the surface of the semiconductor substrate is provided corresponding to the main capacitance element and the sub-capacitance element. The sub-capacitance element is characterized in that the sub-capacitance element is formed so that the potential formed therein has a step or a slope.

Therefore, as the amount of signal charge input to the main capacitance element increases, part of it moves to the sub-capacitance element, and the amount of charge transferred to the sub-capacitance element increases as the amount of input charge increases. It increases discontinuously or continuously. Therefore, when the amount of charge is small, there is no charge transfer to the sub-capacitance element, resulting in high sensitivity, and the effective sensitivity is high, and when the amount of charge is large, there is no charge transfer to the sub-capacitance element, resulting in a wide dynamic range. It will have a range.

[Practice of the invention-]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a first embodiment of the Flora diffusion layer type charge detection device to which the present invention is applied. The structure is schematically shown, and FIG. 2(c) shows the channel potential distribution state.The charge detection device in FIG. 2 is different from the charge detection device described above with reference to FIG. layer 7,
In other words, a sub-capacitive element row is provided adjacent to the main capacitive element,
The difference is that the potentials formed by the main capacitance element and the sub-capacitance element row are made to have a step difference.Others are the same, so the same parts in Fig. 2 as in Fig. 1 are given the same reference numerals and explained. omitted.

The above-mentioned sub-capacitance element array is arranged in parallel in a two-layered structure in which the sub-capacitance elements are mapped in the insulating layer 2, and each includes a plurality of electrodes 21 to 27 formed of, for example, polycrystalline polysilicon, and these M
It consists of means for applying each divided voltage obtained by dividing the voltage of the power source 3θ by the voltage dividing resistor elements 31 to 37 rows to the O8 type electrodes 21 to 27 in a corresponding manner. In this case, the applied voltage changes stepwise and becomes smaller from the electrode 21 on the side closer to the main capacitance element to the electrode 27 on the side farther from the main capacitor. 21, a channel potential distribution P as shown in FIG. 2 (,) is obtained.

Next, the operation of the charge detection device shown in Fig. wJ2 will be explained. First, a Noyals voltage is applied to the reset r-) electrode 9, and after the floating diffusion layer 7 is set to the potential of the reset drain 8, it enters a floating state. Next, a voltage is applied to the output dirt electrode 6, the channel under this electrode 6 opens, and the signal charge Q is transferred from the COD to the floating diffusion layer 7 over the potential barrier PI, as shown in the second diagram of the potential well. It is accumulated in the area 40 shown in (6). This charge accumulation is a fixed charge Q of the floating diffusion layer 7. added to. When the signal charges Q from 9 and COD are transferred to the diffusion layer 7 one after another by applying a clock pulse to the CCD electrode 3.4, the floating diffusion layer 7 is transferred as shown in FIG. 2(c). When charges Q and K are accumulated in the potential well, the excess charges are transferred to the electrodes 21 to 21 of the sub-capacitance element.
The potential well regions 41 to 47 below 27 are filled to the jI order (up to 44 in the figure).

When the input signal charge amount is small, the potential change Δv, D of the floating diffusion layer 7 with respect to the change ΔQ8 in the signal charge cap in a state where the signal charge is accumulated in the region 40 is the floating diffusion layer 7 has a capacitance CFD (given by the reciprocal of l. That is, the sensitivity is expressed by the following formula.

Therefore, if the capacitance CFDO is small, high sensitivity can be obtained. As described above, when the accumulated charge Q in the diffusion layer 7 increases and the accumulated charge spreads in the potential well region 411 under the electrode 21, the capacitance CFDI between the electrode 21 and the channel increases to a new value. When the charge is added, the sensitivity becomes ・Furthermore, the accumulated charges are in the regions 42 to 47. When the capacitance CFDI'=CFD between each electrode 22 to 27 and each channel is sequentially increased, the sensitivity becomes...(5) ΣCFDn H=Q and gradually decreases.

On the other hand, the signal charge accumulation amount increases as the capacitance CFD, ~CFD, is sequentially added to j5 described above.
Capacitance CFD6~CFD? A very wide dynamic range can be obtained throughout. Capacitance CF as mentioned above
De~CFD? The relationship is shown in the equivalent circuit of FIG.

That is, first, the switch R8 corresponding to the channel under the reset gate electrode 9 is temporarily turned on and CFDO is set to the potential of the reset power supply 16, and then the input signal charge Q
begins to accumulate in C++FDO, and as this accumulation occurs, switches sw1-SW corresponding to the channels below electrodes 21-27.

are closed sequentially, and CFDI to CFD7 are sequentially connected in parallel. In addition, E1 to E are the above-mentioned 'resistance elements 31 to 3.
This corresponds to each divided voltage in seven columns.

The potential change of the floating diffusion layer 7 due to charge accumulation as described above is caused by the source lower circuit section 1 as in the conventional case.
7, it is converted into a stain pressure change signal and taken out to the outside. Here, an example of the signal charge input versus voltage signal output characteristics of the charge detection device shown in FIG. 2 is shown in FIG. That is, as mentioned above, the capacitance i c, D□~CFD? The slope (sensitivity) of the input/output characteristic is small for each input signal charge section to which the input signal charge sections are sequentially connected, and the overall characteristic is nonlinear.

By the way, in general, the detection sensitivity of signal charges needs to be high when the amount of signal charges is small, and this requirement becomes smaller as the amount of charges increases. That is, the sensitivity can be expressed as the sensitivity at the time of small signal charge. Therefore, the charge detection device of the above embodiment has high sensitivity when the amount of input signal charge is small, so it has effectively high sensitivity.Moreover, since the maximum value of the signal storage capacitance is very large, it has a dramatically wider dynamic range. Range can be realized.

FIG. 5 schematically shows the cross-sectional structure of a charge detection device according to a second embodiment of the present invention, and also shows the distribution state of its channel potential. This second embodiment is different from the first embodiment in that a resistive electrode 50 is provided within the insulating layer 2 as a sub-capacitance element.
At the same time, a current (1) is applied from a power source 51 from one end of the electrode 50 near the diffusion layer 7 to the other end. The difference is that a potential gradient is formed between the two terminals of the electrode 50 by flowing a current, and that a buried channel 52 structure is used in which the channel region is composed of an n-layer having a conductivity type opposite to that of the semiconductor substrate 1. According to such a configuration, a channel potential is formed in the vicinity of the surface of the semiconductor substrate facing the electrode 50 such that the channel potential decreases continuously from the side close to the diffusion layer 7 to the side far away from the diffusion layer 7, as shown in FIG. A channel potential distribution P having a slope is formed. Therefore, as the signal charge input to the floating diffusion layer 7 increases, the potential well region 40 of the diffusion layer 7 is followed by the region 5 below the electrode 50, as shown in the figure.
3 is continuously filled, and a wider area under the electrode 50 is further continuously filled. In the figure, the potential well below the electrode 50 is filled from left to right.

In this process, the detection sensitivity gradually decreases as in the if embodiment, and a wide dynamic range is realized. In this case, the input/output characteristics of the second embodiment exhibit smooth nonlinearity as shown in FIG. 6, and are slightly different from the input/output characteristics of the first embodiment in that the sensitivity changes continuously. Note that the sensitivity of the second embodiment is expressed by the following equation.

However, ΔCFD is the capacitance per unit length between the channel under the electrode 60 and t is the length of the capacitance opposing portion of the channel.

FIG. 7 shows a charge detection device according to a third embodiment of the present invention, in which a single electrode 70 to which a constant abuse voltage is applied is formed in the insulating layer 2 as a sub-response tht element. At the same time, n-type impurity layers 71, 72, 7 having different impurity concentrations are formed on the surface of the semiconductor substrate facing the MO8-type electrode 70.
This embodiment differs from the previous embodiments in that the difference in impurity concentration forms a potential distribution P in the channel in which the potential decreases stepwise as the distance from the diffusion layer 7 increases as shown in the figure. According to such a configuration, as the charge input to the diffusion layer 1 increases, the area 4 increases as shown in the figure.
0. Since '14°75...tI@' is satisfied, input/output characteristics similar to those of the first embodiment can be obtained. This third embodiment has the advantage that the formation of the electrode 70 and the voltage supply thereto are simple. FIG.
-) type charge detection device, the main feature of which is that a floating f-) structure is used as the main capacitance element for detecting charge, and other aspects are substantially the same as those of the first embodiment. That is, a floating dirt electrode go is formed in the insulating layer 2, this dirt electrode 80 is connected to the input gate of the source follower circuit section 170, and a reset gate 11'' is used to set the floating gate electrode 80 to a predetermined potential in advance. ) circuit 85 is provided. According to such a configuration, as the amount of charge input to the channel under the floating e-) electrode 80 increases, this ff-) circuit 85 increases.
As the zero potential shifts, the charge accumulation regions 81 to 85 gradually expand in accordance with the stepped potential distribution P below the electrodes 21 to 25, so that input/output characteristics similar to the first embodiment can be obtained. However, in the fourth embodiment, the detection sensitivity is determined by the ratio of the capacitance between the electrode 80 and the channel and the capacitance of the channel.

Incidentally, as a manufacturing process for realizing the charge detection device of the present invention, it is easy to use, for example, a normal CCD manufacturing process.
This is advantageous because it can be formed on an ordinary semiconductor substrate.

In addition, although each of the above embodiments shows a channel type structure using electrons as signal charges, it is possible to change the impurity to the opposite conductivity type and to reverse the polarity of the applied voltage. It goes without saying that the same effects as in the above embodiments can be obtained even with a p-channel structure in which holes are used as carriers.

〔Effect of the invention〕

As described above, the floating capacitance type (including floating diffusion layer type and floating gate type) charge detection device of the present invention has effectively high sensitivity and a wide dynamic range, and also has nonlinear conversion characteristics of input charge to output voltage. A wide variety of settings can be made by appropriately selecting the size and shape of the subcapacitance element, the number of electrodes, and the voltage applied to the electrodes.

Therefore, especially when the device of the present invention is used to calculate the sum of multiple signal charge inputs and perform nonlinear amplification (or compression), it is possible to simultaneously perform nonlinear conversion while detecting signals over a wide dynamic range. Therefore, it is very effective.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams shown to explain conventional charge detection, a schematic cross-sectional structure of the device, and channel potential distribution,
FIG. 2 shows a first embodiment of the charge detection device according to the present invention, and FIG. 3 is a diagram showing the equivalent circuit of the main part of FIG. 2, FIG. 4 is a diagram showing the input/output characteristics of the device in FIG. 2, and FIG. 5 is a diagram showing the second embodiment of the present invention. FIG. 6 is a diagram showing the input/output characteristics of the device of FIG. 5, and FIGS. FIG. 4 is a diagram showing a schematic cross-sectional structure and channel potential distribution according to Example 4. 1... Semiconductor substrate, 2... Insulating layer, 3.4... C
CD electrode, 6... Output f-) electrode, 7... Floating diffusion layer, 8... Reset drain, 9... Reset, top electrode, 17... Source lower circuit section, 21- 27.70...MO8 type electrode, 16.301
51... Power supply, 31-37... Resistance, 50... Resistive electrode, 80... Floating r-) electrode, 86
...Reset dirt circuit, 40.41~44°53.
74, 76, III-84...charge accumulation region, P...
- Channel potential distribution (potential well distribution), Q...input charge, Q...accumulated charge, Qo...fixed charge. Applicant's agent: Patent attorney Takehiko Suzue1. 1 [Figure 1 (a) (b) Figure 5 J1's heavy charge - υ Fuku + charge - Figure 7

Claims (4)

[Claims] (1) A main capacitive element formed on a semiconductor substrate, an input means for inputting charge to the main capacitive element, a means for intermittently setting the main capacitive element to a predetermined potential, and a main capacitive element adjacent to the main capacitive element. The main capacitance element is formed with at least one capacitive element, and stores a portion of the charge that moves as the signal charge increases, which is input from the input means to the main capacitance element, and discontinuously moves as the signal charge increases. Alternatively, a charge detection device characterized by comprising a sub-capacitance resistor in which accumulated charge increases continuously, and means for taking out a potential change tube of the main capacitance element. (2) The sub-capacitance element includes a plurality of MO8 type electrodes and voltage application means for applying different voltages to each of the electrodes, and is located near the surface of the semiconductor substrate facing each of the electrodes with an insulating layer interposed therebetween. 2. The charge detection device according to claim 1, wherein a stepped potential well is formed in the charge detection device. (3) The sub-capacitance element includes one MOB type electrode, a voltage applying means for applying a predetermined voltage to the electrode, and an impurity concentration formed on the surface of the semiconductor substrate facing the electrode via an insulating layer. 2. The charge detection device according to claim 1, further comprising a plurality of impurity layers having different impurity levels. (4) The auxiliary capacitance element includes one resistive electrode formed in an insulating layer on the surface of a semiconductor substrate, and means for passing a current between both ends of this electrode, and a semiconductor device facing the electrode. 2. The charge detection device according to claim 1, wherein an inclined potential well is formed near the surface of the substrate.