JPS5821863B2 - receiving device - Google Patents

receiving device

Info

Publication number
JPS5821863B2
JPS5821863B2 JP51045894A JP4589476A JPS5821863B2 JP S5821863 B2 JPS5821863 B2 JP S5821863B2 JP 51045894 A JP51045894 A JP 51045894A JP 4589476 A JP4589476 A JP 4589476A JP S5821863 B2 JPS5821863 B2 JP S5821863B2
Authority
JP
Japan
Prior art keywords
operational amplifier
resistor
receiving device
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP51045894A
Other languages
Japanese (ja)
Other versions
JPS52129217A (en
Inventor
大口孝
田草川武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Mobile Communications Co Ltd
Japan Broadcasting Corp
Original Assignee
Nippon Hoso Kyokai NHK
Matsushita Communication Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Hoso Kyokai NHK, Matsushita Communication Industrial Co Ltd filed Critical Nippon Hoso Kyokai NHK
Priority to JP51045894A priority Critical patent/JPS5821863B2/en
Publication of JPS52129217A publication Critical patent/JPS52129217A/en
Publication of JPS5821863B2 publication Critical patent/JPS5821863B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/1009Placing the antenna at a place where the noise level is low and using a noise-free transmission line between the antenna and the receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Radio Transmission System (AREA)
  • Manipulation Of Pulses (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Description

【発明の詳細な説明】 本発明は2つの受信出力の中から受信電界の強いものを
優先して選択できるようにした受信装置に関するもので
、受信出力の優先選択が容易におこなえるようにしたも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving device that is capable of preferentially selecting the one with a stronger received electric field from among two receiving outputs, and allows easy priority selection of the receiving output. It is.

たとえば2つの受信出力より、受信電界の強い方を選択
するものとしては従来第1図のようなものがある。
For example, there is a conventional system as shown in FIG. 1 which selects the stronger received electric field from two received outputs.

第1図において51.71はアンテナ、52゜72は受
信部、53,63.73は比較器、54゜74は基準源
、55.75はナントゲート、64はインバータ、65
はフリップフロップ、56゜76はスイッチである。
In Fig. 1, 51.71 is an antenna, 52.72 is a receiver, 53, 63.73 is a comparator, 54.74 is a reference source, 55.75 is a Nant gate, 64 is an inverter, 65
is a flip-flop, and 56° and 76 are switches.

ここで52.72の受信部は第2図のようにRFアンプ
81、ミキサ82、局部発振部83、フィルタ84,8
6、アンプ85,87,91、ダイオード90,92,
93、検波器88、スケルチ信号を取り出すフィルタ8
9で形成され、端子98に加わるアンテナ入力に対して
出力端子94〜97からは受信検知信号■F1(第1図
のI ”1−t 、I Fl−2)、受信電界信号■F
2(第1図のI F2−1.I F2−2 )、検波信
号RX(第1図RX。
Here, the receiving section of 52.72 includes an RF amplifier 81, mixer 82, local oscillation section 83, filters 84,
6, amplifier 85, 87, 91, diode 90, 92,
93, detector 88, filter 8 for extracting the squelch signal
9, and in response to the antenna input applied to the terminal 98, the output terminals 94 to 97 output the reception detection signal ■F1 (I"1-t, IFl-2 in FIG. 1) and the reception electric field signal ■F
2 (IF2-1.IF2-2 in FIG. 1), and the detected signal RX (RX in FIG. 1).

RX2)、スケルチ信号RXSQ第1図RX1 SQ。RX2), squelch signal RXSQ Fig. 1 RX1 SQ.

RX2 SQが取り出せるようになっている。RX2 SQ can now be taken out.

そこで比較器53,73では基準源54,74とIF、
1 ■F2−2、比較器63ではIF1〜1 と■F1
−2 とを比較し、この比較器53,63゜73の出
力によりナントゲート55,75の一方を開き、フリッ
プフロップ65のセット入力としている。
Therefore, in the comparators 53 and 73, the reference sources 54 and 74 and the IF,
1 ■F2-2, IF1~1 and ■F1 in comparator 63
-2, one of the Nant gates 55, 75 is opened by the output of the comparators 53, 63.degree.

この場合フリップフロップ65はゲート55゜75から
出力があってもただちにセットされるのでなくRX、S
Q、RX2 SQの出力とからスイッチ56.76のオ
ンオフ制御をおこなうようにしている。
In this case, the flip-flop 65 is not set immediately even if there is an output from the gate 55.
The on/off control of the switch 56.76 is performed from the output of Q and RX2 SQ.

第3図においてX、 Yは理想的なIF2(■F2−1
y lF2−2)、IFt(IFt−t * I
Ft−2)を示している。
In Figure 3, X and Y are ideal IF2 (■F2-1
y lF2-2), IFt(IFt-t*I
Ft-2).

この構成において比較器63はIFl−1>IF、2で
あればIf I II、その逆であればII OIIの
出力になり、第3図の基準ラインaに対しIF、。
In this configuration, the comparator 63 outputs If I II if IFl-1>IF, 2, and II OII if vice versa, IF with respect to the reference line a in FIG.

が右側、IFl、が左側にあれば明らかに比較できる。If IFl is on the right side and IFl is on the left side, a comparison can be made clearly.

しかし比較器63の感度を良くした場合ラインaに対し
共に右側であってもb部を拡大に示すようにIF特性の
リップルまたは電界のゆらぎ等により1F1−1 と
■Fh2 とで差があった時には電界が丸印で示す範
囲で変化していると切換出力が発生してしまうという欠
点がある。
However, when the sensitivity of the comparator 63 was improved, there was a difference between 1F1-1 and ■Fh2 due to ripples in the IF characteristics or fluctuations in the electric field, as shown in the enlarged view of part b, even though they were both on the right side of line a. There is a drawback that sometimes a switching output occurs when the electric field changes within the range indicated by the circle.

また■F1−1 とIF、2を同じになるようにしな
ければな“らず、製作がむずかしい。
Also, F1-1 and IF, 2 must be made to be the same, making manufacturing difficult.

本発明はこのような欠点を除去したもので以下第4図の
一実施例により説明すると51,71゜52.72,5
3,73,54,74,55゜75.56,76.64
,65は第1図のものと同じであってその説明は省略す
るが、IFl−1゜IFl−2,IF、1.IF、2出
力は第5図のような形で取り出せるようにしている。
The present invention eliminates such drawbacks, and will be explained below with reference to an embodiment in FIG. 4.
3,73,54,74,55°75.56,76.64
, 65 are the same as those in FIG. 1, and their explanation will be omitted. The IF and 2 outputs can be taken out as shown in Figure 5.

したがって第3図の場合と異なるがこれは第2図におけ
る92.93のダイオードの接続(使用)の仕方によっ
て自由に選べる。
Therefore, this is different from the case in FIG. 3, but this can be freely selected depending on how the diodes 92 and 93 in FIG. 2 are connected (used).

第4図において20は入力比較のだめの設定可変抵抗2
0.21は比較器、22は基準源、23は比較器21に
ヒステリシスをもたせるだめの時間設定用の抵抗である
In Figure 4, 20 is the setting variable resistor 2 for input comparison.
0.21 is a comparator, 22 is a reference source, and 23 is a time setting resistor for providing hysteresis to the comparator 21.

このヒステリシスは上述のゆらぎ等に対しては切換信号
を発生させないようにする不感帯を形成している。
This hysteresis forms a dead zone that prevents the generation of a switching signal in response to the above-mentioned fluctuations.

次にこの構成にもとすく動作を説明する。Next, the operation of this configuration will be briefly explained.

まずI Fl−1y I F)−2は第5図のように
逆の形で得られるようにしており、これらが基準ライン
Dの右側に位置する時には設定可変抵抗20にてOvに
することができる。
First, I Fl-1y I F)-2 are obtained in the reverse form as shown in Fig. 5, and when they are located on the right side of the reference line D, they can be set to Ov by the setting variable resistor 20. can.

したがって1F1−1.IF1、を相当高いレベルで近
似させることに注意をはらう必要がなくなり、両者の差
が0になることにより等制約に一致させることができる
Therefore, 1F1-1. It is no longer necessary to pay attention to approximating IF1 at a considerably high level, and by making the difference between the two 0, it is possible to match the equality constraint.

また精度の良い抵抗器を用いることにより、両者の電圧
差が0.001Vの精度で容易に合わせることができる
Furthermore, by using a highly accurate resistor, the voltage difference between the two can be easily adjusted to an accuracy of 0.001V.

一方、■F1−1 と■F1−2 の間で差が生じた
場合、比較器21には入力がある。
On the other hand, if a difference occurs between ■F1-1 and ■F1-2, the comparator 21 has an input.

(第6図は第4図の20〜23の構成を具体的に説明し
たもので23なるVB2を可変することにより比較器2
1を形成するオペアンプは第7図のように動作できるよ
うになっている。
(Figure 6 specifically explains the configuration of 20 to 23 in Figure 4. By varying VB2, which is 23, the comparator 2
The operational amplifier forming the circuit 1 can operate as shown in FIG.

出力の帰還量を可変することによりホールド電圧を第8
図のように可変できるようにしている)。
By varying the amount of feedback of the output, the hold voltage can be adjusted to the 8th
(It can be changed as shown in the figure).

なおIFl−1,■F1−2が第5図に示すDの右側に
ある時には比較器21に加わる入力は0になるように設
定可変抵抗20で調整されるため、220基準源もOV
に設定する。
Note that when IFl-1 and ■F1-2 are on the right side of D shown in FIG.
Set to .

このようにしておくことにより比較器21の入力電位が
十であればII I II、−であればII OIIが
出力され、これは従来のものと同一のナントゲート55
,75の入力となる。
By doing this, if the input potential of the comparator 21 is 0, II I II is output, and if it is -, II OII is output, which is the same as the conventional Nant gate 55.
, 75 are input.

なお■F、1 とIFl−2との間で第3図に示すよう
にリップルが生じた場合にはvFの帰還量を可変すると
とど対応でき、VB2 として精度の良いものを使用す
ればその安定性がはかれる。
Note that if a ripple occurs between F,1 and IFl-2 as shown in Figure 3, it can be dealt with by varying the feedback amount of vF, and if a highly accurate VB2 is used, it can be dealt with. Stability is measured.

また比較器21は1000000倍以上利得のあるもの
を用いることにより、シュミットスピードが早くなりホ
ールドも十分におこなえる。
Furthermore, by using a comparator 21 with a gain of 1,000,000 times or more, the Schmitt speed can be increased and holding can be performed satisfactorily.

以上実施例によシ説明したが、本装置によれば従来のも
のに比べ高精度の装置が簡単に形成でき実用上きわめて
有利である。
Although the embodiments have been described above, the present apparatus can easily form a high-precision apparatus compared to conventional apparatuses, and is extremely advantageous in practice.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の受信装置の系統図、第2図はその一部の
具体的な系統図、第3図は中間周波特性図、第4図は本
発明の一実施例における受信装置の系統図、第5図はそ
の中間周波特性図、第6図は一部の具体的電気結線図、
第7歯、第8図はその動作特性図である。 20・・・・・・設定可変抵抗、21. 53. 73
・・・・・・比較器、52,72・・・・・・受信部、
55,75・・・・・・ナントゲート、56,76・・
・・・・スイッチ、65・・・・・・フリップフロップ
、64・・・・・・インバータ、54゜74.22・・
・・・・基準源。
Fig. 1 is a system diagram of a conventional receiving device, Fig. 2 is a specific system diagram of a part thereof, Fig. 3 is an intermediate frequency characteristic diagram, and Fig. 4 is a system diagram of a receiving device in an embodiment of the present invention. Figure 5 is its intermediate frequency characteristic diagram, Figure 6 is a partial electrical wiring diagram,
The seventh tooth, FIG. 8, is its operating characteristic diagram. 20... Setting variable resistor, 21. 53. 73
...Comparator, 52, 72...Receiving section,
55,75... Nantes Gate, 56,76...
...Switch, 65...Flip-flop, 64...Inverter, 54°74.22...
...Reference source.

Claims (1)

【特許請求の範囲】 12個の受信部より受信順位決定信号を逆の形で取り出
してバランス調整用の抵抗器の両端に加え、その抵抗器
の摺動子から取り出した信号を、帰還形に構成され、一
方の入力端子が所定の電位に設定されたオペアンプの他
方の入力端子に供給し、そのオペアンプの出力信号と前
記2個の受信部中の所定受信電界を越えた受信電界信号
との論理積で検波出力選択用信号を作成したことを特徴
とする受信装置。 2 抵抗器を、固定抵抗器、可変抵抗器および固定抵抗
器の順に直列接続した回路で構成し、微細な調整を行う
ことを可能とした特許請求の範囲第1項記載の受信装置
。 3 オペアンプを、その出力側にダイオードを有して出
力電圧の範囲を制限するようにした特許請求の範囲第1
項記載の受信装置。 42個の受信部の受信レベルを同一にしたときバランス
調整用の抵抗器の摺動子に現われる信号電圧に等しい電
位を前記オペアンプの一方の入力端子に設定して、前記
抵抗と前記オペアンプの整合をとるようにした特許請求
の範囲第1項記載の受信装置。 5 オペアンプの帰還量を調整して、飽和時における受
信順位決定信号のゆらぎに相当する量の不感帯を前記オ
ペアンプに付与し、前記ゆらぎによっては前記オペアン
プの出力信号に変化を生じないようにした特許請求の範
囲第1項記載の受信装置。
[Claims] Reception order determining signals are taken out in reverse form from the 12 receiving sections and applied to both ends of a resistor for balance adjustment, and the signals taken out from the sliders of the resistors are fed back into the feedback form. one input terminal is supplied to the other input terminal of an operational amplifier whose potential is set to a predetermined potential, and the output signal of the operational amplifier and the received electric field signal exceeding the predetermined received electric field in the two receiving sections are connected. A receiving device characterized in that a detection output selection signal is created by logical product. 2. The receiving device according to claim 1, wherein the resistor is configured by a circuit in which a fixed resistor, a variable resistor, and a fixed resistor are connected in series in this order, thereby making it possible to perform fine adjustment. 3 Claim 1 in which the operational amplifier has a diode on its output side to limit the output voltage range.
Receiving device described in section. When the reception levels of the 42 receivers are made the same, a potential equal to the signal voltage appearing on the slider of the balance adjustment resistor is set to one input terminal of the operational amplifier, and the resistor and the operational amplifier are matched. The receiving device according to claim 1, wherein: 5. A patent that adjusts the amount of feedback of the operational amplifier to provide the operational amplifier with a dead zone corresponding to the fluctuation of the reception priority determining signal at saturation, so that the fluctuation does not cause a change in the output signal of the operational amplifier. A receiving device according to claim 1.
JP51045894A 1976-04-21 1976-04-21 receiving device Expired JPS5821863B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51045894A JPS5821863B2 (en) 1976-04-21 1976-04-21 receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51045894A JPS5821863B2 (en) 1976-04-21 1976-04-21 receiving device

Publications (2)

Publication Number Publication Date
JPS52129217A JPS52129217A (en) 1977-10-29
JPS5821863B2 true JPS5821863B2 (en) 1983-05-04

Family

ID=12731936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51045894A Expired JPS5821863B2 (en) 1976-04-21 1976-04-21 receiving device

Country Status (1)

Country Link
JP (1) JPS5821863B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838011A (en) * 1971-09-10 1973-06-05
JPS4950860A (en) * 1972-09-18 1974-05-17

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4838011A (en) * 1971-09-10 1973-06-05
JPS4950860A (en) * 1972-09-18 1974-05-17

Also Published As

Publication number Publication date
JPS52129217A (en) 1977-10-29

Similar Documents

Publication Publication Date Title
US8401504B2 (en) Extended range RMS-DC converter
US5831423A (en) Phase meter and method of providing a voltage indicative of a phase difference
JPS5821863B2 (en) receiving device
US3821648A (en) Automatic noise figure indicator
CN1180534C (en) Tuning arrangement
SU631841A1 (en) Frequency deviation rate meter
US3548307A (en) Electronic holding circuit
US3617887A (en) Voltage-to-current converter for driving a meter movement
GB2034142A (en) Muting circuit for an fm receiver
US4263558A (en) Phase-selective amplifier
SU1397838A1 (en) Device for exciting oscillations of movable system of magnetoelectric instrument
SU1629875A1 (en) Converter of complex impedance parameters
SU853561A1 (en) Peak detector
SU1068831A1 (en) Device for measuring frequency non-stability
SU1661656A1 (en) Instantaneous alternating analog signals transducer
SU1626328A1 (en) Voltage following device
SU415611A1 (en)
SU679814A1 (en) Device for the calibration of multichannel apparatus
RU2060507C1 (en) Frequency-modulated radiospectrometer
SU614392A1 (en) Dc measuring amplifier
SU659993A1 (en) Capacitance and inductance digital meter
Chapman Recorder preamplifier for displaying three decades on one linear scale
SU503194A1 (en) Device for estimating parameters of pulsed radio signals
SU488151A1 (en) Digital decibel ratio meter
SU1104430A2 (en) Wide-band ac-to-dc voltage converter