JPS58215027A - Formation of pattern according to etching - Google Patents
Formation of pattern according to etchingInfo
- Publication number
- JPS58215027A JPS58215027A JP9794982A JP9794982A JPS58215027A JP S58215027 A JPS58215027 A JP S58215027A JP 9794982 A JP9794982 A JP 9794982A JP 9794982 A JP9794982 A JP 9794982A JP S58215027 A JPS58215027 A JP S58215027A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- layer
- thin film
- resist
- forming layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はエツチングによるパターン、特に微荊なパター
ンを正確に形成させる方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for accurately forming patterns by etching, particularly fine patterns.
(b) 技術の背景
フォトリソグラフィ技術により形成される値上なパター
ンを具えた素子、例えば磁気バブルメモリ素子において
バブル転送路やバブル発生器及びバブル検出器等のパタ
ーンは、素子の大容量化及び小形化の追求により1μm
以下の42が要求されるようになった。そして、これら
素子パターンはパーマロイやAt及びNiCr等にてな
る金属層の表面にレジストパターンを形成し、該レジス
トパターンで覆われない部分をエツチングして形成され
る。(b) Background of the technology In elements with expensive patterns formed by photolithography technology, such as magnetic bubble memory elements, patterns such as bubble transfer paths, bubble generators, and bubble detectors are used to increase the capacity of the element and 1μm due to the pursuit of miniaturization
The following 42 are now required. These element patterns are formed by forming a resist pattern on the surface of a metal layer made of permalloy, At, NiCr, etc., and etching the portions not covered by the resist pattern.
(c) 従来技術と間頭点
しかし、前記金属層の表面反射率が高い(例えばAtの
それは90%以上)ため、レジストパターンを形成する
のに瞭して露光させたとき該光の廻り込みにより該レジ
ストパターン、延いては今頃パターンの襦明が損なわれ
るようになる。そのため、従来は金属層の表面に低反射
率の・4膜全蒸着(又はスパッタ)手段で被着し、該薄
膜の表面にレジストパターンを形成し、該レジスト・(
ターンで覆われない薄膜と金嘴層とをエツチング除去し
てからレジストパターンを除去し、その上に他の構成パ
ターン及び保護層を形成及びftLm’L、ていた。(c) Comparison with the prior art However, since the surface reflectance of the metal layer is high (for example, that of At is over 90%), when it is clearly exposed to form a resist pattern, the light is reflected around the surface. As a result, the resist pattern and, by extension, the clarity of the pattern will be impaired. Therefore, conventionally, a low-reflectance .4 film is deposited on the surface of a metal layer by full evaporation (or sputtering), a resist pattern is formed on the surface of the thin film, and the resist .(
After removing the thin film and gold beak layer not covered by the turns, the resist pattern was removed, and other constituent patterns and a protective layer were formed thereon.
その際、前記薄膜がCr2O3の如き酸化物でなるとき
は02のとり込み方が不安定であること及びその上に仮
看された積層との間で02のやりとりが行なわれて体積
変化することがある。とともに、残存する前記14ff
lのパターンが金@韻パターンの4気的特性に影響する
ときけ、素子特性の信頴性が損なわれるため、金属]偕
パターン形成悦に化学的エツチング手段で薄膜パターン
を除去しなければならない煩られしさがあった。At that time, when the thin film is made of an oxide such as Cr2O3, the way in which 02 is taken in is unstable, and the volume changes due to exchange of 02 with the laminated layer temporarily formed on it. There is. In addition, the remaining 14ff
If the metal pattern affects the four-dimensional characteristics of the metal pattern, the reliability of the device characteristics will be lost, so it is not necessary to remove the thin film pattern by chemical etching when forming the metal pattern. There was something special about it.
(d)発明の目的
本発明の目的は、上記欠点を除去したエツチングパター
ンの形成方法を提供することである。(d) Object of the Invention An object of the present invention is to provide a method for forming an etching pattern that eliminates the above-mentioned drawbacks.
(e) 発明の構成
上記目的は、パターン形成[暢の表面に低反射率であり
酸化させたとき該パターン形成・舊より低融点化される
薄@を被着し、該薄膜の表面にレジストパターンを形成
し、該レジストパターンに覆われない該薄膜と該パター
ン形成層との露呈部をエツチング除去し、該レジストパ
ターンを除去し、該レジストパターンの下に形成された
該)専膜のノくターンを酸化・蒸発させて除去すること
を特徴としたエツチングによるパターンの形成方法によ
り達成される。(e) Structure of the Invention The above object is to form a pattern by depositing a thin film on the surface of which has a low reflectance and which has a lower melting point when oxidized than the pattern forming film, and to apply a resist to the surface of the thin film. forming a pattern, etching away the exposed parts of the thin film and the pattern forming layer that are not covered by the resist pattern, removing the resist pattern, and etching away the exposed parts of the thin film and the pattern forming layer that are not covered by the resist pattern; This is achieved by a method of forming a pattern by etching, which is characterized in that the pattern is removed by oxidation and evaporation.
(f) 発明の実施例
以下、本発明の一実施例に係わる主要工程を説明するた
めの表及び図を用いて本発明方法を収明する○
下記の表は基板(ウエーノ・)の表面vcht−:ター
ンを形成する主要工程と該工程で1吏用する主要装置を
示したものであシ。(f) Embodiment of the Invention The method of the present invention will be described below using tables and figures for explaining the main steps related to an embodiment of the present invention. -: Shows the main process of forming a turn and the main equipment used in this process.
表 図は該主要工程に対応する試料の断面図である。table The figure is a cross-sectional view of a sample corresponding to the main process.
表の工程a及び図イにおいて、基板1の表面に蒸着手段
で厚さ2000 AのAi%(パターン形成層)2を被
着する。In Steps a and A of the table, an Ai% (pattern forming layer) 2 with a thickness of 2000 A is deposited on the surface of the substrate 1 using a vapor deposition means.
欠いて表の工程す及び1口において、AJ[2の表面に
蒸着手段で厚さ200Aのc r 205層(低反射率
の、尊4)3を被着する。In the first and second steps, a 200A thick cr 205 layer (low reflectance, grade 4) 3 is deposited on the surface of the AJ2 by vapor deposition means.
次いで表の工程C及び図ハにおいて、一般的手づ
段、90ちレジスト層をスピン#−トしたのち露光・現
像してレジストパターン4を形成する。Next, in Step C of the table and Figure C, a resist pattern 4 is formed by spinning the resist layer 90 times, exposing and developing it using a general method.
次いで表の工程d及び図ニジて2いて、イオンエ、テン
グ装置を用いレジストパターン4で扱われないCr20
g ’音3とAt層2を除去し、レジストパターン4の
下にCrt O,パターン(博1摸パターン)3′とA
tパターン(所望のパターン)2′とを形成させる。Next, in step d in the table and 2 in the figure, Cr20, which is not treated in the resist pattern 4, is removed using an ion etching and tengu device.
g 'Remove sound 3 and At layer 2, and add CrtO, pattern (pattern 1) and A under resist pattern 4.
t pattern (desired pattern) 2' is formed.
欠いて表の工程e及び図7rSVCおいて、プラズマア
ッシャを用い、Atiアッシングしない02プラズマ中
に1二に示す試料を曝すと、先ずレジストパターン4が
灰化され除去されたのち、Cr2O5パターン3′が0
.プラズマに直接曝されるようになる。その結果、融点
が約1990℃のCr2O3は酸化され融点が約190
℃のCrysに変質して蒸発するため、Cr2O,パタ
ーン−3′は消威しAtパターン2′のみが基板1の表
面に残存されるようになる、なお、上記実施例はA4層
2の不要部分をエツチング除去してAtパターン2′を
形成した一例であり、パーマロイやAu及びNi Cr
等のパターンも上記工程と同様な工程及び族1跋を便用
して形成される。In step e in the table and SVC in FIG. 7r, when the sample shown in 12 is exposed to 02 plasma without Ati ashing using a plasma asher, the resist pattern 4 is first incinerated and removed, and then the Cr2O5 pattern 3' is 0
.. Becomes directly exposed to plasma. As a result, Cr2O3, which has a melting point of about 1990°C, is oxidized and has a melting point of about 190°C.
℃ and evaporates, the Cr2O pattern -3' disappears and only the At pattern 2' remains on the surface of the substrate 1. Note that the above embodiment does not require the A4 layer 2. This is an example in which the At pattern 2' is formed by etching away the etched portion, and is made of permalloy, Au, and NiCr.
Patterns such as the above are also formed by using the same process as the above process and the same pattern as the above.
(2))発明の詳細
な説明した如く不発明方法によれば、光の廻り込み防止
用としてパターン形成1iの表面に=iした低反射率の
1膜は、酸化させて低融点化し蒸発除去させるため、該
薄膜の表面に形叔したレジストパターンの除去と同一工
程で除去することが可能になり、低反射率膜パターンの
除去が従来方法よりも著しく簡易化できた効果は太きい
。(2)) According to the uninvented method as described in detail of the invention, a film with low reflectance =i on the surface of the pattern formation 1i for preventing light from going around is oxidized to have a low melting point and removed by evaporation. Therefore, it becomes possible to remove the resist pattern shaped on the surface of the thin film in the same process, and the effect of making the removal of the low reflectance film pattern much easier than in the conventional method is significant.
図は本発明の一実飛例になる主要工程を祝明丁るだめの
断面図である。
なおjν1中に〉いて、2ばAt唱(・くターン形成、
])。
2”riALパターン(所望のパターン)、3はCr2
O3膜(低反射尤の4暎)、 3′ばCr2O3□’
ター/ (7に:J、(パターン)、4はレジストハタ
ーンヲ示す。The figure is a cross-sectional view of the main steps of the present invention. In addition, while in jν1, chant 2 Ba At (・ku turn formation,
]). 2”riAL pattern (desired pattern), 3 is Cr2
O3 film (4 layers with low reflection potential), 3' and Cr2O3□'
/ (7: J, (pattern), 4 indicates the resist pattern.
Claims (1)
的にエツチングし所望のパターンを形成する方法におい
て、パターン形成層の表面に低反射率であり教化させた
とき該パターン形成層より低、樵点化されるCrzOs
等の薄膜を被着し、桜薄膜の表面にレジストパターンを
形成し、該レジストパターンに覆われない該薄膜と該パ
ターン形成層との露呈部をエツチング除去し、該レジス
トパターンを除去し、該レジストパターンの下に形成さ
五ていた該薄膜のパターンを酸化・蒸発させて除去する
ことを特徴としたエツチングによるパターンの形成方法
。In a method of forming a desired pattern by selectively etching a pattern-forming layer having a thin film of low reflectance on its surface, the surface of the pattern-forming layer has a low reflectance and when etched, the pattern-forming layer has a lower reflectance than that of the pattern-forming layer. , CrzOs
A resist pattern is formed on the surface of the cherry blossom thin film, the exposed portion of the thin film and the pattern forming layer that is not covered by the resist pattern is removed by etching, the resist pattern is removed, and the resist pattern is removed. A method for forming a pattern by etching, characterized in that the thin film pattern formed under the resist pattern is removed by oxidation and evaporation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9794982A JPS58215027A (en) | 1982-06-08 | 1982-06-08 | Formation of pattern according to etching |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9794982A JPS58215027A (en) | 1982-06-08 | 1982-06-08 | Formation of pattern according to etching |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58215027A true JPS58215027A (en) | 1983-12-14 |
Family
ID=14205915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9794982A Pending JPS58215027A (en) | 1982-06-08 | 1982-06-08 | Formation of pattern according to etching |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58215027A (en) |
-
1982
- 1982-06-08 JP JP9794982A patent/JPS58215027A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4218532A (en) | Photolithographic technique for depositing thin films | |
JPS62245509A (en) | Manufacture of thin film magnetic head | |
KR0147976B1 (en) | A method for planarization patterning onto the thin film head | |
US4464459A (en) | Method of forming a pattern of metal elements | |
JPS5851412B2 (en) | Microfabrication method for semiconductor devices | |
JPS58215027A (en) | Formation of pattern according to etching | |
JPS5821808B2 (en) | Method for manufacturing magnetic bubble domain device | |
JPH0575237A (en) | Conductor pattern formation | |
KR0147996B1 (en) | A method for planarization patterning onto a thin film head | |
JPS6326536B2 (en) | ||
JPH0548247A (en) | Forming method for conductor pattern | |
JPH0620230A (en) | Thin-film magnetic head and its manufacture | |
JPS58123711A (en) | Preparation of magnetic bubble memory element | |
JPS61210508A (en) | Manufacture of thin-film magnetic head | |
KR0147995B1 (en) | A method for patterning a thin film head | |
KR0153970B1 (en) | Method for fabricating a thin film magnetic head | |
US3450534A (en) | Tin-lead-tin layer arrangement to improve adherence of photoresist and substrate | |
JPH04129016A (en) | Thin film magnetic head | |
KR100252757B1 (en) | Method of forming metal pattern | |
JPH11175915A (en) | Thin-film magnetic head and its production | |
JPH0320809B2 (en) | ||
JPS6036088B2 (en) | Method for manufacturing magnetic bubble memory element | |
JPH1197394A (en) | Direct writing patterning method | |
JPH04181794A (en) | Manufacture of circuit board | |
JPH05159223A (en) | Production of thin-film magnetic head |