JPS58209235A - Noise reduction device - Google Patents

Abstract

PURPOSE:To obtain a sufficient characteristics without saturation at high frequencies even if a device whose tape speed drives slow is used, by separating an input signal for encoding or decoding into a signal for a main signal system and a side chain signal system. CONSTITUTION:In the encoding state where a switch S11 to the position of contact (a), a signal applied to an input terminal IN is separated into a signal for the main signal system introducing the applied signal to an adder 22 as it is via an amplifier 21, and a side chain signal system introducing the applied signal to an adder 22 via an amplifier 23, a filter circuit 24 and a variable impedance circuit 25. The filter characteristics is changed by controlling the impedance of the variable impedance circuit 25 with a control voltage formed from an output of the circuit 22 via an amplifier 26 and a detecting circuit 27. In the decoding state where the switch SW11 turns to the position of contact (b), a signal having the decoding characteristics is derivered with almost reverse procedures as those at the encoding.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a noise reduction device suitable for tape recorders and the like.

[Technical background of the invention]

2. Description of the Related Art Conventionally, a noise reduction device configured as shown in FIG. 1 has been known for a compact cassette type tape recorder or the like.

That is, this is what is called a Dolby B type, and during encoding (ENOODB), the signal Jr5 applied to the input terminal (IN) K is directly passed through the amplifier 11 to the adder circuit 12Vci! ill<main signal system and
It is divided into an amplifier 13, a filter circuit 14, an amplifier 15, and a side chain signal system that leads to the adder circuit 12 via a limiter 16. In this case, the filter characteristics are changed by controlling the resistance value of the transformer 19 using a control signal obtained from the output of the amplifier 15 through the amplifier 17 and the detection circuit 18. ), a signal having encoding characteristics as shown in FIG. 2(a) is derived.

At the time of decoding (DECOR, D), by going through almost the opposite procedure to the above-mentioned encoding time, the
A signal with decoding characteristics as shown in l is output to the output terminal (O
UT).

In addition, (Sl) in the figure is encoded on the (al = point side) (
BNCODE) state and decode (D
This is a switch that changes to the EOODE) state.

[Problems with background technology]

However, although the conventional noise reduction devices described above can provide sufficient characteristics when applied to a normal compact cassette tape recorder, when applied to a micro-type cassette tape recorder where the tape speed is slow. Such devices have the disadvantage that sufficient characteristics cannot be obtained with devices that require high-frequency and high-level recording.

This is because, when applied to the latter type of equipment, high frequency saturation tends to occur when the recording level is raised.

[Purpose of the invention]

Therefore, this invention has been developed in view of the above points, and has been developed so that sufficient characteristics can be obtained without high-rise saturation even when applied to devices with slow tape speeds such as micro-type cassette tape recorders. The object is to provide an improved and very good noise reduction device.

[Summary of the invention]

That is, the noise reduction device according to the present invention has the following features:
a first means for separating an input signal for encoding or decoding into a main signal system and a side chain signal system;
a second means for generating a control voltage according to a change in the input signal; a filter circuit included in the side chain signal system; and a variable impedance for changing the characteristics of the filter circuit; A variable impedance circuit consisting of a voltage-controlled amplifier whose gain is controlled from in-phase gain to anti-phase gain by a means, and a side signal passing through a variable impedance circuit included in the main signal system 1477 and the side chain year system. It is characterized in that it is provided with a third means for adding the chain signals and deriving the encode output tube or the decode output.

[Embodiment 1 of the Invention] An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, as shown in FIG.
In the encoded (BNOODE) state on the AL contact side, the signal applied to the input terminal (IN) is passed through the amplifier 21 to that 1 addition circuit 22 and the main signal system.
It is divided into a side chain signal system that leads to the adder circuit 22 via an amplifier 23, a filter circuit 24, and a variable impedance circuit 25. In this case, the impedance value of the variable impedance circuit 25 is controlled by a control voltage obtained by 7% of the output of the addition (b) path 22 through the amplifier 26 and the detection circuit 27, thereby changing the filter characteristic to ef, as will be described later. A signal with encoded characteristics is output to the output terminal (OUT
).

1, the decode (DECODB) state in which the switch (Sl, 1 can be output from the end (OUT).

FIG. 4 shows a specific example of the variable impedance circuit 25 in the above, in which the lower differential pair transistor (Q, +) is applied with the input signal from the filter circuit 24.
- (Q! ) and the upper differential pair transistor (Q, ) to which the control voltage from the detection circuit 27 is applied.
, (Q4) and (Qri, (Qa)), it is a type of voltage-controlled amplifier (VOA) with a double-balanced configuration.

FIG. 5 shows an intangible example of each part of FIG. 3 including the variable impedance circuit 24 shown in FIG. 4, and the detection circuit 27 is a diode (DI).

The detection output from (Dt) is connected to the resistors (R, , ), (R,
) of the upper differential pair transistor (Qsl) of the variable impedance circuit 25.
), (Qa).

In addition, the variable impedance circuit 25 has a bias voltage (VB) supplied to the bases of its upper differential pair transistors (Q, ), (Qll), and
The output from the collector of s) is supplied to the adder circuit 22 via an amplifier 28 having a feedback configuration and a clipping circuit 29 consisting of diodes (D, ) and (D4).

Therefore, in the above configuration, the variable impedance circuit 2
5 is a bubble balance circuit having transistors (Ql) to (Qa), in which an input signal (Vin) applied to the base of (Q,) is connected between the emitters of (Ql) and (Q,). (Q, ), (Qt
) and flow in opposite phase relation to each other. Then, control voltage (v'c) force negative polarity (l V'c I (2VT
), (Q4), (Q, l are on and (Q3),
When (Ql,l) turns off, an output signal that is in phase with the input is generated at the load resistor (RL, ).

Here, if Ro=RL, the gain of the variable impedance circuit 25 at this time is 1 (OdB)
(This gain is usually used when it is less than 1).

Then, as the control voltage (Vc') approaches the O potential, the gain gradually decreases, and at Vc w O the ideal vc
If it is operating, the gain is 0 (-oodB).

Furthermore, when the control voltage (Vc') increases and becomes positive, (Q4) and (Q,) are turned off and (Ql > and (Qa) are turned on, causing the load resistance (RL, ) to will produce an output signal that is in opposite phase to the input.

Figure 6 shows the variable impedance (2) path 25 as described above.
It shows the characteristics of

Next, the variable impedance circuit 25 as described above? ! −
The two-code operation of the noise reduction device used will be explained.

First, when the input signal is at the small level, the control voltage (Vc) from the detection circuit 27 is actually (Q,),
The control voltage (Ve) applied to the pace of (Q,)
It is assumed that the value of the bias voltage (VB) is set so that ') has negative polarity.

In this state, as mentioned above, the gain of the variable impedance circuit 25 is 1, so the main signal and the side chain signal passing through the filter circuit 24 with bypass characteristics are added together in the adder circuit 22. Therefore, as shown in FIG. 7, a signal with the high frequency boosted is derived from the output terminal (OUT).

Then, as the input level increases and the control voltage (Vc) from the detection circuit 27 increases, (
When Vc') approaches 0 potential from negative polarity, the gain of the variable impedance circuit 25 approaches -■ as described above, so only the main signal is gradually derived from the output terminal (OUT). , the characteristics approach the flat characteristics as shown in FIG.

Furthermore, when the input level increases, (V e' ) becomes positive and the output signal of the variable impedance circuit 25 at this time has an opposite phase to the input signal, so that the side chain signal is transferred from the main signal. Since the signal is subtracted, the output signal derived from the output terminal (OUT) has a characteristic in which the high frequency region is lowered as shown in FIG.

This is effective in preventing saturation at a large level of X, which is characteristic of tape recorders.

Furthermore, during decoding, the pressure of the adder circuit 22 is applied to the input of the amplifier 23, resulting in a characteristic opposite to that during encoding, as shown in FIG.

In other words, when such a noise reduction device is applied to a tape recorder, it records by raising the low-level treble, and raises it during playback to reduce noise, and also raises the high-level treble range to record. However, by increasing it during playback, it is possible to prevent saturation in the high range.

In addition, since such a noise reduction device is of a dual-pass type, it has a sharp rise characteristic such as tone burst, and unnecessary overshoot can be removed by the clipping circuit 29 when a constant force is attached. Therefore, it becomes possible to improve the dynamic characteristics to that extent.

It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and applications can be made without departing from the gist of the invention.

For example, for the variable impedance circuit 25, the gain (-8) is shown in FIG.
Or (A) inverting amplifier, ? A combination of Ua or sob and a voltage controlled amplifier 31a or 9lb whose gain varies from 0 to 2 or 12A-0''i may be used.

At the time of decoding, as shown in FIG. 10, it may be taken out from the input terminal (I N ) (lIl) as an input to the level cut-off or detection [0] path 27'.

In this case, the gain of the variable impedance circuit 25' is set so as to vary by up to 10K (IKl minus 1).

Further, as for the filter circuit 24, one having characteristics other than the low-pass characteristic may be used.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, the invention has been improved so that sufficient characteristics such as high frequency saturation can be obtained even when applied to devices with slow tape speeds such as micro-type cassette tape recorders. It becomes possible to provide an extremely good noise reduction device.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing a conventional noise reduction device.
Fig. 2 (al, tbl are curve diagrams showing the encoding characteristics and decoding characteristics of Fig. 1, Fig. 3 is a block diagram showing one embodiment of the noise reduction device according to the present invention, and Fig. 4 is a curve diagram showing the encoding characteristics and decoding characteristics of Fig. 3). A block diagram showing a specific example of the variable impedance circuit section, FIG. 5 is a block diagram showing a specific example of each part in FIG. 3, and FIG. 6 is a block diagram showing the characteristics of the variable impedance circuit in FIGS. 4 and 5. Figures 7 and 8 are curve diagrams showing the encoding and decoding characteristics of Figures 3 and 5.
Figures (al and b) are block diagrams showing other concrete examples of the variable impedance circuit of Fig. 3, and Fig. 10 is a block diagram of a decoding system showing another embodiment of the present invention. )...Input end, 21 River amplifier, 23...Addition circuit, 24...Filter circuit, 25 Variable impedance circuit, 26...Amplifier, 27...Detection circuit, 2
8... Amplifier, 29... Clipping circuit, (S+
,)...Switch, (OUT)...Output end.

Claims (1)

[Claims] a first means for separating an input signal for encoding or decoding into a main signal system and a side chain signal system;
a second means for generating a control voltage according to a change in the input signal; a filter circuit included in the side chain signal system; and a variable impedance for changing the characteristics of the filter circuit. a variable impedance circuit consisting of a voltage-controlled amplifier whose gain is controlled from in-phase gain to negative-phase gain by a control voltage; A noise reduction device that is patented as comprising a third means for adding the passed side chain signal and outputting an encoded output or a decoded output.