JPS58207871A - Full wave rectifying circuit - Google Patents

Abstract

PURPOSE:To obtain a rectified voltage proportional to the AC voltage even if it is extremely low AC voltage by eliminating an insensitive zone in a full-wave rectifying circuit. CONSTITUTION:While positive high level voltage is applied to control terminals 15, 16, the rectified voltage becomes negative or positive, and only negative of the rectified voltage is produced at the output terminals 18, 20 of C-MOS switches 13, 14 and rectified. Since the switches 13, 14 respectively generate output voltages for the voltages of opposite phases, full-wave rectified waveform is obtained at the output terminal 21 which is connected in parallel with the output terminals 18, 20. The input terminal 17 and the output terminal 18 as well as the input terminal 19 and the output terminal 20 when positive high level voltage is applied between the terminals 15 and 16 are mere resistance therebetween, no insensitive zone exists with good linearity. Accordingly, even extremely low rectified voltage, an output which is proportional to the rectified voltage is obtained from the output terminals 18 and 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for accurately performing full-wave fluorescence even at minute voltages.

Conventionally, a diode is used for the rectifier kr, and in the case of full-wave rectification, for example, a circuit such as the 11th W is used. In this figure, 1 is a transformer, and the center point 3 of the secondary coil 2 is grounded. 4°S is a diode!
), the output side is connected.

When a sine wave is applied to the primary side of the transformer 1, a full-wave rectified output voltage is obtained at the output terminal 6.

This circuit is effective when obtaining DC power or when demodulating an AM modulated signal having sufficient amplitude. However, the diode 4.5 has nonlinearity,
Particularly at low voltages, it is strongly affected by the dead zone and cannot be used when it is desired to obtain a DC voltage proportional to the voltage of the signal to be rectified. For example, if a silicon diode is used for diode 4.5, a dead zone of 0.6 to 7 V will normally occur, even if an AC voltage with a peak value of about 0.6 to 0.7 V or less is applied. Rectified output cannot be obtained.0.6~0,
Even if the signal is 7V or more, a rectified output can only be obtained for the voltage that exceeds this voltage, so for low AC voltages such as 1 or 2V, it is not possible to obtain a rectified voltage proportional to the AC voltage. is impossible.

By eliminating the dead zone, this invention reduces the
The rectification 'proportional to the alternating current voltage even if the pressure is a is related to the II flow path that allows the pressure to be obtained.

Hereinafter, this invention will be explained in detail with reference to the drawings.

FIG. 2 is a pull diagram showing one embodiment of the present invention.

7.8 is a comparator with little hysteresis, and when the voltage applied to the human power 49.10 is negative, or negative or zero, a positive high level voltage is applied to the output terminals 11 and 12; otherwise, it is positive. A low level voltage is generated.

13.14 are CMOS switches, and control terminals 15.14 are CMOS switches.
Only when a positive high level voltage is applied to input terminal 17, output terminal 18, and input terminal 19. Output end 20
The resistance between them decreases and they become conductive. Input terminals 17 and 1
A voltage to be rectified is applied to 9. The phase of the voltage input to the input terminal 19 is input to the input terminal 17 (the phase of the voltage is inverted and equal to k).

Since a positive level voltage is applied to the il control terminals 15 and 16 (during the time when the applied vLIlt voltage is negative or zero, the CMOS switch 13, 14
Only the negative part of the rectified voltage is taken out at the output terminals 18 and 20 of. In other words, it has been rectified. CM
Since the OS switches 13 and 14 generate output voltages for voltages with opposite phases, a full-wave rectified waveform is obtained at the output terminal 21 to which the output terminals 18 and 20 are connected in parallel.

Input terminal 17. when a positive - level voltage is applied to control terminal IS, 111. between the output end 1B and the input end 19. The connection between the output terminals 20 is simply a resistance, there is no dead zone, and the linearity is good, so even if the voltage to be rectified is minute, a rectified output can be obtained from the output terminals 18 and 20, and the output voltage is proportional to the voltage to be rectified. I get the output.

In the above embodiment, the comparator 7.8 has been described for generating a unipolar output voltage, but it may also generate a bipolar voltage. For example, input terminals S and 1
It may be a comparator that outputs a positive high level voltage when the input voltage is negative or negative or zero, or outputs a positive high level voltage when the input voltage is positive. In this case, CM
The OS switches 13 and 14 need to have a switch circuit configuration that does not break down when the negative voltages of the outputs of the comparators 7 and 8 are applied to the control terminals 15 and 16. For example, CMOS switches 13 and 14 are CM
In the case of an OS switch, it is necessary to ensure that the absolute value of the power supply voltage v0 does not become smaller than the voltage on the negative side of the output voltage of the cosciparators 1 and 8.

Also, the comparator 118 is positive (or positive or zero).
It may be possible to generate a positive high level voltage with respect to the input. In this case, the positive part of the rectified voltage is output from the output terminal 18.20VC of the CMOS switch 13.14. Of course, in this case as well, the output of the comparator 7.8 may be bipolar.

Furthermore, the comparator 7.8 may be unipolar with a negative output voltage. In this case, the one with the larger absolute value...
level. The CMOS switches 13 and 14 are required to be conductive at a negative high level voltage.

E. In the above, the CMOS switches 13 and 14 are assumed to be conductive only at high level, but they may be conductive only at low level. Also, CM
The OS switches 13 and 14 are not only CMOS switches, but also conductive only for voltages at either the voltage level or the low level.

Any other switch may be used as long as it has no dead zone.

FIG. 3 shows another embodiment of the invention. 22
is a phase inverting circuit such as an inverting amplifier with an amplification factor of 1, for example. Comparator 7.8゜cMos switch 13
．． Since the phase relationship of the voltages applied to 14 is the same as in FIG. 2, the same rectification function as in FIG. 2 is obtained.

FIG. 4 shows still another embodiment of the invention.

In this figure, 23 is a non-inverting amplifier, and 24 is an inverting amplifier, and the amplification factors of the non-inverting amplifier 23 and the inverting amplifier 24 are the same. In this case as well, comparator 7.8, CM OS
The phase relationship of the voltages input to the switches 13 and 14 is the second
The case is the same as in the figure, and CMOS switches 1, 3 and 1
However, the comparator 8, for example 8, may be replaced with an inverter 25 as shown in the $S diagram kC.

Comparator 7.8 in the embodiment of FIGS. 3 to 5
The output voltage of the inverter 25, the polarity and level of the voltage to be applied to the control terminal of the switch are the same as in the case of FIG.

Output terminal 21 kC The input impedance of the connected circuit is CMOS switch 13.14, output terminal 17.
If the impedance is not negligible compared to the impedance at the time of interruption between 18 and 19.20, it is preferable to connect the resistor 26 at the position shown by the broken line in each figure.

The resistance value is human, output end 17.18 and 19. ．． It is necessary that the impedance is sufficiently small compared to the impedance at the time of interruption between 20° and 20°.

The c ht o s switch 13 has a control terminal 15 . The integrator may generate a voltage proportional to the product of the voltages applied to the input terminal 17 at the output #18 (the same applies to the CMOS switch 14. In this case, the controller 7
, It or the output of the inverter 25 is required to generate a constant positive or negative voltage for one polarity of the voltage to be rectified, and a zero voltage for the other polarity. At the output of the integrator, a voltage proportional to the voltage obtained by multiplying one polarity of the voltage to be rectified by a constant voltage is obtained, which means that the voltage has been rectified t'. The integrator in this case can be equivalently regarded as a switch. Further, the input terminal to which the comparator 7.8 or the inverter 25 is connected can be regarded as a control terminal.

In addition, in the first distribution, it is remarkable that the rectified output voltage is proportional to the m current voltage only when the output voltage of the CMOS swigs 13 and 14 is set to zero KpAIIn,Stl.

As is clear from the above explanation, the full-wave rectifying circuit 4 of the present invention has no dead zone and has good directivity. A rectified output can be obtained. Therefore, if this invention is used, for example, when converting into a small amplitude sine wave direct current, A/DR converting it, processing it with a computer, and controlling it, the computer can accurately measure the amplitude of the small amplitude sine wave KvL. and can be accurately controlled by a computer. In addition, since the first input voltage obtained by full-wave rectification is effectively used, and compared to half-wave rectification, the time constant of the filter circuit can be made smaller, resulting in a full-wave rectification circuit with good response characteristics. Furthermore, this invention can also be applied to precision AC voltmeters, current ammeters, resistance meters, etc.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a conventional rectifier circuit, #! Figure 2, Figure 3,
FIGS. 4 and 5 are block diagrams showing each embodiment of the full-wave 4I flow circuit of the present invention. In the figure, 1 is a transformer, 2 is a secondary coil, 3 is a center point, and 7
．． 8 is a comparator, 9.10.1F. 19 is human power, 11, 12, 18, 20 is the output end, 13
．． 14 is a CMOS switch, 15.16 is a control terminal, 2
1 is an output terminal, 22 is a phase inversion circuit, 23 is a non-inverting amplifier, 24 is an inverting amplifier, and 25 is an inverter. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A switch or equivalent switch circuit that passes a signal only when a voltage at one of the high or low levels is applied, and this switch is not yet rectified with respect to the control terminal of the equivalent switch circuit. (a first rectifier circuit consisting of nine circuits for applying a voltage of one level to the '+l1lj control terminal at a time synchronized with only one polarity of The input terminal of the circuit includes an N signal generating section, and a signal generating section whose phase is inverted with respect to the signal input to the iJ1 crab flow circuit at the input terminal of the second rectifier circuit. Patented full-wave rectifier circuit.