JPS58205989A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize high speed reading, by increasing the potential of a bit line higher than a supply voltage to be supplied to a memory cell when precharging, in order to increase the conductance of a transistor for driving. CONSTITUTION:If a precharge controlling signal Vin is set to a grounding electric potential V SS, an output VC of a precharge signal generation circuit attains to the electric potential VSS, and a transistor in the precharge circuit is turned on to increase the potential of a bit line on low level side to electric power source potential VDD. On the other hand, the output voltage VD of a delay circuit 30 formed by inverters I3-I5 of an enhancement type CMOS transistor due to the drop of the signal Vin is increased to electric potential VDD. Simultaneously, a transistor N1 is turned off, P5 turned on by the same kind of two-stage inverters I1 and I2, and a transistor P4 is turned off. A capacitor C is charged to electric potential 2VDD, and bit line voltage on high and low sides is increased higher than the electric potential VDD. Word line potential is also increased to increase the inductance of a transistor for driving a memory cell so that a high speed reading can be performed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This book 5-5 describes studies and shoes that will be used in circuit memories and microcomputer systems. 1. relates to the equipment, especially the F11 open circuit in which a resistance element is used as a load and an enhancement type MO8) runnostar is used as a drive transistor. 1. Regarding the semiconductor memory device d which is located south of the 7'd memory cell.

[Technological view of the invention] Innate (4) The opening of light is the same as Yukihi Iriya and the commercialization of access V. In order to increase the capacity, *Ill
The size of the 1-hin i-g lyme-7 lysel is reduced. Because of -τ, there are more memory cells in the pair of throats, and the memory capacity of each of fl and Ll decreases due to the imitation ratio, and -C goes. Therefore, the time required to transfer the pressure 4L4 from the memory cell to the bit line becomes longer, making it difficult to speed up access.

The above will be explained in detail below.

FIG. 1 shows an E/L type memory cell in a static memory, and its basic structure is a two-circuit circuit consisting of a load resistor and a drive transistor. That is, R1 and R8 are resistive elements for load, and one end of each is connected to the DD power supply. T1 and T,
are construction type N-channel MOS transistors for driving, each source is connected to the VSS power supply (grounded), and each f-t drain is connected to each other. Ts and T4 are transistors for transfer darts, and each dart is connected to the word line 10. J”
and 12 are a pair of pits m, and the resistive element R1
The transfer transistor Ts is connected between the connection point (node A) of the drive transistor T1 and the bit line 11, and the transfer transistor Ts is connected between the resistance element Kl and the drive transistor T2.
The transfer transistor r4 is connected between the connection point (node B) and the pin 812.

In a memory cell based on a f-flop circuit like the 6-pin above, for example, the connection point A is l! il+1! Assuming that the connection point B of vMs is held at a low potential vL, normally, vM% is held at a value of Voa'It by a current iu supplied through one of the resistive elements R, A current iL flows through the other resistance element R1 and transistor T8.

Therefore, in a static memory having such an ElR type memory, at least the upper
The current obtained by multiplying iL by the memory capacity M is consumed as stand power υ1t. Therefore, in the human body mouse static memory, in order to reduce the standby current, the current iL is decreased so that the current iL is
The resistance element g1. R
.

The resistance value is increased.

Now, the word line potential vWL becomes the VDD potential, and bits -11.12 are transferred through the transfer transistors 1's and Ta'.
Consider the case where a high potential and a low potential are applied to nodes A and B, respectively. At this time, the node B on the side of the low potential V
is at a Veil potential because the transfer transistor T4 performs a three-pole tkJJ operation, but the node A on the high potential vH side is at VDD because the transfer transistor Ts performs a pentode operation.
The transfer transistor T does not rise to m level, but from vDD,
It is the value obtained by subtracting the threshold voltage of . That is, VM = VDD −Vt (Vu) ・”
(1), where Vd (Mu) is the threshold voltage due to the substrate bias effect, Vr (Vn) = VTO+,,',l/””τQ ”1
1111 (Ako-”u-k) ・-(JVro
: Threshold voltage C of the transfer transistor when Vu=Ov
OX; unit of transfer transistor f-) capacity 68; permittivity q of the semiconductor substrate on which the transfer transistor is formed; one charge of electrons NgU; upper Mc: impurity of Jk& once Vb+: built-in voltage .

By the way, even if the high potential VH01+10 node A is at a voltage as low as VooliL during writing, after a while, a current of 1M is supplied to the resistor R and approaches the VOO potential (however, the time is as described above). As in the case of a large-view memory, resistor cables R,,R are used to reduce the standby'ft flow.

It is necessary to increase the resistance value of 1r^, so it becomes quite long. For example, in a 64-bit memory, the resistance value is several tens of Gla, and the electrical board of node A on the VH side is several tens/F, so the discharge (precharging) of node A on the VH side is several tens of times. It takes 100 μs.

This time is much larger than the main read cycle and write cycle time (about 10100n).
It is not possible to follow the short-term write/read repetitions in the +ra- cell, and in the end the voltage at the 4 node A on the ^ potential side of the cell never becomes greater than VB, and this 1L of node A
The drive transistor 1's voltage applied to the voltage f-) is insufficient to reduce the 1u voltage of the pit IVllJ2 (therefore, it takes a long time to step down the bit line 12, and the bits Hii, iz In addition, both equations (1), <z> are required. As can be seen from the above, as the substrate concentration increases, the effective l&l tolerance voltage increases and the V■ potential decreases.As an example of this, consider the case where transistors are miniaturized.

In this case, if the vDD14L pressure is constant, the substrate concentration must be increased as the size becomes smaller. By doing so, the substrate effect of threshold voltage increases and the Vlt potential decreases (.

On the other hand, if you want to miniaturize without increasing the substrate concentration, VD
DI! It is necessary to lower the source voltage. In this case, both formulas (
]) As can be seen from the graph, the vH potential is lower than papermaking.

Here, we pay attention to the channel length of the transistor as a parameter for miniaturization, and V to L.

Figure 2 shows the changes in . In the figure, the reason why the vH convex curve breaks as L becomes smaller is because if L is below that value, the transistor will not be able to operate through the transistor.
As l decreases, the bit line voltage step-down device of the memory cell becomes increasingly slow. [Problems in the background art] In order to shorten the above-mentioned access time, conventionally, the bit line voltage step-down device for the memory cell is Methods have been taken to compensate for the burden of However, most of the pit line valleys are the junctions formed between the diffusion of the source or drain of the transfer transistor and the substrate, and as the substrate concentration increases with miniaturization, it becomes necessary to increase the concentration of the substrate. It has become difficult to reduce the capacity of the pit line due to the nature of the pit line, and it has become difficult to perform fast hedding operations.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.
The present invention provides a semiconductor memory device that can shorten the step-down time of the bit line voltage by the memory cell when the memory cell is extended and performs a high-speed offset operation.

[Summary of the invention]

That is, the present invention has a static memory cell in which a resistive element serves as a load for a driving transistor, and the transfer transistor is turned on by selecting a pair of pin word lines connected to a node inside the memory cell via a transfer transistor. In a semiconductor memory device having the function of boosting the voltage through a pair of one or more transistors before the voltage rises, the pin voltage is boosted to a voltage higher than the supply voltage VL)D to the memory cell. When the voltage at the side node is set to be higher than the voltage value at the time of the high potential V, the conductance of the driving transistor with a dirt connected to that node is increased to increase the driving ability of the bit line. In addition, the voltage of the selected sword forest is also increased in response to the voltage increase of the pit voltage. Therefore, after boosting is completed, the memory cell
The step-down speed IW of the bit line voltage that is drawn to the low level becomes faster, and high-speed read operation becomes possible.

[Examples of invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In order to clarify the principle of the present invention, FIG. 3 shows the relationship between the driving transistor T and the transfer transistor T4 when the potential VWt of the word fN10 in FIG.
The bit line voltage VEIL changes from VP to 0 by driving by
．． I Pull-in time T until reaching Vp and high “NIL”
Indicates the relationship with is't VH. As can be seen from this figure, the high potential vH of the node within the memory cell.

By increasing the number, the pull-in time T of the memory cell becomes shorter, and faster reading becomes possible. -JJ When the voltage redundancy at ■P is equal to L, the bit line voltage VIL and Vat, ! : is boosted to the boosted potential V, and its speed is 11.1.
The vH voltage when the respective voltages of nodes A and B in the memory cell reach V and Vat1 after stopping the forcible boosting of V2, that is, - The voltage that can be boosted by the precharge operation is increased to be higher than the power supply voltage VDD of the memory cell, as shown in Fig. 4.
^Potential vH voltage can be increased. However, in this case, it is assumed that the word line voltage VWL is equal to the precharge pressure V.

Furthermore, as a practical problem, the relationship between the precharge voltage V and the bit line pull-in time T is as shown in Figure @5. That is, by increasing the precharge voltage V, it is possible to start out the heel at a higher speed.

Next, an example of E for realizing the principle of the present invention described above
FIG. 6 shows an IR type smestatic memory section. A large number of memory cells are provided in the row and column directions, and memory cells in the same column commonly have a pair of bits 1j411. I
Memory cells in the same row are commonly connected to one word line IO. 20 is P with reference to Figure 1.
This is the E/IL type static memristor storage section (a frig-frozzo circuit composed of two load resistors and two driving transistors) mentioned above, and this is a pair of transfer transistors T3.

Connected to a pair of bits mJ1.1z through 1 and 4.
．． The dart of transfer transistor TI+'l'4 is connected to the word line 10. 21 is a row decoder and source line drive circuit, 22 is a sense amplifier circuit, and 23 is! In the recharge circuit, bit 4jJJ, J,? P-channel transistor PI-+P connected in series between and 1 recharge 'Kamegen V! and a transistor P connected between the bits IJ and 12, and the respective r-tos are commonly connected and a precharge gate signal vc is applied thereto. The precharge 1#4 generation circuit 24 receives the f17 charge control information vln and generates a precharge power supply V for the precharge circuit 23,
and a precharge gate signal vc, for example, as shown in FIG. 7, it is composed of 108 circuits.

That is, Il''Is is 10 to 1C from the P-channel transistor and the N-channel transistor, respectively.
In the S inpark, among these, inverters 3 to I are connected in 1u series to form a CMOS inverter M circuit 30, and control ++141 Haku No. V1,1 is manually operated 1,
The inverter and I8 are connected in series, and the control input η In is manually operated. l) a is VDD*,
One end is connected to the source and the other is the precharge power supply V, the output l) channel transistor which sends out the output, its dirt is grounded via the N channel transistor Nl, and the above via the P channel transistor P, It is strung on the other end. The other end of this is connected to the output end of the inverter - through a boost capacitor C, and the front ml in mark I□O output layer is connected to the front d self transistor N
, and P, f−) are continuously followed by t′. Note that the control tal1g vIn is the inverter II described above,
It enters into Ij, branches and outputs as the precharge gate signal vc. van I
V8B (=Ov) is a power supply voltage.

FIG. 8(-)(b) shows the voltages at each part (Nority control signal 'Fns', 'Precharge power source Vp', 'Precharge power supply Vp') to explain a series of operations of each part in FIGS. 6 and 7. X voltage, voltage on a pair of bit lines L+V
This is word line voltage VWL % High potential in memory cell vH
It shows the time relationship between the node voltage and the voltage at one end of the boost capacitor C (VD). That is, before time tl, the bit voltages ViL and VIL of -i remain at the voltage set at the time of commitment, and VBL=VDD*.
Vsh=Ov (=Vss). In addition, at this time, since vl n ''= ''c = VDO, each of the P channel transistors P1 to P of the precharge circuit 23 enters the cut-off state, and the current state occurs.
In the signal generation circuit 24, the output of the inverter I2 is VDD.
Therefore, the output transistor P4 is in a conductive state because the dart voltage is V1i8, and vP=vDD. Further, the output Vo jl'i of the C~108 inverter delay circuit 30 is at the Vss potential, and the voltage across the capacitor C is VDD.

Next, when vin reaches Vsst at time t;, vc=v
ss, and the transistor PX of the grid charge circuit 23
~P3 becomes conductive, and the pit line voltage V on the low level side
This voltage is boosted, so that V=VllL""VDD. Then, word #j at time tw! is selected, and the selected word line is set to a precharge high voltage Vp higher than the supply voltage VLII to the memory cell so that a potential VM"kL voltage can be pumped into the memory cell. , same as (2■l, L.

Pressure increases to Then, the transfer transistor 1-3 on the simple potential vH node side enters the triode operation region, and the +jJz potential v
The voltage at the H node is van the same as the precharge voltage vP.
'＼The pressure is boosted. After that, 9 is the commercial when vin falls.
The OS inverter delay circuit 30'fr is connected and its output V
D is time 1. The voltage starts to be boosted to vDD at . At this time,
The output of the inverter (2) is at V[lI tolerance potential, and the transistor N is in a disconnected state (g).

The transistor Ps is in the state J11I, and the output transistor P4 is in a cutoff state because the voltage Vp'a is applied to the dart. Therefore, when VD is boosted to VDD,
Because of the voltage VDD between near 7 f 7 t CC) #14m, V is boosted to 2 VL) D. If the valley JIt value of the external voltage capacitor C is larger than the bit line capacitance value, the pair of bit lines will be boosted to a voltage close to 2vDD by boosting V.

Then, the voltage at the high vH node in the memory cell is the pit ld1! The voltage Vll is boosted to a voltage lower than VIL by the voltage drop of the aI value of the transfer transistor T1 at the high potential ViB node.

When vin becomes VDD at the seventh interval-1 time tc, ! Each of the transistors P1 to P of the recovery circuit 23 is cut off, and the transistor selected by the word line is driven, so that a voltage drop of 5 is generated between the pair of bit lines.

Then, at time t8, the sense increase 1 positive circuit 22 starts to operate, and the 7th human power potential source lights up the nemesis, and further outputs a header signal corresponding to the magnitude relationship of the pair of pit lines 'overpressure. be done. Suppose that after the word line voltage VWt is lowered and every memory cell is electrically isolated from the pit m, v
The rising edge of In peaks the delay circuit 30, and its output V
D starts to be stepped down by 1 to V811 at time 1e. At the same time, the voltage is also lowered to Vp', and at this time, the inverter'
■The output of the camera is ML) D% Tra/Nosta N is in a conductive state, and the output transistor P4 is in a conductive state because r-t is at the Vss voltage, and the voltage is V and the voltage is VO.
Calm down to O.

FIG. 9 shows a part of a static memory according to another embodiment of the present invention, which is the same as FIG. 6 except for the precharge circuit 40 and the precharge signal generating circuit 4. The precharge circuit 40 has a dark value voltage near Ov, and its CI capacity range is -0.5 to +〇.5V. The intrinsic type transistor '1'' If
, '1' and 12, and the precharge 1g generation circuit 4
1 is an intrinsic type transistor 'rxs l T
Enhancement type transistor EI-E with summer 4 and ll & 11 direct voltage larger than intrinsic type transistor, for example +m + direct' negative pressure of 0.8 ■JiM degree.
6, the threshold voltage 11k1m is lower than the dark value voltage of the intrinsic type transistor, and the threshold voltage t is about 15V.
- Guypression type transistors D, ~D4 having
The capacitors C1+ and Cz are connected as shown in the figure, and the precharge power supply vP and ! Recharge gate 16
All the same signals are output as VC. Here, 42 is E/
A D-type inverter delay circuit, 43 forms a bootstrap potential 1-lowering circuit, and 44 forms a drive circuit. In addition, in the case of the voltage ADs, when the drive circuit output VD is outputting V2O3, the voltage of the transistor 1I4 decreases due to some reason (DI), and the voltage of the transistor 1I4 decreases due to
If you can no longer hold the VD in a vacuum
Think of it as a transistor that has the function of maintaining the potential auxiliary,
If the period in which VD is at the VDD level is short or if the dark value voltage of 1゛I4 is lower than Ov, it will be the case in all Europe.

Figures 10(,) and (b) show the valley voltages (Deliciano control gate No. 6 vfin1, recharge gate No. 16 vc, and precharge gate No. 16 vc and precharge voltage) to explain the series of operations of each part in Figure 9. vP1 pair of bit danger, )! voltage v
BL, ■This shows the time relationship between the word line voltage vIML x t voltage VM% of the high potential node in the memory cell, the voltage at one end of the boosting capacitor C2 vD, ).

That is, before time t1, the voltage is VDo, and the output transistor D4 is in a conductive state, and VPl is necessarily in a conductive state.
Both v and c are about VDD'It. Therefore,! The transistors T111 and T17 must be in conductive state, and the voltages vIL * vai, both of which are v
The voltage is close to DD. At time tW1c, as the voltage VWL of the selected word line increases, the transfer transistors T, , 'l' pass through, and the pair of bit lines 11 .
12 is a charge transistor 'l'.

1 ” Although the voltage is increased by advancing 12, the bit line 12 with one power is pulled to the V8B side via the memory cell due to the potential node pressure V in the memory cell, and the bit donated voltage VIL is The bit of force #M is a little lower than the voltage Vl11.Next, the EZD type inverter M extension circuit 42 is set to 1, and due to the fall of vIn, at time 1, transistors E4 to E6 are turned into a disconnection state. -, and the voltage at one end of the gate stop capacitor C1, v8, becomes 2.
Vl) D-VT (however, VT is 11 of transistor E3
11' peak voltage), which causes the transistor T14 to conduct and the voltage at one end of the boost capacitor Cm to be V.
OK External pressure will be applied. In this case, the dirt of the output transistor D4 is shown, and the rising pressure is already V5t.
It is S, and the external pressure capacitor C is td, so...J
Since the voltage difference between both terminals or VDD is caused by the charging of the capacitor vC2 (IIJ yHA'1lIL
If Vy, VC is boosted to 2vL,D. By boosting ■l' + vC, the pair of bit line voltages Vt
1L+V8 are both boosted. Then, at time tc, Vi
When n becomes VDD, the output transistor I)4t becomes conductive, and both V and S Vc are voltages with a voltage of vI3D'. At this time, vB L + VN L are both VD
Since the voltage level is higher than D, the precharge transistor TITITf2 is cut off, and a potential difference is created between the pair of bit lines 11 and 12 by driving the selected memory cell. Then, the potential difference is greatly amplified by the sense item number-1 circuit 22, and is outputted as a part number and a part number. However, the sense board 8-width circuit 22 used here is just a difference because it does not have a jitte hpi! It is said that it is a circuit with more songs.

Therefore, even if the sense amplifier circuit operates, the potential of the pair of bit lines will not be increased by Jvl+14. -force, vln
rising edge (No. 4 connects the delay circuit 42 to &4-C time td
, transistors E4 to E6 are made conductive, and the putt strap f voltage v8 and the voltage VD at one end of the boost capacitor q are respectively raised to Vss'. Then°C1 time tl
When the word line voltage vwi, is stepped down to V811 at I and becomes a non-selected state, the low potential V of the memory cell, the pin (N12) corresponding to the node side, is set to Vsgol by the memory cell.
It is no longer driven to ll, and returns to a voltage close to the initial vDD again by the precharging transistor T12. In each of the above embodiments, the confining capacitor C1Czlk
The #11 voltage booster circuit used is used, but for the memory cell supply 'lLJ' and Q'A Vou, a voltage higher than vDD (in other words, 2Voo) is used in circuits other than the memory cell. As a result, the same operation as in each of the above embodiments can be performed using ordinary 11 paths without using the static tolerance dish booster circuit.

The valley value of the boost capacitor φC,C is, in order to sufficiently increase the boost voltage of the Grinayanya Ryo V, the capacitor C,c connected to the node where the voltage becomes V,
It is preferable that the capacitance value is the same as or higher than the other capacitance values.In addition, the semiconductor memory device of the present invention is
Nap selection No. 11 of the semi-humiliated body collection circuit to be completed or Terra l enable gochi or address change compensation ItI
O [Effect of discovery] As mentioned above, the present invention's half-obtainable description 1. Depending on the device,
When precharging the bit line before the start operation, the bit line is boosted to a voltage higher than the supply voltage vDD to the memory cell, and the selected word line is also boosted in response to the confining voltage of the bit line. The voltage is also boosted to mfE- which is higher than vDD, and the voltage vH on the surface potential node side in the memory cell is lower than the 1st voltage during writing. By increasing the conductance and increasing the LiA dynamic capacity for the bit line, the bit voltage pulled to a lower potential by the memory cell will drop faster, allowing for faster read operations.
become capable. For example, when the embodiments shown in FIGS. 6 and 7 are applied to a 64-bit synchronous static RAM, the drive period of the bit line by the memory cell is shortened to 10 ns (20 nA in the conventional circuit), and the access The time was improved by 10 na. In addition, the embodiment shown in FIG.
When applied to the asynchronous state of the bit in RAN1, the driving time of the bit axis by the memory cell was 10n.
s (25 ns in the conventional circuit), and the access time has been revised to 15 ns.

[Brief explanation of the drawing]

Figure wJ1 is a circuit diagram showing a word line and a pair of pits in a static memory.
This figure shows the relationship between the potential node' voltage vH and the channel length of the transistor in the memory cell of FIG. 1. FIG. 3 is a diagram showing the relationship between the bit line drive time TO and the high potential node voltage V in the memory cell of FIG. 1, where fI04 is the bit line precharge voltage. FIG. 5 is a diagram showing the relationship between the memory cell's high potential mate voltage vH and the bit line 1 recharge voltage PK.
Figure 1 is a circuit diagram showing the main parts of a static memory according to an embodiment of the present invention. Figure 7 is a circuit diagram showing the recharge signal generation circuit shown in Figure 6. b
) is a voltage waveform diagram shown for explaining the operation of FIGS. 6 and 7, FIG. 9 is a circuit diagram showing another embodiment of the invention, and FIG.
0(,)(b) is a voltage waveform diagram shown for explaining the operation of FIG. 9. 10... Word 1g, 1z, xz... Bit line 12
3.40...Precharge l path, 24.41・゛. Precharge (, No. 4 generation circuit, 11m, 11=...
・Resistance element, 1゛, ~T4...Memory cell transistor, P4+04...Drive output transistor, T
E 41 D B + 1-1...Step-up transistor, P l """ P H* Tl 1 + 'l'
+ 7...klO8 for precharging) 2 registers,
Is...Inverter, C1C2...Boost capacitor〇Applicant's representative Patent attorney Takehiko Suzue Figure 4

Claims (1)

[Claims] (1) Each first cD turtle i; 7. VDp and the second “μ
A first resistor and a first enhancement type 1OS transistor are connected in series between the first resistor and the first enhancement type. A type transistor is connected to the chest,
The r-1- and drains of both transistors are connected to each other, one end of the third enhancement MOS (MOS) lannostar is connected to the drain of the first transistor on the top 6c, and the drain of the second trannostar υ is connected to the drain of the first transistor. One end of the 10S transnoster is connected to a plurality of E/N transistors arranged in the row and column directions.
A pair of bits are commonly connected to the other end of the third transistor and the other end of the fourth transistor, respectively. The word i, which is commonly connected to each gate of the third transistor and the fourth transistor in each of the same memory cells, and the word i, which is connected in common to each of the gates of the third and fourth transistors in each of the same memory cells, and the word i, which is connected in common to the respective gates of the third and fourth transistors in each of the same memory cells, and the 10 bit lines of IJTh and 1111+, respectively.
One recharge is performed at a predetermined timing via one or more precharge MOS transistors! Riciano circuit,
Absolute 1 of the first power supply voltage used in the memory cell and the power supply voltage used in peripheral circuits other than the memory cell in the above-mentioned grid charge power supply for the gutter protrusion AIJ from the memory cell due to J1!1 selection of the word line.
Pre-charge Kamiryo VP with absolute 1st shift for ward climbers *
Semiconductor memory rereading with a % value of being equipped with a precharge signal generation circuit that supplies voltage. The 1 mJ n self-bricciano generation circuit has a step-up output terminal that outputs a rechargeable power supply Vpk, which is connected to the first power supply V through an FCDMOS transistor.
DD, one end of the step-up capacitor is connected to the step-up output terminal rP*, and the other end of the step-up capacitor rP* is connected to the step-up output terminal. Claim 1: A semiconductor device according to claim 1, which is driven by a power source jdJ of the second embodiment. (:t), iiJ if the first end of the self-contained external pressure capacitor is MIJ'Bself 11th 20'α≦mi, L==
It is assumed that the output of the C to IOS inverter is connected to the output of the inverter on the ship, divided by 6 t. (4) Other products such as rJ'lJ day force pressure condenser external pressure sensor have 1 kex and 1 direct drop in -reinforcement m^self first 'La remedy ■Di). -05~+0.5V -N
10S) With the former of Ransixta as a teacher, I;Jmu,
Added to the second Denei vss, this threshold 1 garden pressure is +
] 4J rihiO8) Lannosta's 1st stitch: Straight ridge L
(5) f ;rJ H self-boosting capacitor's 6 gate 1 direct is similar to the d mouse other than the above external pressure capacitor connected to the boosted output of this external pressure capacitor.
d1 - The second term of the enclosure of the field d The beast device 1t of the self-mounted cow acquisition body. (S) The scope of the claim is that the voltage of the edge of the sword that is selected at the time of reading is increased. 1st horizontal - 14 bodies of self □ Self 1 Ji Nagao.