JPS58202624A - Analog switch circuit - Google Patents
Analog switch circuitInfo
- Publication number
- JPS58202624A JPS58202624A JP8597282A JP8597282A JPS58202624A JP S58202624 A JPS58202624 A JP S58202624A JP 8597282 A JP8597282 A JP 8597282A JP 8597282 A JP8597282 A JP 8597282A JP S58202624 A JPS58202624 A JP S58202624A
- Authority
- JP
- Japan
- Prior art keywords
- source
- voltage
- temperature
- gate
- jfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
Abstract
Description
【発明の詳細な説明】
本発明はアナログスイッチ回路に係り、特に接合形電界
効果トランジスタ（以下ＪＰＥＴと略す）を用いたアナ
ログスイッチ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog switch circuit, and particularly to an analog switch circuit using a junction field effect transistor (hereinafter abbreviated as JPET).
アナログスイッチは、サンプルアンドホールド回路、マ
ルチプレクサ回路、増幅器の利得切替回路、積分器等に
頻繁に用いられている。これらの応用のうちで、マルチ
プレクサ回路、増幅器の利得切替回路においては、信号
ラインにシリーズにアナログスイッチが入るので、アナ
ログスイッチのオン抵抗の温度特性が問題になることが
ある。Analog switches are frequently used in sample-and-hold circuits, multiplexer circuits, amplifier gain switching circuits, integrators, and the like. Among these applications, in multiplexer circuits and amplifier gain switching circuits, analog switches are connected in series to the signal line, so the temperature characteristics of the on-resistance of the analog switches may become a problem.
従来、簡単な温度特性補償回路を設けたものも考えられ
たが、その性能は満足できるものではなかった。Conventionally, a device equipped with a simple temperature characteristic compensation circuit has been considered, but its performance was not satisfactory.
以下、この問題についてＰチャンネル型ＪＰＥＴを例に
取って説明する。よく知られているようにＪＰＥＴの３
極管領域におけるオン抵抗値ＲＯＭは、式（１）のよう
に表わされる。This problem will be explained below using P-channel JPET as an example. As is well known, JPET 3
The on-resistance value ROM in the electrode region is expressed as in equation (1).
ここでｖＰはピンチオフ電圧、ＩＤ１８は最大飽和トレ
イン電流％ＶＧｌｌＩけゲート・ソース間逆バイアス電
圧である。ＶＣＳが零の時、ＲＯＭは最少値ＶＰ／２Ｉ
Ｄ８Ｂを示し％ ＶＧｊｌが正に大きくなるに従ってＲ
ＯＮ Ｆ１大きくな）、ＶＯＳがｖＰでＲＯＮは無限大
となる。ＪＰＥＴのＲＯＭは高温で大きくなり低温で小
さくなるので、ゲート・ソース間電圧ＶＧ８を高温で小
さくし、低温で大きくするように温度特性を持たせると
ＲＯＭの温度特性を補償できる事がゎわる。第１図は、
この原理を示している。同図で１．２．ａｌｌ″１′そ
れぞれＪＦＥＴ Ｊｌのソース、ドレインゲート端子で
あり、４けバッファ、５け可変電圧源である。可変電圧
源５の電圧を変えるとＪｌのＶＣＳが変わりＲＯＭが変
わる。この原理は既に知られている。実際の回路への従
来の適用例を第２図に示す。この図でスイッチのＪＦＥ
Ｔ ｌｄ Ｊｌ １ である。端子１１，１２．１３
は、それぞれソース。Here, vP is the pinch-off voltage, and ID18 is the maximum saturation train current %VGllI and the reverse bias voltage between the gate and source. When VCS is zero, ROM has the minimum value VP/2I
Indicates D8B, and as %VGjl increases positively, R
ON F1 is large), VOS is vP and RON is infinite. Since the ROM of JPET becomes large at high temperatures and becomes small at low temperatures, it is possible to compensate for the temperature characteristics of the ROM by making the gate-source voltage VG8 small at high temperatures and increasing it at low temperatures. Figure 1 shows
illustrates this principle. In the same figure, 1.2. all"1' are the source and drain gate terminals of JFET Jl, respectively, and are a 4-digit buffer and a 5-digit variable voltage source. Changing the voltage of the variable voltage source 5 changes the VCS of Jl and changes the ROM. This principle has already been explained. An example of conventional application to an actual circuit is shown in Figure 2.
T ld Jl 1 . Terminal 11, 12.13
are the respective sources.
１１、、ｌ。11,,l.
ドレイン、ゲートである。２３け温度補償されたバイア
ス電圧でその値をＶｒｅｆで表わす。１６〜１９は、抵
抗で抵抗値を几１＋Ｒ２＋凡３．Ｒ４で表わす。It is a drain and a gate. The value is expressed as Vref, which is a bias voltage compensated for by 23 temperatures. 16 to 19 are resistors whose resistance values are 1+R2+3. It is represented by R4.
ダイオードはＤＩ 、Ｄ２ 、 ）ランジスタはＱｌ。The diode is DI, D2, and the transistor is Ql.
Ｑ２．電流源は２０．２１．２２．スイッチ以外のＪＰ
ＥＴＩＪ１２ 、Ｊｌ３で表わす。Ｊｌ２とＪ１３Ｆｉ
同一形状のＪＦ’ＥＴである。、ＪＦＥ’ｌ”スイッチ
をオフさせるのは、ゲート端子を最高電位に接続するだ
けで簡単なので、以下の説明はオン状態に限る。Q2. The current sources are 20.21.22. JP other than switches
Represented by ETIJ12 and Jl3. Jl2 and J13Fi
It is JF'ET with the same shape. , JFE'l'' switch can be easily turned off by simply connecting the gate terminal to the highest potential, so the following explanation will be limited to the on state.
スイッチ１１のソース端子１１の電位は、Ｊｌ３により
検知される。Ｊｌ３とＪｌ２け全く同一形状なのでＪｌ
２ 、Ｊｌ３のソース・ゲート間電圧は等しい。ここで
Ｊｌ２のソース・ゲート間電圧ＶＧ８１２は次のように
表わせる。The potential of the source terminal 11 of the switch 11 is detected by Jl3. Since Jl3 and Jl2 have exactly the same shape, Jl
2, the source-gate voltages of Jl3 are equal. Here, the source-gate voltage VG812 of Jl2 can be expressed as follows.
ここでＶＢＥはダイオードの順方向降下電圧値或は、ト
ランジスタのペースエミッタ間電圧値を表わす。端子１
１のソース電位は、Ｊｌ３のゲルトソース間電圧、Ｄ２
の！一方向降下電圧、Ｑ２のペース・エミッタ間順方向
降下電圧をシフトして端子・１・、。Here, VBE represents a forward drop voltage value of a diode or a pace emitter voltage value of a transistor. terminal 1
The source potential of 1 is the gelt-source voltage of Jl3, D2
of! One-way voltage drop, Q2's pace-emitter forward voltage drop is shifted to terminal 1.
１３に伝達されるのでＪｌｌのゲート・ソース間電圧Ｖ
Ｇｌｉｌｌとその温度係数””ｕ、（３） 、 （４１
式で表Ｔ
わす事ができる。13, so the gate-source voltage V of Jll
Grill and its temperature coefficient ""u, (3), (41
It is possible to write the table T in the formula.
この従来例では、ＪＦＥＴのオン抵抗の温特をＶＢＥの
温度特性（約−２，Ｏｎｎｏ／ ０Ｃ）で補償している
事が（３） ｌ （４１式かられかる。しかしながらＪ
ＦＥＴとダイオード、トランジスタの拡散プロファイル
は全く違うのでＪＰＥＴのパラメータ■Ｄ８８ ＋ ｖ
Ｐの温度特性、バラつきを上記ＶＢＥの温度特性で補償
する方法は、不十分であり、温度特性はわずかに改善さ
れたにすぎなかった。In this conventional example, the temperature characteristics of the on-resistance of the JFET are compensated by the temperature characteristics of VBE (approximately -2, Onno/0C).
Since the diffusion profiles of FET, diode, and transistor are completely different, the JPET parameter ■D88 + v
The method of compensating for variations in the temperature characteristics of P using the temperature characteristics of VBE is insufficient, and the temperature characteristics are only slightly improved.
本発明は、上記問題点を解決し、ＪＦＥＴのオン抵抗の
温度補償を完全にするものである。The present invention solves the above problems and completely compensates the temperature of the on-resistance of the JFET.
本発明の特徴は、例えばアナログスイッチとなる第１の
ＪＰＥＴのソース電位は、利得が１倍のバッファ回路に
より検出され、このバッファ回路出力には温度補償され
たバイアス電圧源と比較用の第２のＪＰＥＴのソース端
子が接続され、このバイアス電圧源の他端と第２のＪＰ
ＥＴのドレイン端子５−
は演算増幅器のそれぞれ反転入力と非反転入力端子に接
続され、さらに第２のＪＦＥ’Ｉ’のドレイン端子は、
温度補償された定電流源に接続され、且つ前記演算増幅
器出力は第１．第２ＪＦＥＴのゲート端子に接続された
アナログスイッチ回路にある。A feature of the present invention is that, for example, the source potential of the first JPET, which is an analog switch, is detected by a buffer circuit with a gain of 1, and the output of this buffer circuit is connected to a temperature-compensated bias voltage source and a second JPET for comparison. The source terminal of the second JPET is connected to the other end of this bias voltage source and the second JPET.
The drain terminal 5- of the ET is connected to the inverting and non-inverting input terminals of the operational amplifier, respectively, and the drain terminal of the second JFE'I' is
connected to a temperature compensated constant current source, and the operational amplifier output is connected to the first. It is in an analog switch circuit connected to the gate terminal of the second JFET.
以下、本発明の一実施例につき図面を用いて説明する。Hereinafter, one embodiment of the present invention will be described using the drawings.
第３図に本発明の一実施例のアナログスイッチ回路を示
す。図でＪ３１がスイッチ用のＪＰＥＴ。FIG. 3 shows an analog switch circuit according to an embodiment of the present invention. In the figure, J31 is the JPET for the switch.
３６は演算増幅器（以下オペアンプ）、Ｊ３２．Ｊ３３
゜Ｊ３４はＪＰＥＴでありＪ３２とＪ３３け全く同一形
状である。Ｄ３はダイオード、Ｑ３はＮＰＮ）ランジス
タ、 ３７ 、３８は定電流源、３５は温度補償された
バイアス電圧源であり、その値をＶ’ｒｅｆで表わす。36 is an operational amplifier (hereinafter referred to as an operational amplifier), J32. J33
゜J34 is JPET, and J32 and J33 have exactly the same shape. D3 is a diode, Q3 is an NPN) transistor, 37 and 38 are constant current sources, and 35 is a temperature compensated bias voltage source, the value of which is expressed as V'ref.
特徴的なのは、比較基準ＪＦＥＴ Ｊ３４を設けである
事と１オペアンプ３６を使ってＪＦＥＴのゲート・ソー
ス間電圧ＶＯＳを制御する事である。The characteristics are that a comparison reference JFET J34 is provided and that one operational amplifier 36 is used to control the gate-source voltage VOS of the JFET.
Ｊ３４ｉオペアンプ３６の負帰還ループ内にある。It is in the negative feedback loop of the J34i operational amplifier 36.
オペアンプ３６の反転入力端子４０と非反転入力端子４
１間電圧は、オペアンプ利得が十分高いとすれば−等し
い。即ちＪ３４のソース・ドレイン間６−
電圧は、Ｖ’ｒ ｅ ｆに等しい。又、定電流源３７の
電流値ｅＩｏで表わすと、Ｊ３４のオン抵抗ＲＯＮ３４
は、（５）式で表わされる。Inverting input terminal 40 and non-inverting input terminal 4 of operational amplifier 36
If the operational amplifier gain is high enough, the voltage between the two is equal to -. That is, the source-drain voltage of J34 is equal to V're f. Also, when expressed as the current value eIo of the constant current source 37, the on-resistance RON34 of J34
is expressed by equation (5).
周囲温度の変動に伴いＪ３４のＩＤ８Ｂ ＋ ｖＰは変
化し、Ｊ３４のオン抵抗も変化しようとするが、上記オ
ペアンプを使った負帰還作用によりＪ３４ のソース
・ドレイン間電圧がＶ’ｒｅｆに等しくなるように、Ｊ
３４のゲート電圧が変化しオン抵抗の変動を抑圧する。ID8B + vP of J34 changes as the ambient temperature fluctuates, and the on-resistance of J34 also tends to change, but the negative feedback effect using the above operational amplifier keeps the voltage between the source and drain of J34 equal to V'ref. ni, J
The gate voltage of 34 is changed to suppress fluctuations in on-resistance.
Ｖ’ｒｅｆとＩｏ＃′ｉ温度補償されているので％（５
）式かられかるように、Ｊ３４のオン抵抗は温度変化に
対して一定に保たれる。こむでＪ３１のソース端子３１
の電圧は、Ｊ３４のソース端子３９の電位に等しい。何
故ならＪ３２とＪ３３は全く同一形状なのでＪ３３のゲ
ート舎ソース電圧は零ボルトであるからである。オペア
ンプ３６の出力端子４２は、Ｊ３４のゲートと共にスイ
ッチＪ３１のゲートにも接続式れているので、出力スイ
ッチＪ３１のゲート・ソース間電圧ＶＧ８もＪ３４のＶ
ＧＳ／と同じ値だけ変化する。Ｊ３１とＪ３４Ｈディメ
ンシ冒ンーチャネル長とチャネル巾−が異なるだけなの
でＪ３４のＲＯＭと共にＪ３１のＲＯＭも温度補償され
ることくなる。さらに本発明によれば、ＪＰＥＴのプロ
セスパラメータＩＤ８１ｉ ＋ ｖＰがロット間で大き
くバラついてもバイアス電圧源Ｖ’ｒｅｆとＩｏのみで
ＲＯＮが決まるので、Ｊ３４．Ｊ３１のオン抵抗の絶対
値のバラつきも抑圧される。一般にＶ’ｒｅｆ、Ｉｏの
バラつきは％ ”Ｉ）８８１ ｖＰのバラつきに比し小
さいからである。Since V'ref and Io#'i are temperature compensated, %(5
), the on-resistance of J34 is kept constant against temperature changes. Komude J31 source terminal 31
The voltage is equal to the potential of the source terminal 39 of J34. This is because J32 and J33 have exactly the same shape, so the gate-to-source voltage of J33 is zero volts. Since the output terminal 42 of the operational amplifier 36 is connected to the gate of the switch J31 as well as the gate of J34, the gate-source voltage VG8 of the output switch J31 is also VG8 of the output switch J34.
It changes by the same value as GS/. Since J31 and J34H differ only in dimensionality, ie, channel length and channel width, the ROM of J31 as well as the ROM of J34 will be temperature compensated. Further, according to the present invention, even if the JPET process parameter ID81i + vP varies greatly between lots, RON is determined only by the bias voltage sources V'ref and Io, so that J34. Variations in the absolute value of the on-resistance of J31 are also suppressed. This is because the variations in V'ref and Io are generally smaller than the variations in %I)881 vP.
こうして本発明け、プロセス変動、温度変動によるＪＰ
ＥＴパラメータ変動を押える事ができ従来、間頓となっ
ていたＪＰＥＴのオン抵抗値の温度変動を極めて効果的
に補償すると共にその絶対値のバラつきも小さくする事
が可能となり、秀れたアナログスイッチを供給でき喪。Thus, with the present invention, JP due to process variations and temperature variations
It is an excellent analog switch that can suppress ET parameter fluctuations, extremely effectively compensate for temperature fluctuations in the on-resistance value of JPET, which conventionally occurred intermittently, and also reduce variations in its absolute value. Can supply mourning.
又、各素子の極性を変えれば不発明ばＮチャネル型ＪＰ
ＥＴにも適用できる事は明らかである。Also, if you change the polarity of each element, you can create an N-channel type JP.
It is clear that this can also be applied to ET.
第１図はゲート・ソース電圧を可変とするＪＦ’ＥＴア
ナログスイッチ回路、第２図は従来の温度補償Ｊ Ｉｉ
’ＥＴアナログスイッチ回路、第３図は本発明実施例の
温度補償ＪＰＥＴアナログスイッチ回路、である。
々お図において、１・・・・・・ソース、２・・・・・
・ドレイン、３・・・・・・ゲート、４・・・・・・バ
ッファ、５・・・・・・可変電圧源％１１・・・・・・
ソース、１２・・・・・・ドレイン、１３・・・・・・
ゲート、２３・・・・・・温度保償されたバイアス電圧
、１６〜１９・・・・・・抵抗−ＤＩ ＋ Ｄ２・・・
・・・ダイオードｂＱｔ＋Ｑｚ・・・・・・トランジス
タ、 ２０〜２２・・・・・・電流源、Ｊ１２．Ｊ１３
・・・・・・ＪＦＥＴ、Ｊ３１〜Ｊ３４、・・・・・Ｊ
ＦＥＴ、３５・・・・・・温度保償されたバイアス電圧
、３６・・・・・・演算増幅器・ ３７．３８・・・・
・・定電流源、４０・・・・・・反転入力端子、４１・
・・・・・非反転入力端子 である。
代理人 弁理士 内 原 晋
−９−・
第 １ 図
第 ２ 区Figure 1 shows a JF'ET analog switch circuit with variable gate-source voltage, and Figure 2 shows a conventional temperature compensated J Ii.
Figure 3 shows a temperature compensated JPET analog switch circuit according to an embodiment of the present invention. In the diagrams, 1...source, 2...
・Drain, 3...Gate, 4...Buffer, 5...Variable voltage source %11...
Source, 12...Drain, 13...
Gate, 23...Temperature guaranteed bias voltage, 16-19...Resistance -DI + D2...
...Diode bQt+Qz...Transistor, 20-22...Current source, J12. J13
...JFET, J31-J34, ...J
FET, 35... Temperature guaranteed bias voltage, 36... Operational amplifier 37.38...
...Constant current source, 40...Inverting input terminal, 41.
...It is a non-inverting input terminal. Agent Patent Attorney Susumu Uchihara-9- Figure 1, Ward 2
Claims (1)
おいて、スイッチされる信号が伝送される第１の電界効
果トランジスタと、該第１の電界効果トランジスタのソ
ースに接続されたバッファ回路と、該バッファ回路の出
力に出力の一端が接続されたバイアス電圧源と、該バッ
ファ回路の出力にソースが接続された第２の電界効果ト
ランジスタと、該バイアス電圧源の出力の他端が反転入
力に接続され該第２の電界効果トランジスタのドレイン
が非反転入力に接続され出力が該第１および第２の電界
効果トランジスタの各々のゲートに接続された演算増幅
器とを含んで構成されることを特徴とするアナログスイ
ッチ回路。An analog switch circuit using field effect transistors includes a first field effect transistor to which a signal to be switched is transmitted, a buffer circuit connected to the source of the first field effect transistor, and an output of the buffer circuit. a bias voltage source having one end connected to its output; a second field effect transistor having a source connected to the output of the buffer circuit; and a second field effect transistor having the other end of the output of the bias voltage source connected to the inverting input. An analog switch circuit comprising: an operational amplifier having a field effect transistor whose drain is connected to a non-inverting input and whose output is connected to each gate of the first and second field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8597282A JPS58202624A (en) | 1982-05-21 | 1982-05-21 | Analog switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8597282A JPS58202624A (en) | 1982-05-21 | 1982-05-21 | Analog switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58202624A true JPS58202624A (en) | 1983-11-25 |
Family
ID=13873635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8597282A Pending JPS58202624A (en) | 1982-05-21 | 1982-05-21 | Analog switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58202624A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572161A (en) * | 1995-06-30 | 1996-11-05 | Harris Corporation | Temperature insensitive filter tuning network and method |
| DE102010012688A1 (en) * | 2010-03-24 | 2011-09-29 | Dspace Digital Signal Processing And Control Engineering Gmbh | Switching arrangement with temperature compensation |
-
1982
- 1982-05-21 JP JP8597282A patent/JPS58202624A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572161A (en) * | 1995-06-30 | 1996-11-05 | Harris Corporation | Temperature insensitive filter tuning network and method |
| DE102010012688A1 (en) * | 2010-03-24 | 2011-09-29 | Dspace Digital Signal Processing And Control Engineering Gmbh | Switching arrangement with temperature compensation |
| US8446208B2 (en) | 2010-03-24 | 2013-05-21 | Dspace Digital Signal Processing And Control Engineering Gmbh | Circuit arrangement with temperature compensation |
| DE102010012688B4 (en) * | 2010-03-24 | 2014-05-15 | Dspace Digital Signal Processing And Control Engineering Gmbh | Switching arrangement with temperature compensation |
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