JPS58201443A - Synchronizing network loop connecting system - Google Patents

Abstract

PURPOSE:To attain the locking in clock phase and error correction at a receiving side, by encoding information symbols into codes possible for error correction at terminal stations on each network, when >=2 line networks are combined at a point respectively, and broad connection of communication networks is performed. CONSTITUTION:Two loop networks alpha and beta are connected at a combining node C, and a transmission frame has a slot given to a node connected to the loop alpha and a slot given to a node connected to the loop beta. In a master clock source 80, the frequency is adjusted by applying a timing signal obtained when a receiving signal of the loop is received at a receiving section 71, via a sample value data system 70. The receiving signal is received at each high order station of both the loops alpha and beta, processed for operation in accordance with the algebraic rules at vector circuits 72, 77 for the detection of errors, and the phase synchronism is controlled. The receiving data is encoded for codes possible for error correction at vector circuits 74, 75 via transmission and reception circuits 73, 76 and transmitted to a low order stations.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a synchronous network loop connection system, in particular, when a communication network is connected over a wide area, it eliminates false synchronization, minimizes the decline in transmission efficiency, and achieves correctness. 6. Concerning a synchronous network loop connection method that enables and improves reliability, when configuring a public communication network or a Fi-C network using a conventional digital transmission method, a method of providing a transmission channel by a slot of a transmission frame; There is a method of giving calls on a first-come, first-served basis. In addition, when constructing a communication network using a digital transmission method, code synchronization must be performed in some way. Conventionally, code synchronization was achieved by adding a regular part to the code sequence. . However, these regularities are carried out independently of the information symbols to be transmitted, and it is necessary to maintain a code distance between the code sequence based on these regularities and the information symbol.
This has the disadvantage of increasing redundancy. Further, although such a coding method is known to indicate the ms position of an information symbol (such as a C10 code), it is necessary to reduce the transmission efficiency to less than 100% for correction.

Furthermore, in order to expand the communicable area, it is necessary to connect the above-mentioned line networks, but with conventional digital transmission systems, connecting a single line network causes a drop in transmission quality. become.

Therefore, prior to the present application, the present inventor performed division using the law of self-correcting encoding, which is a method of algebraic encoding, on the transmitting side, and determined that the received code was created according to the same law. We have proposed a method to check the above using the t'JIJ h method and a method to perform synchronization using it (Special It(I)).
Tfj No. 57-46018ry L, -MullJ
Patent Application No. 57-46019 “Loop Transmission System”
.

(See Japanese Patent Application No. 57-544-34 ``Asynchronous Connection System,'' etc.)

OBJECTS OF THE INVENTION An object of the present invention is to improve the conventional drawbacks by
An object of the present invention is to provide a synchronous network loop connection system that can increase reliability by eliminating test synchronization, minimizing the decrease in transmission efficiency, and performing error correction when connecting a wide area network.

Comprehensive defense d) In order to quickly achieve the above purpose, the synchronous I14 loop connection system of the present invention provides two transmission links each sharing seven transmission frames of a fixed length and forming a closed circuit with a plurality of transmission links. The line networks are connected at one point, each transmission frame sequence is synchronized at this point, and at the terminal station on each line network, information symbols are manipulated according to algebraic laws on the transmission side. The clock phase of the receiving side is set based on the output of the register that configures the transmission frame and detects that the above algebraic law is consistent with the above-mentioned algebraic law in the receiving operation 1, and the error of the information symbol is corrected. .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the Invention Synchronization Method FIG. 1 is a logic diagram of a division V path by a generator polynomial on the transmitting side.

It is created by calculating a polynomial having a frequency of (K-1) or less using the code 1SVi and its generating polynomial gfX) using an arbitrary information symbol as a coefficient. Now, let's consider a vector whose components are the logic of each bit that makes up a code word, and this is called a code petator. In general, a code vector is made up of a given number of information symbols and a check symbol with h< n-K (l). This check symbol corresponds to a self-correcting code. .

Among the encoding methods described above, there is a method to obtain what is called a cyclic code, which is calculated using the following procedure.

Now, f(100wo, X” ”, X”s, ---
Suppose that K %M including The component of is 0, and the following components correspond to a vector consisting of arbitrary information bits.If such a polynomial fo(a) is divided by the generator polynomial g(X), the following relational expression is obtained. To establish.

foOO-g(X)q(X)tenrcO10,α) Above (
1) In the formula, n - g, which is the frequency of r OO minus goO
It has a smaller frequency.

Therefore, the following equation is derived from the above equation α).

f(,00-rcX)-g(Xi qclN
-...O f in equation e) above. The coset (f, (a)-r(X)) whose representative is (X)-r(X) is a code vector. Since it has a number smaller than r(a)Fin-ic, all terms with a frequency of n-K or more are 0. However, since all terms in tt m smaller than n- in to(1) are 0, f, (, Xl
The terms with high frequencies in −r (X) are the given information bits, and the terms with low l# numbers are check signals determined by the information bits.
-r(X) of focus. Such a combined code vector can be created by the circuit shown in FIG. The division field by the generator polynomial goo of ffjxJ is shown in FIG.

K information bits, which are city frequency coefficients, and n K pieces J)
The polynomial f, which has 0 as a low frequency coefficient, is shifted from high frequency coefficients first until the last coefficient is added to the low frequency position of the shift register. For the information symbol and for the low frequency O, there are n −K gold phases Ω (1t shift 0 in Fig. 1.Do −qo+q1+ q,X”+ −− -qnX
” goo-go+g, X+ g2X”−+−−−
-grl, the operation of dividing by 'ill' n-1
is the first coefficient of the quotient. For each coefficient gi of the dividing equation, the polynomial qig(X) is subtracted from the dividend! [This is done by the feedback path 11 in FIG. 1. After a total of n shifts), the completed quotient appears in the output. The remaining ◆rOO is then included in the shift register. Since the residual rQQ is the checker bits with a negative sign added, these check bits are assigned to 0 at the (rooo) degree 11 position to form a code vector.

Transmission is performed as follows. That is, information symbols are first shifted into the device of FIG. 1 and transmitted to the communication channel in parallel. K
At the same time as ll information symbols have been input into the shift register, n- bits V! of the register have been input. The remainder will be retained.

This is a 1 with a negative sign added to the check symbol. Next, the feedback circuit of the shift register is disconnected by the switching path (b), and the contents of the shift register t
Shift output. In this case, the bit output from the shift register is transmitted to the communication channel through the contacts 1 and 2 of the switching circuit P) while inverting the polarity. These n check symbols together with the m information symbols of KM complete the code vector. In addition, circuit 3 is 1
This is the beginning code and the light code's ukuchi - 艷.

FIG. 2 is a block diagram of one receiving side showing an embodiment of the present invention.

On the receiving side, when the code vector transmitted by the method shown in Figure 1 is input, this code is generated by the generator polynomial g(X]
It will be divisible by . The decoder is 9! Buffer register 7 stores the multiplied number 1, and the ``sign'' is 1!
(A has a shift register number of 111 Jl. Then, if each remaining bit of the division becomes O,
This means that the code pexyl has been received without error, and by detecting this, the reception fd synchronization of the transmission frame can be achieved.

In FIG. 2, shift register 4 is connected to memory device r −' r and coefficient device 0 of FIG.
! 1-Otori-l Chair-It has g0 to g-1, etc., and divides the code input from the receiver (to the d terminal). At the same time, the received code is input to the buffer register 7 and temporarily stored. Inspection a
In the i circuit 5, each bit of the shift register is all O.
A signal is sent to the crotter generator 6 upon detecting that the curvature is the same. The multiphase clock generator 6 operates by being supplied with a clock from the bit clock terminal in order to generate a multiphase clock of the input rJ 8 *, i circuit.
The black ivy from the first child (G) is also supplied to the other blocks in FIG. 2, thereby making one crop each. The output 6F-) of the detection circuit 5 is generated as if each bit of the shift register 4 is O, thereby resetting the multiphase generator 6. By resetting the multiphase clock generator 6, the timing of the multiphase clock is adjusted so that the timing that can be outputted through the circuit ('J) for each symbol of the buffer register 7 is appropriate. The phase is set. Then, at each slot time of the transmission frame, the contents of the constituent bits of the corresponding frame are read out to the output bit. A reset pulse is generated for each frame of the received code, but If talk occurs, naturally the reset pulse will not occur. However, assuming that the clock supplied to the multi-phase clock generator 6 is unrelated to this reset pulse, the phase of the multi-phase clock will match with the reset pulse when the transmission frame of (I is received). If the current 7 frames do not have a reset pulse, a polyphase signal with the correct phase will be obtained. Even without a reset pulse, a polyphase signal will occur, but a reset pulse will never occur. It is not unnecessary, but without this reset pulse, it will naturally not be possible to synchronize with the 7th frame of the received code, so it is necessary to reset the multiphase clock generator 6 when the desperation transmission frame is correctly received.

The codes constituting the transmission frame are generated by the generator polynomial g(
X) can be divided by lP]. The transmission frame is filled with such codes. 2) When the 0 codes occupied by the field are exhausted, the line (a) shown in Fig. 2 is filled.
This resets the multiphase clock generator 6 on the receiving side, and maintains a normal operating phase on the receiving side. By the way, transmission 7
The frames are transmitted continuously without any transmission down time. In this way, if an l bit is generated in the 'lk' state and the remainder of the division created by shift register 4 does not become O at the normal timing, the next transmission frame will not be transmitted correctly. The remainder of Teyake Sho division does not become 0. However, in order to prevent this from happening, it is necessary to provide a function field with a specific code configuration that indicates the beginning and end of the transmission frame in a field other than the code vector of the transmission frame. . That is, a switching circuit (c) and a start/end code sending circuit 5 are provided on the transmitting side in FIG.
Before (b) is restored and the next information bit appears at the input terminal, the switching circuit (c) is switched from 1 to 2 and the start code is sent from the sending circuit 3 following the end code. After that, it will return to its original state. On the receiving side, it is necessary to provide a circuit for detecting the code in the generator polynomial g00 from this redness and the diameter from which the starting code is extracted, and the shift register 8 in FIG. 2 plays this role.

The shift register 8 receives the code inputted from the reception terminal (3) while shifting it, and outputs a reset output when the code configuration created by the logical value of each bit is the above-mentioned ending and beginning 7-antasi code configuration. to shift register 4)
Set the remainder register of the divider circuit to 9-. Although a method of providing start and end codes and detecting them on the receiving side has been used in the past, in the present invention, without immediately resetting the polyphase tatada circuit 6, it is possible to detect code tatters. After performing this, the multi-phase p-block circuit 6 is reset.

Note that in order to reset the remaining registers without using the shift register 8 in Fig. 2, it is necessary to provide a space time equal to the length of 7 transmission frames, but since lagging causes a large loss in transmission efficiency. There should be no undesirable, long spaced pauses between the end of one transmission frame and the start symbol of the next transmission frame.

(n correction method Figure 3 is a splitter diagram of the correction iE circuit used in the present invention), and Figure 4 is a block diagram of a synchronization and bit correction/parallel execution circuit showing an embodiment of the present invention. .

Assume now that a code vector (f(Xi)) is transmitted.

At this time, an imposition occurs, and on the receiving side, assuming that a code that is higher than the code vector by y (1) is received, then l
l(Xi is the Kujirasho pattern. And the received code is g
By calculating m with oo, lI and the pattern are also divided, but this division will be called a parity check. If the result of the parity check is the residual R(X), then the following formula holds: O EOO-g(X)S(X)+R(X)
...-6) Multiplying the remainder R(X) by X and dividing by g(X) can be expressed as follows.

X'R(X) -goo 8□CO+ R1(X)
-・-4) The following equation is derived from the above equations O) and (a).

X 1(X)-R, Do-X g(X) 8(X)+
t(A 8.00 -・-5) above) equation (x, m(
1) −R1(1)) is a code vector t, v<
L, ka(XilCX)) ト(R1(XI)ka) should also be included in the surplus amount.

The correction of #l#) is to execute the left side of the above equation), and is carried out using the circuit shown in Figure 3.

In FIG. 3, 9 is the memory device (
r-r) and its peripheral devices/n-
1 is a shift register with a circuit whose contents are R1(X).

B) is the receiving terminal of the communication channel, and during code reception, the switching circuit (B) is closed and the switching circuit (B) is open.

The parity check is calculated by the S calculation circuit 9 used during encoding over the entire received code vector.

At the same time, the received No. IV vector is recorded in the buffer IO.

The parity check is completed at the same time as the reception of the received code vector is completed, and then the switching circuit (open) and the switching circuit (→) are closed in order to perform the correction according to equation b) above.

The shift registers 9 are sequentially diaded, and at the same time when one symbol is output one after another, one symbol is output one after another from the buffer 10. This process is repeated, and at the step where there is one selection,
The error is corrected by subtracting the output symbol of the shift register 9 from the output symbol of the buffer 10 in the arithmetic unit 11. (to) is the terminal from which this corrected output is obtained.

The most common form of hollow pattern is burst deception.

This burst error pattern is expressed as (X'BOO). Therefore, the received code 1t(
f(X)+XjBOO)tonal.

A parity check is performed on the receiver side by dividing f(X)+XjB(X) by g(X), and the balance is retained.

If the remainder is 0, the code candy has been received correctly, or 0
Otherwise, it will contain the distortion information 〇Here, since (foo)t-j code vector, f
Divisible by ooFi (1). Therefore, the parity check residual is equal to XjB(X) divided by zc)O.

Now, suppose that XjB■ is expressed by the following formula, OXjl1
00=glX)8(X)+R(Xi...
・6) Here, Roo has a smaller power than the power n- of the irises.

The kneading correction method described in (3 to (6) above and the circuit shown in FIG. 3 are for determining the above-mentioned XjB c)O.

In the above formula, (E(XI)-(XjB(X))
and i −n −j, the following equation is derived.

X'RCX) -X'"jBsen-x i, ■Sm-(
X”-1)j3tX)-X g(a)soo+ncx
...σ) Here, X''-1 is divisible by goo, and if B(Xl has a frequency smaller than the frequency n- of g(N, then B(X) is Xl)t( X) to g
There must be a true remainder when divided by (X). From this, the above (→.

Operation of equation (5) is nothing but deleting B(Xi). Note that if the frequency of B(X) becomes larger than n-, the limit of error correction ability is exceeded, so other Corrections will be made by means.

Figure 2 shows a circuit that performs 7-rem synchronization on the receiving side.
Figure 3 shows a circuit that performs smear correction on the receiving side.

In order to create a circuit capable of synchronization and error correction using these, it is necessary to improve the circuit shown in FIG. 2.

Shift register storage in FIG. 2 corresponds to shift register 9 in FIG. 3, and buffer register 7 in FIG. 2 corresponds to buffer register 10 in FIG. Therefore, in order to improve the circuit to be able to correct the second Q, it is necessary to adopt the circuit system shown in Figure 3 on the output side of the buffer register 7. However, in the current state, the 2) to the reception terminal in Figure 2), it becomes impossible to receive 1). Therefore, the 2vth shift register 4 is set to 2 (in general, one maintains the state shown in Fig. 2, but the other
Error correction may be performed according to the purpose of the diagram. That is, the contents of the shift register 9 are transferred to the other shift register 9 at the timing when the code is set in the buffer register 7 by the multiphase clock from the multiphase clock generation circuit 6 shown in FIG. , the reading correction shown in FIG. 3 may be performed.

A circuit that simultaneously performs synchronization and correction of blank bits is shown in FIG. This circuit includes a same-order shift register 14, a synchronization detection circuit i13 that detects when its output becomes 0,
A multiphase tarlock generation circuit 16 that is reset by the output of the synchronization detection circuit 13, and a shift register 1 for manufacturing correction.
1, a buffer register 12 for inputting the received code,
Shift register 17 shifted by polyphase clock
and a reset circuit 16.

When the code of one frame input to the receiving terminal) is input to the synchronization shift register 14 and the buffer register 12, the shift register 14 converts the input code to g(X
) to output the remainder. When the synchronization detection circuit 13 detects that the output of the shift register 14 becomes 0, the multiphase clock generation circuit 16 is reset by the output. When the multiphase tarlock generation circuit 16 outputs a clock to round off the time when the code of one frame ends, the contents of the synchronization shift register 14 are transferred to the shift register 11 having the same logic configuration, and from then on. , corrects the received code output from the buffer register 12 and sends it to the next stage buffer register 17.

To perform the division of the subsequently received transmission frame, shift register 14. Since the remainder of d@ needs to be cleared, the output d@ of the reset circuit 15 is sent to the shift register 14 via the reset line.

Extraction of information in the desired time slot 5 of the transmission frame and transmission to the terminal 11i! is performed using the corrected data, that is, the output of the buffer register 17, according to instructions from the multiphase clock. R is a support 1η mounted, and '8 is a transmitting device.

Transfer from the buffer register 17 to the receiver 41 f[IR is performed through the -ring gate 1.2.3, ANDed with the polyphase tarlock output, and sent out. In addition, the transmission from the transmitting device g to the transmission system located next to the buffer register 17 is performed through logic games 4, 5, and 6, and is ANDed with the polyphase click output and output to the buffer register 17. After admiring it there for a while, the data is shifted one bit at a time and transferred one bit at a time to the transmission system (A). Note that the clock added to the logic game 1,2°3 is smaller than the clock added to the corresponding logic gate 5.6.
It is necessary to construct the polyphase tarot generator circuit 16 so that it appears l steps ahead.

In the above explanation, the self-correction of the trial bit in frame transmission was performed, but this also applies to writing to an external storage device used in an information processing system, etc.

It can also be applied to continuous reading, and by making encoding and correction correspond to writing and reading, respectively, the external memory 1
It is possible to improve the reliability of Zeng.

FIG. 5, FIG. 0, and FIG. 7 are all part of the present invention]
It is a diagram explaining the operating principle of an arithmetic circuit, and FIG. 6 is a circuit that divides an arbitrary polynomial by a special space polynomial, and FIG. 6 is a specific example of a division circuit on a field consisting of two elements, and ts7 diagram. 6 shows the case where the division shown in FIG. 6 is performed by arithmetic operation.

It, g(X) - go 10g1X+ ---+grXr
If you create a circuit that divides teL(X)-~Toki, X0...+dX'', it will look like the one shown in Figure 6.

The altitude is input in order starting from the first term, and the xr term is stored in the register 29, then the xr1 term...the X term is stored in the register 22, and the 0 term is stored in the register 21. The recording device must be turned on initially. The first input symbol arrives at the last stage of the shift register #I is the output 0 for the first r shift. Then the first non-zero output appears. This is a! 1gr, which is the first 4fL number of the quotient.

For each coefficient g1 of the dividing equation, the polynomial q1g(X) must be subtracted from the divisor. This is Is5
This is done using the connection shown in the figure. After hitting the n1 shift with a total of 815, the completed quotient appears at the output and the remainder remains in the shift) register.

Figure 6 shows g(1)-1 on a field consisting of two elements.
It is a circuit that divides the input polynomial by +X”+
'+X"+ 1-c x'+ x"+-xlo+X'+
When dividing X'-1-X"+ X + 1, the seventh
The quotient is obtained by performing a round calculation as shown in the figure, and this method can be easily explained by comparing this method with the operation shown in FIG. However, calculation 7
In the case of the calculation by hand in the figure, the altitude 1d is on the left, but
In shift register 3 to 6 in Figure p, 6, the altitude 1 term is on the right side.

In FIG. 6, the first 61 shifts do not correspond to the paper in FIG. Shift after 6 shifts) Register 31~
Contents of 36 LL '1° 7v part A and one mosquito.

The first descendant / is the first quotient symbol and is also the output after seven sheets. The feedback matches the polynomial marked B and the input corresponding to C downgraded. After the seventh shift, the contents of the shift register match the polynomial marked D. The feedback matches F lowered to the next stage, and y is the same as the input. And after the 8th shift, the contents of the shift register match G. This process continues until 14 shifts, at which time the shift register holds the quotient for each coefficient of the dividend and the quotient coefficient is output.

(c) Transmission system FIG. 8 shows the origin of the transmission system using the present invention. In the transmission system to which the present invention is applied, the code format flowing through the closed circuit transmission link as shown in FIG. However, it is constructed by the ivy code 11ft. Of each terminal station or system that is the 7th node of the transmission system, the station 41 has a switching function, and the terminal station devices 42 to 44F
The i-terminal device is connected, and the processing unit 45 performs information processing or verification processing, and the communication between the loop-shaped transmission line β, which is a subsystem of the transmission network α, and the transmission network α) is performed.
Has an exchange function. Each 7 connected to loop-shaped transmission line α
- nodes share the transmission frame and circulate through the transmission network α IId. Note that the originating and receiving call processor 4o directly transfers exchange information to the exchange 41. Information symbol part 3 of transmission frame
It consists of 4 parts: the first part is general information, the second part is call information, and the third part is call information. α network exchange 84
Time-sharing slots are allocated to node stations other than 1 and the call processor 11A40, where the first part and the second part are processed by the switching center 41, and the third part is processed by the call processor 40. It is processed.

In the loop network ψ, it is generally necessary to provide the transmission processing function of the node 1-1 other than the switching center 41 and the originating/receiving call processor 40.

FIG. 9 is a block diagram of the transmission processing function of each node station in FIG. 8.

At 45 in FIG. 9, a receiving section 52 is a receiving section of a line terminator 59 that receives signals from an upper station, and a mask clock source 50 automatically adjusts the fundamental frequency by voltage control.
Meals are available. The sample value data system 51 detects bit clock timing information from the scrambling baseband signal received by the receiver 52 using the well-known signal emm method, and operates based on the bit clock. Then, a voltage that controls the timing information in the direction of zero is applied to the master clock and to the oscillation frequency control terminal 60. Vector circuit No. 6 is operated by the bit input from the mask clock source 50, and is operated by the error correction shift F register 11 and the buffer register 11 in FIG.
Register 12, synchronization detection circuit 13 and synchronization shift/
It consists of registers 14. The output of the receiving section 52 is descrambled by a circuit 53 and inputted to a vector circuit 54, which checks whether the code word is a code word according to the algebraic coding law as described above, and then outputs the result. It is stored in the scissors correction shift register 11 in FIG. The output H1lI4 of the vector circuit 54 in FIG. 9 is a code word error-corrected by the contents of the buffer register 17 in FIG. The transmitting/receiving circuit 65 buffers codes between the transmission system and the device, and is composed of the buffer register 17 shown in FIG. 4 and the clock circuit 16 that controls its contents.

The output of the transmit/receive@path 65 forms the information symbol portion of the transmission 7 frame transmitted to the lower station;
The frame is created by the division circuit 66◎ Division circuit 5
6 is the same as the configuration in Figure 1.j The division time M in Figure 11
The output from the transmitting/receiving μ path 56 is connected to the input terminal of the transmitting/receiving μ path 56, and information is transmitted by receiving the clock before the information symbol is transferred from the pitter circuit 16 in FIG.

That is, from the start/end transmission time wI3, the end code and the start code are also transferred to the output side of the make contact 2 of the switching circuit (c) in FIG. 1, and when it returns to the break contact 1, the next switching circuit The information symbol is transferred from the input terminal to the output side through the break contact 1 of , and is transmitted to the transmission path, and at the same time, registers r and ~"n- are set to -1 to perform the processing for creating the code west.・By receiving the clock for information timing termination from the clock circuit 16 in FIG.
1g circuit ←) is connected to make contact 2, and at the same time the cut point (
b) is turned off 11T, registers r0 to rn
A Chetsuta symbol is transmitted to change the code from -1 to -.

Terminal 1 connected to the loop network, that is, terminal 4 in FIG.
At 11.3 of the transmission frame, the timing of the own time slot is indicated from the clock circuit 16 of FIG. The information symbols of the terminal 43 in the second and third parts are the receiving registers 63, 64, 65 of the 9th wJ.
At the same time, the portion corresponding to this time slot in the transmitting/receiving circuit 6 is updated with the transmitted information symbol from the terminal 43. The transmitted information symbols of the terminal 43 are transferred from the transmitting registers 60, 61, 62 of FIG. 9 to the transmitting/receiving circuit 65 by the clock circuit 16 of FIG. 4. A set of transmitting registers and receiving registers 60 and 63, 61 and 64, and 62 and 66 respectively correspond to the terminals 4 of the first, second and third parts of the transmission frame.
Transfer is performed in the 3 slot.

When the loop network α is used as a local area network, other transmission channels connected to other transmission networks are connected to this local area network. 8, the terminal 42 is connected to four other transmission networks through 1.rho. D D X If! via the terminal 42 !
47, the node transmission function in the terminal 42 connects to the DDX network adapter. FIG. 10 is a diagram showing the connection state between the terminal in FIG. 6 and the DDX network.

The DOE70Fi shown in FIG. 10 is a terminator for the DDX network@line, and the DDX71 is an adapter having a logical interface function between the DDXm line and the local area network terminal. The input/output line to the adapter 71 is connected to the node transmission function circuit of the terminal 42, and the master clock fi5 shown in FIG.
0, send 1, and receive registers 60 to 50, respectively.

In this case, the receiving (U register 64) normally handles only call information, but if the receiving register 64 is used for other purposes in the private line network, the receiving register 64 connected to the adapter 71 handles the call information only. It is exciting to exchange information.In other words, since the DDX network does not handle electric vehicles,
The problem is the relationship between the second part and the reception register 6 that handles call information. When no external line is connected to the local area network, the terminal 42 in FIG. 8 operates with its own clock source and becomes a clock master station. When connecting a private line network to a digital communication line, for example, a DDX network line, it is not necessary to connect the private line network and the DDX line in an asynchronous manner. However, the private network needs to be synchronized to the DDX bag.

In FIG. 10, the timing/clock signal line of the DDX human output lines supplies a clock for synchronizing the local area network with the DDX line, and this signal Vi
It is used as a clock source in terminal 42, and roughly the other terminal stations 43, 44 synchronize their timing with terminal 42.

The transmission processing function of each node including the terminal 42 is shown in FIG. 9, but the details differ depending on the position of a certain node in terms of clock synchronization.

There are three types of clock synchronization methods in the transmission processing function of each node of the local area network: First, timing!
When connected to the clock main station on li'H in the form of a tree branch, the mask clock source 50 is
includes a voltage controlled oscillator, and the output line of the sample value data system 51 is connected to the voltage controlled oscillator II (in the master clock 50) rather than to the delay adjuster iD (in the 1 terminator 59). i! Take the crest. The second is a case in which a line is not connected from the outside at the clock main station on the timing connection, and therefore the mask clock [50 is independent, as shown in Figure 119]') DX network Neither the connection from sample value data system 51 nor the connection from sample value data system 51 to the voltage controlled oscillator is made. Just loop #? The most V of the continuation
The timing of receiving the transmission code from the node 44 is automatically set to 10.
In order to do this, signal processing is performed on the received baseband signal performed by the sample value data system 61, and the amount of delay in the delay circuit D (within the line terminator 69) is adjusted using the output of the extracted timing information. It is necessary to take such methods.

Next, the eighth case is a case where the clock main station is digitally connected to an external network on a timing connection.

Both of these include the mask clock il in FIG.
l! 50 is supplied with a clock from the DDX network, but the sample value data system 51 is not connected to the voltage controlled oscillator, but only to the delay circuit D (within the line terminator 59). Therefore, mask clock source 50
is a clock generator that operates with the clock from the DDX network. In the present invention, the first and third cases are utilized.

Note that the method of automatically adjusting the amount of delay in the delay circuit shown in FIG. 9 can be simplified when the number of connected links is small. That is, without connecting the sample value data system 51 of FIG. 9 to the delay circuit, the delay amount of the delay amount 'PJD can be fixedly set as A in advance.

In FIG. 8, when a loop-shaped line network is connected, the relationship between the line networks α and β is determined at the switching center 46. In this case, the flow of timing information from DDXm47 to α is transmitted by elements in a tree relationship consisting of each link of α, node Ol' (1m46) and each link of β.
Ru. First, the functions of node O in FIG. 8 will be described. In the transmission frame flowing through the transmission loop α, the slot stop given to the node connected to the loop C,
There is a field consisting of slots given to nodes connected on other transmission loops β coupled to node C.

FIG. 11 is a diagram showing the internal configuration of a connection point node of a line network.

The mask clock source 80, the sample value data system 701, the line terminator 87, and the receiver section 71 all have the same functions as those in FIG. 9, and the two output lines 1. 2 supplies operating clocks to the vector circuit 7δ, the transmitter/receiver circuit 76, the divider circuit 7'l, the vector circuit 72, the transmitter/receiver circuit 73, and the divider'h1 path 74, respectively. The 1 wave number ratio of these tarocks is abbreviated to the ratio of the number of bits in each transmission frame of the α and β loops.

In this case, the time lengths of both transmission frames are increased.

Receive register 81. , 62, 83 and the transmitting registers 84.8e'l, 86 are shared by the α loop and the β loop. 83 is the transmission register 60, 6 for the fS receiving circuit 55 in FIG.
1.63, the transmit register 84.
85.86 will have the role of receiving register 63°64.65. Although the transmission/reception circuits 76 and 73t-j have the buffer register 17 shown in FIG. 4, the number of bits is equal to the number of bits of the seven transmission frames of the β loop and α loop, respectively. The capacity of the transmitting/receiving circuit 76 is equal to the number of bits of the transmitting registers 84, 85, 85, and receiving registers 81.82, but the capacity of the transmitting/receiving η11 path 73 on the α loop side is equal to the number of bits of the transmitting registers 84, 85, 85, and receiving registers. The number of bits is considerably larger than the number of bits of registers 81, 82, and 83. In order to prevent the timings of transmission regarding the transmitting/receiving circuit 76 and transfer regarding the transmitting/receiving circuit 73 from coinciding, the operating phases of the multiphase clock circuits 16 (FIG. 4) provided in each are adjusted.

For this purpose, in the transmitting/receiving circuit 76 on the β loop side,
The reset line of the fourth multiphase clock circuit 16 is not connected from the output of the synchronization detection circuit 13, but from the transmitting/receiving circuit 7 on the α loop side.
3 to the specific phase output of the multiphase clock circuit 16.

In a loop-like network, tl is generally read by r terminals on the loop, but in the case of β loose in Fig. 8, node C
In addition, there are cases where only one terminal station is connected. This is a case where the two transmission links that connect the β loop +*t also serve as the same transmission line for transmitting in the upstream and downstream directions, and this bidirectional transmission line is connected to the dedicated #1'r1 channel line. It can be used to communicate with offices of the same company in different regions. At this office as well,
Similarly, if you have a loop network and connect it,
Similar to the connection of the α loop and β loop in Figure 11! !
! In this case, the clock of the network α loop of this business office will be synchronized by receiving timing information from the receiving side of the dedicated telephone line.

Figure 11112 shows the percentage performance at the end of the connection point between the dedicated telephone line and the loop network, and Figure 13 shows the system when two loop networks are connected via the dedicated telephone line. It is.

In the Cocoon 13 diagram, if node I is the connection point between β loop and α' loop, which are made up of dedicated telephone lines, then node E is
The transmission processing function is as shown in FIG. 12, and the function of the connection point C is as shown in FIG.

In FIG. 12, the mask clock source 89, the sample value data system 79, the same terminator 88, and the receiving section 78 are connected to the yoke 9.
Master tarotsuta source 60 and sample value data system 51 shown in the figure
, have functions corresponding to the same terminal device 59 and the receiving section 52, respectively.

The fleck synchronization relationship in each loop of α, β, and a is
There is a main station at α, and its timing information is relayed to the β loop at 7-doC, that is, to the summary value data thread 70 in FIG. 11, the master clock source 80, etc.
Synchronization is achieved with the signal terminal device 88, sample pulp data, and 1% 79. However, this function is performed by a modem and there is no need for automatic adjustment. The β-loop stack timing is relayed at node E in FIG. In other words, the α' loop is driven by the master timing function on the β loop side in FIG. and synchronization is achieved. It is possible to place a switching center in the α loop like in the α loop, and it is possible to use the Soviet Union's unique transmission frame Sakaki, but some slots of these 7 transmission frames are for the β loop. Even in the transmission frame in the loop, there is a slot on the β loop side. Regarding the use of these slots, the method will be clarified by conducting a W& run on how the exchange information should be and how it will be handled at the exchange.
For transmission of frame synchronization, node 01 in the Kasu 13 diagram
In other words, the line (A) in Figure 11 is the node in Figure 13 that establishes the phase relationship between INL, α loop and β loop frames at the reset m of the polyphase circuit 16 in #14, and the node in Figure 13. 11, that is, WaS> in Fig. 12 is β in the same way.
The phase relationship between the 7 frames of the loop and α loop is ttv wide.As described in detail, according to the present invention, two or more A-lines are connected at one point each, and the communication network is When carrying out wide-scale integration, it is possible to improve reliability by eliminating synchronization, minimizing the drop in transmission performance, and making corrections after experimenting.

[Brief explanation of the drawing]

Figure 1 shows the m calculation 1 mark V Island Rida in the transmission view, and Figure 2 shows the same frame used in the present invention. The block diagram of the a road, FIG. 3, is the l! road used in the present invention. ! Block diagram of correction circuit, Ayu 4
The figure is a block diagram of a self-correction circuit showing the practical example of the present invention.
Figure 8 is a diagram explaining the creation of the lily circuit, Figure 8 is a diagram of the loop transmission system to which the present invention is applied, Figure 9 is a block diagram of each terminal in Figure 8, and Figure 10 is the DDII! of Figure 8. The same interlocking state with #! Figure 11 is a block diagram of the transmission function at the terminal at the connection point between the line networks, Figure 12 is a block diagram of the transmission function at the terminal at the connection point between the dedicated telephone line and the loop network, and Figure 1s is the transmission function block diagram at the terminal at the connection point between the dedicated telephone line and the loop network. When we combine the two loop networks, we get the eclipse family tree. 32 start/end code sending circuit, 4. 8, 9 digit register, 5: detection times! , 6.16F multiphase tarlock generation circuit, 7.10, 12, 17: x7a register, 111
WI4 committee correction shift register, 13: synchronization detection ηd path, 14 shift register for two synchronizations, 15: reset movement, 21 to 36: registers forming shift registers, 42
~44+ terminal, 47 r DDX network, 50,80.89
:Ys#・RIO7 source, 51,70.79: Timing information detection circuit, 52.71.78: Receiving section, 53:
Destaramplinme circuit, 54, 72, 77; Hector circuit, δ5, 73. 768 hair receiving circuit, 56, 74, 75: division circuit, 57
Tomi Rumbling 11th Road, 58, 59, 87, 88;
Terminal V route, 40: Departure and arrival katana processing machine,! 1,46: Replacement scrap,
60-62.84-86: Transmission register, 63-65° 81-83: Reception register, 70: DDX line terminator,
71: Adapter. a tz: J 47 Figure 9

Claims (1)

[Claims] Two line networks each sharing a transmission frame of a predetermined length and forming a closed circuit with a plurality of transmission links are connected at one point, and each transmission frame series is synchronized at the one point. At the terminal station on each line network, the transmitting side manipulates information symbols according to algebraic laws to construct a transmission frame, and the receiving side registers a register that detects that the above algebraic laws are met. A synchronous network loop connection method characterized by setting the receiving side phase using the output and correcting errors in information symbols.