JPS5820033A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the consumption of power supply current in an assured way, by providing a means for supplying voltage higher than the gate voltage to the source of a control depression type MOS transistor in a power-down mode. CONSTITUTION:A control depression type MOS transistor TR11, a load TR12 and a driving enhancement EH type MOSTR13 are connected between power supply VC and the earth. At the same time, an EH type MOS controlling TR14 is connected in parallel with the TR13. Both the TR11 and TR14 receive gate control with a power-down signal-PD and a signal PD. The signals PD and -PD are set at 1 and 0 respectively in a power-down mode. Thus the TR14 conducts and voltage VSO is applied to the source of the TR12 from a voltage generating circuit 21, and the voltage VSO is set at a certain level that is decided by the ratio of the conduction resistance of TRs22-24 of the circuit 21. The threshold voltage of the TR12 is set larger than that of the TR11. Thus the VSO is supplied to the source of the TR11 via the TR12, and the gate of the TR11 is equivalently turned negative. Thus the TR11 is assuredly cut off to reduce current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor integrated circuit equipped with means for reducing power supply current consumption.

Semiconductor integrated circuits are equipped with J to reduce power supply current consumption.
: When a part of the circuit program in an integrated circuit is not used, it is often provided with a means for stopping the power supply to the circuit block to put it in an inoperable state. For example, in semiconductor memory.

When the memory chip is in a non-selected state, a power-down mode function is provided that puts the circuits in the chip in an inactive state to reduce power supply current consumption.

Such a power down mode feature! Conventionally, as shown in FIG. 1 (4), integrated circuits equipped with
MO8) Kunisters 11 to IJ are connected in series between vC and ground], and the load M08 transistor (for example, an N-channel depletion type M08 transistor)
An inverter is configured by an N-channel enhancement fiMO8) transistor (hereinafter referred to as a drive transistor) 11 and a drive MO8) transistor (hereinafter referred to as a drive transistor) 11, for example, an N-channel enhancement fiMO8) transistor. Collinearly connected output terminals. Therefore, the drive transistor 11
An input signal 1M is supplied to the gate of . Then, the power 11j Vc is supplied to the load transistor 12 via the N-channel depression type MO8) transistor Ilv, and this power supply control MO8) transistor (hereinafter referred to as a control transistor) 11 outputs a power down mode signal FD. gated by. This power down mode signal FD is an inverted signal of the signal FD and becomes "0" during power down, that is, when the inverter is put in a non-operating state to reduce power supply current consumption,
This signal becomes "1" when power down is released. Furthermore, a control transistor 14 is provided between the output terminal M- and ground in parallel with the main body transistor 11, and this control transistor 14 is gate-controlled by a power-down mode signal PD, for example, an N-channel enhancement transistor 11 MO8). ) is a transistor. This power down mode signal PD is.

This signal is rl J during power down and rOJ when power down is released. Further, a circuit consisting of M08 transistors 15 to 18 is provided similar to the circuit consisting of MO8) transistors 11 to 14, and this driving M0
8 transistors 11 are connected to the output terminal of the inverter,
gated by a signal from the cage. In addition, control M
08 transistors Is and III are connected to the signal P in the same manner as above.
Each gate is controlled by D and PD.

In such an integrated circuit C: the control transistor 11
is in a conductive state, the power supply VC is supplied to the load transistor 12, and the control transistor 14 is in a cut-off state, the inverted signal is output from the output terminal A, in accordance with the input signal a1.
occurs in

At this time, power down mode signals PD and PD are rlJ and rOJ, respectively. When this integrated circuit is put into a non-operating state to reduce power supply current consumption, the signals FD and FD become rOJ and rxJ, respectively, the control transistor 11v is brought into a state close to cut-off, and the control transistor 14 is turned on. state. In this way,
The supply of power Vc to the load transistor 12 is stopped, and the output terminal M. The signals generated in the control transistor 14 flow to ground through the control transistor 14.

At this time, that is, during power down, in order to completely stop the supply of power We to the load transistor 12, the threshold voltage Vsb1. It is necessary to set it to "Ov" or higher, but in that case, when power down is canceled,
That is, during operation of the integrated circuit, the transistor 11
．． 13, which occurs at the output terminals of the inverter consisting of
1'' level signal does not rise to the power supply voltage We, but only reaches the level of rVc-vth, lJ, resulting in a reduction in the power supply margin of the integrated circuit. Also, contrary to the above, in order to increase the level of the output signal to almost the superposition voltage v6 when the integrated circuit is operating,
Threshold voltage of control transistor 11 vtkttt' ro
V There are inconveniences that hinder reductions in consumption. Furthermore, the threshold voltage vth1. of the control transistor 11. If it is made negative, the drawbacks such as the decrease in the power supply margin mentioned above can be overcome.

The current flowing through the control transistor 11 during power-down (
The current between the source and the drain) is the control transistor 11
Because it sensitively responds to the threshold voltage VtbH of the transistor or the length of its channel, the current consumption during power-down is unstable, with large variations occurring. Therefore, in manufacturing the control transistor 11, great care is required in setting the threshold voltage vth or the channel length C2.

In addition, as shown in FIG. 1, the drive transistor I1. A method has also been proposed in which a control MO8) transistor 20 is provided between Ifl and the ground, and this control transistor 20 is gate-controlled by the power down mode signal FD. That is, in such an integrated circuit, when powering down, the signal F
When D becomes "0" and the control transistor 20 is cut off, the consumption of current can be reduced. However, in such a method, all circuit points rise to the "1" level during power-down, and when the power-down is released (PD becomes "1"), the charges are discharged, so the integrated circuit Due to the coupling capacitance between the substrate and the circuit point, the substrate potential is pushed down in the negative direction, causing the substrate potential to fluctuate, which adversely affects the operation of the integrated circuit. Further, when the power down is canceled, the drain voltage of the control transistor 20 takes time to change from "l" to "0" in response to the change of the signal FD from "0" to "l".

There is a drawback that the release speed of power down is slow due to the mirror feedback capacitance.

Furthermore, if it is the method shown in the above 'J11 cause.

It is sufficient to connect control transistors 11.14 to every other inverter (MOS) transistors 11.73 and 16.11 as shown in FIG.
In the method shown above, since the output of the inverter becomes "1" level during power down, it is necessary to connect all of the inverters. Furthermore, in order to keep the drain potential of the control transistor 2o close to the ground potential so as not to interfere with the operation of each inverter, it is necessary to set the driving capacity of the transistor 20 to be large, which has the disadvantage of increasing the chip area of the integrated circuit. arise.

This invention was made in view of the above-mentioned circumstances, and reduces the supply of power to the M08 transistor circuit constituting the logic circuit in response to a power-down mode signal, thereby ensuring a reduction in power supply current consumption. It is an object of the present invention to provide a semiconductor integrated circuit that can perform the following steps and obtain a sufficient power supply margin under normal circuit operating conditions.

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.

For an integrated circuit similar to that shown in Figure 1 of Volume 1 (4).

Power down mode signal FD is “1” during power down
The source C of the control transistor 14 becomes conductive when
: A voltage generation circuit 21 that supplies voltage Vao1 is provided. This voltage generating circuit 21 is composed of MO8 transistors 22 to 24 connected in series between the electrical conductors (between ve and ground).

In this MOS) transistor circuit, the gate and source of the MO & transistor 22 are commonly connected, and the power supply Vc
vMO8) is supplied to the transistor 23. The gate of this M08 transistor 2S is grounded or gate-controlled by the power down mode signal FD, and a voltage Vso is generated from its source. This transistor 2
The source of the M08 transistor 24 and the drain of the M08 transistor 24 are commonly connected, and the gate of the transistor 24 and the source of the transistor 22 are commonly connected, and the source is grounded.

In such an integrated circuit, if you temporarily put the circuit in a non-operating state and power it down.

Power down mode signals PD and PD shown in FIG. 2 are rOJ and rlJ, respectively. Therefore, the control transistor 14 becomes conductive, and the voltage VsO generated from the voltage generating circuit 21 is supplied to the output terminal AOs of the inverter, that is, the source of the load transistor 12 via the control transistor 14. At this time, this voltage VmO is.

In the voltage generation circuit 21, first, the voltage 111IN1 voltage Va
is supplied through M08 transistors zx, zz and 1M
The voltage rises until the 08) transistor 23 is cut off, and when this MOS) transistor 23 is cut off, the gate voltage of the M08 transistor 24 rises rapidly. Therefore, the MO8 transistor 24 is turned on, and the voltage VmO is applied to the transistor j! 2. ! It is maintained constant due to the conduction resistance ratio of 8.14. And this voltage VI
Q is connected to the control transistor 1 via the load transistor 12
1, the gate potential of the control transistor 11 to which the signal PD is supplied becomes negative equivalently to 1, and the threshold voltage Vth of the control transistor 11 becomes negative.
.

When is in a negative state, the control transistor 11 can be reliably cut off. That is, the M08 transistor 23 of the voltage generation circuit 21 has the same single value voltage Vt as the control transistor 11.
When the gate voltage is rOVJ, the voltage Vso generated at the source is approximately the same as the absolute value of the threshold voltage Vth, 1 vth, , l. Further, the transistor 24 is an enhancement type transistor having the same threshold voltage n' as, for example, the transistor 1s, and the transistor 22 is of the depletion type in this example, but may be a simple resistor, for example. Therefore, the voltage Vso supplied to the source of the control transistor 1
is always greater than its gate potential (signal PD), so
The gate potential becomes equivalently negative, and the voltage Vao changes and occurs according to the threshold voltage Vth, , of the control transistor 11, and the threshold voltage V th 1*
The settings are relatively flexible. In addition.

This voltage Vso is preferably equal to or lower than the single value voltage Vth of the drive transistor 17 of the next stage inverter shown in FIG. Then, when power down is released, that is, when the integrated circuit operates (signals PD and PD are rlJ and r
OJ) I: is the threshold voltage Vth of the wound transistor 1
Since 11 is negative, when the output signal of the inverter is at the rlJ level, the voltage is sufficiently outputted to 1 to the #l voltage Vc, and the power supply margin does not decrease. In addition, in the circuit comprising the primary stage inverter 1kIII in the above integrated circuit, that is, the circuit comprising the MOS transistors 15 to 18, the power down mode signals PD, PD
Since the configuration and operation are the same, their explanation will be omitted.

Note that in the voltage generation circuit 21, the transistor 22 is omitted, and the drain of the transistor 23 is connected to the power source Vc, the gate of the transistor 24 is connected to the drain of the transistor 24,
That is, it may be connected to the source of the transistor 21.

At this time, in the power down mode, the voltage Vso is output from the drain of the transistor 24, and its value is:

If the absolute value Jvth of the threshold voltage of the transistor 2S is smaller than the threshold voltage Vthffi of the transistor 24, the voltage VIO becomes l Vthem l, and the voltage VIO of the transistor 11. IB and 2J are cut off and the current consumption becomes O. On the other hand, even if 1Vth, , l is greater than vth, the voltage VIO will not become less than vth, 4, so the current consumption will be much smaller than in the conventional case. Further, the gate 12 of the transistor 23 of the voltage generating circuit 21 receives the signal P during power down.
A signal of a higher level than L) may be supplied. In that case, the level of voltage VsO also becomes high, and control transistor 11. The current flowing to No. 5 can be further cut.

FIG. 3 shows the driving transistor 11.
11 and control transistor 14゜1 #t'MO8)
This is the case where the transistor 31 is grounded. This M.O.
S) The transistor S1 is.

It is gate-controlled by the power down mode signal P'o, and is cut off during power down, that is, when the signal PD is "0", and the voltage v10 from the voltage generating circuit 2I is supplied to the control transistor 14.18. Also, when power down is released.

That is, when the signal PD is "1", the MOS transistor S1 is turned on, and the voltage VmO is held at the ground level. Even in such an integrated circuit, the same effects as in the above embodiment can be obtained. Note that the other configurations and circuit operations are the same as those in the embodiment shown in FIG.

Figure vI4 is for the embodiment shown in Figure 3 above.

Open/open transistor 14 gated by power down mode signal PD. This is the case when Iaf is omitted. In this case, the same effects as in the above embodiment can be obtained. In addition, when compared with the integrated circuit shown in FIG. 1(b), the control transistor 1 is
1.15, the supply of power supply VC can be completely stopped.

The potential at each circuit point hardly increases, and no potential fluctuation occurs on the substrate when power down is canceled. Note that other circuit configurations and operations are the same, so the same reference numerals are given and explanations are omitted.

FIGS. 5(A) and 5(B) show the voltage V in the above embodiment.
s.

This is another embodiment of the voltage generating circuit 21 that generates . First, as shown in FIG. 5 (6), MOI9) transistor 22
This is a case where the power source VC is supplied via a MOS Kunister 51, which is an N-channel enhancement type, for example, instead of being directly supplied to the drain of the MOS transistor 51. This MOS transistor 51 is gate-controlled by a power down mode signal PD, and when the signal PD becomes "0" when power down is released, the MOS transistor 51 is cut off.

Therefore, when the integrated circuit is in normal operation, consumption of the power supply current of the voltage generating circuit can be prevented.

Furthermore, as shown in FIG. also has the same effect as above. That is, the MOS transistor 52 is gate-controlled by the power-down mode signal FD, and the signal PD becomes "0" when power-down is released.
'', the MOS transistor 51 is cut off. Furthermore, even if the potential of the signal PD rises due to the gate control of the transistor 23 in FIG. The potential of can be increased accordingly. Of course, the gate of the transistor 23 of the voltage generating circuit 21 in FIG. 2 may also be the signal PD. Therefore, the control transistor 11 of the integrated circuit is reliably cut off even if the potential of the gate signal PD rises during power down. In addition.

The other circuit configurations and operations are the same as those in the above embodiment, so their explanation will be omitted.

FIG. 6 shows an example of a circuit in which the present invention is applied to a normal buffer circuit 61. That is, this is the case where a buffer circuit II is added to the integrated circuit shown in FIG. 2 (voltage generation circuit 21 is omitted).

This buffer circuit 61 is between 118 (between Vc and ground)
The load and control M08 transistor 113 and the drive transistor 63 are connected in series, and this MOS) transistor 1.611 is connected to the output terminals A, , M, and the inverter.
are respectively gate-controlled by the output signal C2 of. Furthermore, a voltage Vso (generated from a voltage generation circuit not shown) is supplied to the output terminal Muden, which is a common *reading point of this MO8 transistor 61. 64 is
It is, for example, an N-channel enhancement type Moa) transistor gated by a power down mode signal PD.

Even in an integrated circuit to which such a buffer circuit lJ is added, as in the Uami embodiment, during power down I: signal F
When D is "1", the control transistor 64 becomes conductive, and the voltage v10 is supplied to the output terminal M. Therefore, the source potential of the transistor 2 increases; therefore, the MOS transistor 52 having a negative threshold voltage can be brought into a state close to cutoff, and the consumption of the power supply VC can be reduced. Also.

When power down is released, signal PD is "0".

Control transistor 64 is cut off and buffer circuit 61 operates normally.

71g (A) and (B) are the voltages supplied to the output terminal M8 of the -buffer circuit 61 through the M08 transistor 641 during power down in the integrated circuit to which the buffer circuit 61 shown in FIG. 6 is added. A voltage generation circuit 11 of VsO is shown. That is, as shown in FIG. 7, the gate of the M08 transistor 2# of the voltage generating circuit 21 is controlled by the gate signal of the buffer circuit 610 and the M08 transistor 62. With such a circuit, it is possible to generate a voltage VIO corresponding to the gate potential of transistor 2 (1M08).

During power-down, even if the gate potential of MO8) Ranjis 1 Talo 2 is relatively high, MO8) Ranjis ε2v
You can definitely cut it off. Also.

vs7 diagram (as shown in Tsukasa, M08 of the voltage generation circuit 21
The buffer circuit 6 is connected to the gate of the transistor 23.
This is the case when the source voltage of MO8) transistor 21 having the same negative threshold voltage as MO8) transistor 2 is supplied. The drain of this MO8) transistor 1 is supplied with the power supply VC, and the gate is grounded. Furthermore, its source is grounded via MO8) Langstaff 2t/or directly. The voltage generating circuit 21 can reliably generate the voltage Vaoy determined by the sum of the absolute value of the threshold voltage of the resistor 2 (MO8 of the buffer circuit) and its gate voltage, and this voltage VsO can be generated as the voltage VsO at the time of power down. By supplying it to the source of the transistor 62, the transistor 2 (1M08) can be reliably cut off.

FIG. 8 shows another circuit example of the voltage generating circuit that generates the voltage vso in the above embodiment. That is, this voltage generating circuit 1 has the same negative threshold voltage as, for example, the control transistor 11 of the integrated circuit shown in FIG.
A power supply Vc is supplied to the drain of the MO8) transistor 81, and its gate is grounded or controlled by a power down mode signal PD. Further, the source of this M08) transistor 81 is grounded via the MO8) transistor 82, and a voltage VR corresponding to the threshold voltage is generated at the source. And this voltage VB is 1M08) transistors 83 to 11
The signal is supplied to one input 1 of a known differential amplifier circuit 87 consisting of 6.1111. The other input terminal of this differential amplifier circuit 81 has a value of 1, for example, l! It is connected to the source of the control transistor 14 shown in FIG. 2, and is supplied with voltage Vso. Further, a transistor 89 is provided between the differential amplifier circuit 81 and the ground, and the gate of the MO8 transistor 89 is controlled by a power down mode signal PD.

A differential amplifier circuit 9o similar to this differential amplifier circuit 181 is provided, and one input terminal of which amplifier circuit 90 is supplied with the output signal B of one of the amplifier circuits 81, and the output signal B of the other amplifier circuit 90 is supplied with the output signal B of the amplifier circuit 81. The other output signal B of the amplifier circuit 87 is supplied to the input terminal. Furthermore, the output signal B of this amplifier circuit 90 is supplied to the gate g of a MO8 transistor 91, and the drain of this M08 transistor 91 is connected to the other input terminal of the amplifier circuit 81, and its source is grounded. Ru.

In such a voltage generation circuit, now the provisional C2I second
When the integrated circuit shown in the figure is powered down.

That is, the signals FD and FD are each "0".

rlJ, even though the signal FD in the control transistor 11 is "0", if the source potential, that is, the voltage VmO is higher than the voltage Vλ due to leakage current, etc., first, the amplifier circuit 8 full output signal BleBl are rlJ level and "0" level, respectively. Therefore, the output signal B of the amplifier circuit 9o becomes "1" level.

MO8) The transistor 91 has a low resistance, and the voltage VmO is lowered by the current path formed between the transistor 91 and the ground. Conversely, when the voltage VsO is lower than the voltage VR, the output signal BleBl of the amplifier circuit 81°
are at the "0" level and "1" level, respectively. Therefore, the output signal B. of the amplifier circuit 90 becomes "0" level.

The M08 transistor 91 has a high resistance, and the voltage VsO increases. That is, according to this voltage generating circuit, for example, in the integrated circuit shown in FIG.
The control transistor 11 and the like can be reliably cut off during power down. Note that the differential amplifier circuit 82°90 is as follows:
Operating in response to the power down mode signal PD is as follows:
Of course.

In the above embodiment, C: voltage V at power down
s Ot' s load MO8)? It is supplied to the source of y9X and 12°16, but this C: Control M without limitation
O8 transistor 11. Direct voltage V s to the source of is
o may be supplied. Also.

Power down mode signal PD during power down.

Instead of PD being rlJ and rOJ, respectively.

The signals rOJ and rlJ may be inverted, respectively. However, in that case, the control transistor 11゜is, xx, a
x, yx are P channel depressions V with positive threshold voltages
:iyfiMO8) transistors and control transistors J 4 and I Jt.

51.52.64 P Channel Enhancement)fiM
O8) It is necessary to use a transistor.

As described in detail above, according to the present invention, the supply of power to the M08 transistor circuit constituting the logic circuit VW is controlled in accordance with the power down mode signal, and
ll1MO8) A semiconductor integrated circuit that can reliably reduce power supply current consumption during power-down by stabilizing the operation of the control MO8) transistor, which is a transistor, and that can also provide a sufficient power supply margin under normal circuit operating conditions. can be provided.

[Brief explanation of the drawing]

Figure 1 ~ (q is a configuration diagram of a conventional semiconductor integrated circuit, Figure 2
FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to an embodiment of the invention, FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to another embodiment of the invention, and FIG. 4 is a configuration diagram of a semiconductor integrated circuit according to another embodiment of the invention. A configuration diagram of such a semiconductor integrated circuit, @5 (6), the top is a configuration diagram illustrating another embodiment of the voltage generation circuit according to the semiconductor integrated circuit of the present invention, and FIG. 6 is a diagram of the semiconductor integrated circuit according to the present invention. Figure 7 shows the instantaneous diagram when a buffer circuit is added to the
(C: is a circuit diagram explaining another embodiment of the semiconductor integrated circuit according to the above-mentioned FIG. 6, and FIG. 8 is a circuit diagram explaining another embodiment of the voltage generating circuit according to the semiconductor integrated circuit of the present invention. 11~at1go, zz~24.11.51°Si, 6
2-64. "j/1.f12.81~at. IIl, 89.91...M2S) transistor, 81゜90...differential amplifier circuit. Representative valve 3!! Saturday Takehiko Suzue 12 Jun Yu. -〇Figure 3 Figure 4 Figure 5ryJ (A) CB) Figure 6 section

Claims (1)

[Claims] (1) Gated by a first input signal. Depressor type MO8) Control IMO which is a transistor
8) A transistor, a drive M08 transistor which is supplied with power directly or through a load circuit from this control MO8 transistor and gated by a second input signal, and a drive M08 transistor which is gate-controlled by a second input signal, and which is connected to the side i[1MO5) transistor during power down. 1. A semiconductor integrated circuit comprising means for supplying a source with a voltage at least higher than its gate voltage. The above load circuit is a depletion IJiMos transistor, and the absolute value of this threshold voltage is on the above side 11.
M08) The semiconductor integrated circuit according to claim I11e, which is larger than the absolute value of the threshold voltage of the transistor.