JPS5820026A - Oscillating circuit - Google Patents

Abstract

PURPOSE:To produce a pulse signal having a frequency stable to the fluctuation of power supply voltage, by using a comparator which controls the change of voltage produced in accordance with the time constant of a CR circuit and then compares the changing voltage with the reference voltage. CONSTITUTION:Divided voltage Va which is produced in accordance with the ratio between resistances R1 and R2 of series connection and an output signal phi of a comparator 61 is supplied to an input of the circuit 61. The reference voltage Vb is supplied to the other input terminal of the comparator 61. Voltage Vb is equal to the divided voltage which is produced in accordance with the ratio between resistances R3 and R4 of series connection that from a reference voltage producing circuit to be provided between power supplies VDD and VSS. Then the signal phi is supplied to the gate of a transfer gate circuit Trp form an output terminal of the comparator 61. The voltege Vi produced at the terminal of a CR circuit 11 is controlled by the power supply voltage VDD. In such a way, a pulse signal having a frequency stable to the fluctuation of the power supply voltage can be produced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit with improved 411K oscillation frequency characteristics.

Pulse generation circuits are used as circuit operation sources for electronic devices, etc.
Various circuits have been proposed for the pulse generation circuit, which is one of the most important circuits in electronic circuits, but the circuit has many advantages such as a simple configuration and a high capacity. CB oscillation circuits are often used. This CB oscillation circuit (hereinafter simply referred to as an oscillation circuit) is a circuit that generates a pulse with a frequency corresponding to the time constant of the C/4 capacitor and the resistor. Conventionally, an oscillation circuit like the one shown in FIG.
) circuit), which is provided with a power supply voltage via a transfer r-) circuit terw, and a current/transducer Cx and a resistor BxO in parallel with a parallel C1 transfer circuit. I having a predetermined frequency with respect to the voltage Vi generated according to the time constant of the capacitor Cx and the resistor lxO of 1.
4 Lus v. The system that generates llt. construction circuit 1j
is provided, and the drus v*mt is supplied to the transfer 1'-root circuit TrN (Dl''-).In addition, when a normal oscillation circuit is integrated into an IC, the Ic internal fJK In this case, CRIIIrl is externally connected to one pin.In such an oscillation circuit, the voltage v4 is Vsg (hereinafter referred to as r).
OJ level), then S. The output voltage veat of the r-t circuit 12 becomes a "1" level lower than VDDC, and the transfer dirt circuits te and N are turned on, that is, are in a conductive state. Therefore, the power supply voltage VDD is supplied to the C1 circuit 11, and the voltage V( rises to the "1" level. The rise time of the voltage v4 at this time is determined by the on-resistance of the transistor Tr) and the time constant Kftft of the capacitor Cx The voltage V (shuts down in the process of rising)? -) At the moment when the high level threshold voltage V1m of the circuit 12 is exceeded, the r-) circuit 12 is inverted and the output voltage V,,i changes from rlJ level to r
When changing to the OJ level, the load capacitance of the terminal where the voltage V (normally occurs) is larger than the load capacitance of the terminal where the voltage Vent occurs, and the fall of the voltage VEAT is the rise of the voltage V4. bK is instantaneous compared to the voltage v,,, ( r O J level) transferred by K f-) circuit? ,)f becomes non-conductive, the voltage v4 stops rising, and starts to fall according to the time constant of C8 of the C1 circuit 11. The low level threshold voltage V of the root circuit 11! -The moment the song goes down, shi. (r-) circuit 12 is inverted and the output voltage v. 11t changes from rOJ level to "1" level. Voltage v at this time
The rising edge of eat is also instantaneous, as is the falling edge. If this operation is repeated, the oscillation Δ of a predetermined frequency will occur due to k.
◎Figure 1 (II) shows the sheet ty
)? -) 11 paths 14 are in positive phase operation, that is, Fig. 1 (A)
It is an oscillation path that generates the pulses generated from the sh*t dart circuit 12 shown in K, thus, the transfer r-) circuit! 1 consists of a P-channel M (Ml) transistor, etc. The other configurations and operations are the same as those of the oscillation circuit shown in FIG.

Therefore, such an oscillation circuit is specifically as shown in Figure 2. The circuit configuration is □, that is, the IC internal
1 is shi J&? -) Substitute bK of circuit 11 or 14
A plurality of input terminals III to 14 are connected in series between the input terminal of the first stage input terminal 21 and the terminal for generating the voltage v1 of the C1 circuit 11. A resistor R1 is provided. Furthermore, the input terminal of Invar 111 and the
A resistor R is provided between the output terminals of f-J j #, and a divided voltage V. is supplied to the input terminal of the first-stage inverter 21.

And the signal φ generated from the output terminal of IN”-fill
is a P-channel MD that supplies power VDD to the C1 circuit 11.
8) Transfer circuit consisting of registers, etc.
supplied to the market.

In an oscillator circuit like this, the voltage v4 now begins to decrease, and the output signal of the input/diameter J1ezz becomes
When the level is set to 0 and 1, the voltage V (is 3
As shown in the figure, at the moment when the voltage drops to the low level threshold voltage VZLt, the in/voltage-! 21 and 11 are inverted. At this time, the voltage VtX is as follows, where R1, R-...Resistor 11. Each resistance value Vth1 of blade 3=
47 I? -7j I Ojl value voltage. Therefore, the output signal φ of the inverter III is at "O" level 1b, and the output signal v*u of the output stage in/f-14 is
t instantly changes from the "1" level to the rOJ level, and the transfer r-t circuit terp becomes conductive.・This transfer? −)
The power supply VDD is supplied to the C-rich circuit 11 by the circuit 〒, , and the voltage v4 starts to rise.・This voltage V(is the third
As shown in the figure, at the moment when the high-level threshold voltage "IHl" is raised, the inverter z
→ Change from level to "1" ・Voltage v at this time
xx becomes. Therefore, the IN-1140 output signal vout of the output stage instantly changes from the rOJ level to the "1" level and transfers? −) Circuit! 1. becomes non-conductive. This transfer dirt circuit Te1. As a result, the supply of power FEVDD to the OR circuit 11 is stopped, and the voltage v4 begins to decrease. I parables ve as shown in
at is generated. By the way, /4rus V, at('
Period T, that is, period T1 and period ? shown in diagram sI3? .

When calculating, first, the voltage v4 is the low-level value voltage VILt
When the output signal φ*vout of the inverters lxz and x4 becomes "0" level (Was), the signal II (rob
) is supplied to the transfer r-) circuit 'r, , or-, and the r-) circuit 〒1 becomes conductive, and the voltage V< starts to rise. An equivalent circuit as shown in (II) is established.

In other words, in 4-111 (D, the switch corresponding to the inversion operation is turned on, and the transfer gate circuit Tr, (if the D on resistance is the resistor R, the current "(1 + leakage") is generated according to the power supply voltage VDD. is connected to the Cn circuit 111Dd through the resistor.
Pya parable Cx, resistance l! and resistance R1, R-
・Voltage VDD at this time ・Current r (s +4
*The JO relational expression is as follows. That is, VDD-(is(')+(s(t))・Rs
10c, / (t (t), dt+ Vll= (4
* (t)+ is (t)) ・-+R/(fable(
1) ・・・・・・・・・・・・(3) However, ・In this case, the initial value is ・Therefore, the above formula (a), (4),
(s) e (a) Yo and ζ here. , furthermore, the voltage V1m is Vxx -17'<1(?t) ・
...Since it is one song (9) - from the above formula (η, (8), the period Tt becomes ・Next, the voltage V (is the high level threshold voltage V! after the period TI! It rises like an irises, In Blue-112,11
4 output signals φ and vout are at rlJ level (vDD)
If K is reached, the signal - (rl) as shown in Figure 5 (A)
J) is supplied to r-)g of the transfer r-) circuit Trp, and the r-) circuit Trp becomes non-conductive and the voltage V( starts to decrease. In other words, the switch cap is turned on and the current r 4.s + (a J
is connected through the resistor Rt −1s to the L”ClCRII circuit 110
The current is shunted to each of the resistors and carriers CX. At this time, the current (l goes to the resistor R1, and the current (4 goes to the resistor R1),
If it flows to the converter C8, the voltage VDD and the current r
(s + 4a The JO relational expression is as follows. That is, VDD-((s(t)+ (a(t))・(Rt +N
a)+4. (s)-hx・H4s (t)・% =
c, / 4 *Ct) as --------
=-94. At this time, the initial value is ・Therefore, the above formula (II, (2), (b))
, a◆(s(t) becomes kai, which is totode・Furthermore, 1 electric EEVIL is VIL I! Rx−(嘗(!鵞)・−・・・・・・・・・・
(b) Therefore, from the above equations (2) and (b), the period 〒S
Hato becomes. Therefore, from the above formula (conversion) and (2), the pulse V, wtC' period T is obtained, and the frequency I is thus obtained.In this way, the frequency I of I4 pulse is equal to the power supply voltage V
DD I voltage Vll I VIL depends on this voltage V! The seal IVIL is the above formula (1), C2"
), it depends on the threshold voltage Vtkl of the inverter 111. Therefore, if the voltage vtht has a proportional relationship to the voltage VHO, the frequency f depends on the power supply voltage V
It becomes a constant value regardless of DD. However, the threshold voltage Vtkl of the inverter 21 does not actually have a proportional relationship to the change in the voltage vDD because the on-resistance of the P-channel or N-channel MO8 transistor that constitutes the inverter changes depending on the voltage VDD. . Therefore, the voltage Vll = VIL is also proportional to the voltage Vl) I) O change, and in the conventional oscillation circuit, the Ill sous frequency f generated from it is equal to the power supply voltage Vl) 1)
The invention was made in view of the above circumstances, and it is possible to eliminate the influence of changes in the power supply voltage, thereby achieving stable frequency reduction characteristics. An object of the present invention is to provide an oscillation circuit that generates pulses having the following characteristics.

An embodiment of the present invention will be described below with reference to the drawings.No. 6 Ill shows the configuration of an oscillation circuit according to the embodiment. First, the oscillation circuit shown in FIG.
For example, a composition ratio soft circuit 61 consisting of an operational amplifier circuit is provided in place of the main 21.
Tryyxp'@*m, N, ta'41111111
5s-108769, one input terminal (+) K is connected to the ratio of the series-connected resistor R1s and the output signal φ of the operational amplifier circuit 61.
A divided voltage V, which is generated according to the voltage, is supplied. Furthermore, the other input terminal (“-” side) has VDD-V between power supplies,
For example, the reference voltage generation circuit provided in , is composed of series-connected resistors R, , R, and a reference voltage vb, which is a divided voltage generated according to each resistance ratio, is supplied.And this operational amplification From the output terminal of circuit σ1 to the above P channel MO
8) Runjis! transfer r-to bribe T□ r-)
A signal φ is supplied to. Note that the other configurations are completely similar to the oscillation circuit shown in FIG. 2 above, so the same reference numerals are given and description thereof will be omitted.

In such an oscillation circuit, if the voltage V (starts to decrease), the input voltage V on the positive (r+J') side of the operational amplifier circuit 110 starts to decrease. Low level threshold voltage V of prefectural circuit 51
When IL drops at 1, the output signal φ becomes rOJ level.In other words, the circuit operation as shown in FIGS. 4(M) and 4(B) above is 1-! , transfer r-) circuit te,,0
A signal (rob) is supplied to r-), and the I circuit Tr becomes conductive. Therefore, the CB circuit ttl
c The power supply VDD is supplied, and the voltage V( starts to rise. At this time, the low level threshold voltage VIL is K11 as shown below.
It will be 21m. In other words, it becomes.Furthermore, when the voltage v4, that is, the voltage V, rises at the high level threshold voltage V1M of the operational amplifier circuit #l,
The force signal - changes to the "1" level, i.e.
The circuit operations shown in FIGS. S (A) and (B) above are performed, and the signal φ(rl
J) is supplied and this? -) Circuit 11. becomes non-conductive. Therefore, the power supply 'DD to the C1 circuit 11 is stopped, and the voltage v4 begins to decrease. At this time, the high-level threshold voltage WIN is expressed as follows.

In other words, ゛. If such a circuit operation is repeated, the curves shown in FIG.
- is generated from the output stage inverter j4. by the way,
At this time, if we calculate the period T1 (08 period T1, that is, the period 〒1, !, shown in Figure 3), it will be expressed as follows.In other words, from the above formula (transformation), Sakaki...・・・・・・・・・・・・・・・(2) becomes,
Therefore, the period T1yT1 is T, and the engineering is 1ψT1 Axle load...-'f
, x= x, −7, −axis, , , −Zeng and Table 3j
l@re, K1, and ni are constants, and Lm is the above formula (c), (
From 2), the frequency f of Δrus v, ut becomes ・Thus, from the above equation (b), the threshold voltage VIL t vx
l is proportional to the power supply voltage VDD, and the above formula (
2e) The frequency f is a constant independent of the power supply voltage VDD and is stable against fluctuations in the power supply voltage VDD. Figure 7 shows the P channel M of the oscillation circuit shown in Figure 6 above.
OII) Transfer r-) circuit consisting of transistors r90
Instead, a transfer dirt circuit consisting of an N-channel MO8) is provided, and a voltage v1 is supplied to the input terminal on the negative (,r-J) side of the operational amplifier circuit alt), and the voltage v1 is supplied to the input terminal on the positive (r+J'') side. This is an oscillation circuit configured such that the voltage vb is supplied to the input terminal.In other words, this oscillation (B) path is a circuit with anti-phase operation compared to the oscillation circuit with normal phase operation shown in Fig. 6 above. Yes, the operational amplifier circuit glcJ output signal 1 generated in response to a change in the voltage V4O, and the output signal layer of the input If-me 24 are inverted signals of the signals -1 and lt. Since it is the same as the oscillation circuit shown in Fig. 6, the same reference numeral is given and the explanation is omitted. Fig. 8 shows the oscillation circuit shown in Fig. 6 above with an oscillation/oscillation stop function. This figure shows the configuration of the added oscillation circuit.In the reference voltage generating circuit that generates the reference voltage Vb supplied to the negative Cr-J> side input terminal of the operational amplifier circuit 17, a resistor is connected between the power supplies VDD and Vll. .

Connected in series with R4 is a transfer r-) circuit T□ consisting of nine N-channel MOs) Tunisters.

This transfer dirt circuit (r- in 〒1) has an oscillation stop signal -
is supplied via the imper 1111. Also, this signal g is supplied to one input terminal of the Noah r-) circuit #1, and the output signal φ of the operational amplifier circuit 61 is supplied to the other input terminal. The output signal of the NOR gate circuit 82 is connected to the power supply V to the C1 circuit 11 via the input Δ-aSS.
The transfer r-) which controls the DD supply is supplied to the gate of the path Tr. Note that the other configurations are the same as the oscillation circuit shown in FIG.
When the voltage decreases to the low-level threshold voltage vtLt shown in 2), the output signal φ of the operational amplifier circuit #l becomes the rOJ level in the same way as above, and this signal φ(rob) is transmitted to the nor-dart circuit aj
#4: Transfer r-) circuit τrpOr via /A-113
−). Therefore, the transfer r-) circuit Trp
becomes conductive, the cm circuit 1111C power supply VDD is supplied, and the voltage v4 begins to rise. When this voltage V( increases to the high level threshold voltage Vllt shown in the above equation 4, the output signal φ of the operational amplifier circuit 61 changes from the “0” level to the “1” level, and this signal φ(rlJ) -)-Route 82. The transfer r-) is supplied to the r-t of the circuit Tr, through the inverter #1. Therefore, the transfer r-, the r-t of the circuit T
O is in a non-conducting state, the power supply VDD to the C8 circuit 11 is stopped, and the voltage v4 begins to decrease.
One rus ve+at occurs from 4.

At Hiro, the oscillation stop signal 1 (rlJ level) is transferred to the oscillation circuit that performs the oscillation operation through the Nordart circuit ax,in/''-Ill.
is supplied to the r-t circuit T□ and becomes non-conductive.
Therefore, regardless of the output signal φ of the operational amplifier circuit 61, the supply of one source VDD to the 1CR circuit 11 is stopped, and the voltage V( is decreased. At the same time, the oscillation stop signal 1 is
The output signal (“0” level) of this input/controller 81 is transferred to the input terminal of circuit T
- and the r-t circuit Tr)i becomes non-conductive. Therefore, generation of the reference voltage vb is stopped,
Unnecessary power consumption can be prevented. Note that when the oscillation circuit is operating normally, that is, when the oscillation is in progress, the oscillation stop signal 1 is at the rOJ level. In the above embodiment, the comparison circuit is not an operational amplifier circuit, but has a comparison function such as a differential amplifier circuit. As long as it has a circuit, it suffices.

As detailed above, this release! According to IK, the change in voltage generated according to the time constant of the 01 circuit is controlled, and HiO1! By providing a comparator circuit that generates a noise signal according to the comparison result between the changing voltage and the reference voltage, it is possible to generate a noise signal with a stable frequency against fluctuations in the power supply voltage. By providing a means for stopping the generation of the reference voltage when stopped, it is possible to provide an oscillation circuit that can prevent unnecessary power consumption.

[Brief explanation of the drawing]

Figure 1 (1) is a schematic configuration diagram of a conventional oscillation circuit, and Figure 2 is a specific configuration diagram of a conventional oscillation circuit.
The figure is a diagram showing the 14th chart, Figure 4 (m).
, (1) and Figure 5 (mu''), (B) are diagrams explaining the operation of a conventional oscillation circuit, Figure 6 is a configuration diagram of an oscillation circuit according to an embodiment of the present invention, and Figure 7 is a diagram explaining the operation of a conventional oscillation circuit. A block diagram of an oscillation circuit according to another embodiment of the invention, FIG. 8 is a block diagram of an oscillation circuit according to still another embodiment of the invention. y) l'
-) ml tract, 21~j 4, a J, a J
-・Imperature, -1・-Comparison--qf and Noah r-
),! 12. 〒M transfer r-) circuit, cx-...car/transfer, R, IB1-B4, R. ···resistance. Applicant's agent Patent attorney Suzu Jiang Wu
Pumpkin 5!5 Figure 4 (A) Figure 5 (A) (B) (B)

Claims (2)

[Claims] (1) A 01 circuit consisting of a capacitor and a resistor connected in parallel, a power transfer r-) circuit connected in series with the 01 circuit between the power supplies, and a first resistor at the connection point between this dirt circuit and the 01 circuit. a comparator circuit having a first input terminal connected thereto and having a twentieth input terminal and an output terminal; and a second resistor connected between the first input terminal and the output terminal of the comparator circuit. and a reference voltage generation circuit connected to the power supply, and the reference voltage from the reference voltage generation circuit connected to the second power supply.
The above-mentioned transfer is carried out by the means for supplying the input terminal of ? and the output signal from the output terminal of the above-mentioned comparison circuit. -) means for controlling r-) of the circuit. (2) C8 made by connecting Imaya/Manashi I and a resistor in parallel
circuit, a power transfer f-) circuit of stripe 1 connected in series with the above 01 circuit between the power supplies, and 1. ←, the first r−) circuit and 0
A comparison circuit having a first input terminal connected to a connection point of one circuit via a first resistor and having a second input terminal and an output terminal, and a first input terminal and an output of the comparison circuit. a reference voltage generation circuit having a second resistor connected between the terminals, a resistive voltage divider and a second power transfer r-) circuit connected in series between the power supplies; -) means for supplying a reference voltage divided from the resistor voltage divider - to the second input terminal according to r-) control of the circuit; and ff-) of the second power transfer r-) circuit. a first transfer means for controlling and transferring an oscillation stop signal; and a first transfer means for transmitting the oscillation stop signal and at least one of the output signal from the output terminal of the comparison circuit to the first power transfer ff-) circuit. ff-)
An oscillation circuit comprising: second transfer means for performing K transfer.