JPS58197773A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPS58197773A JPS58197773A JP8036582A JP8036582A JPS58197773A JP S58197773 A JPS58197773 A JP S58197773A JP 8036582 A JP8036582 A JP 8036582A JP 8036582 A JP8036582 A JP 8036582A JP S58197773 A JPS58197773 A JP S58197773A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor device
- type semiconductor
- substrate
- mos type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000010354 integration Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 8
- 238000009413 insulation Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はＭＯ８臘半導体装置の構造に関する。[Detailed description of the invention] The present invention relates to the structure of an MO8 semiconductor device.
従来、ＭＯＢｆＪ半導体装置は、第１図に示すごとく、
ｌｉ半導体基板１の表面にソース拡歇ＩＩ城２、ドレイ
ン拡散領域５が形成され、周辺フィールド絶縁ｊＩ４と
前記拡散領域３．４にはさまれて、ゲート絶縁膜５とそ
の上に形成されたゲート電極金属６が平担に形成されて
成る。Conventionally, MOBfJ semiconductor devices, as shown in Figure 1,
A source expansion region 2 and a drain diffusion region 5 are formed on the surface of the li semiconductor substrate 1, sandwiched between a peripheral field insulation layer 4 and the diffusion region 3.4, and a gate insulation film 5 formed thereon. Gate electrode metal 6 is formed flat.
しかし、上記従来技術では、チャネル長が平面寸法で定
められるため、例えば長いチャネル長を有するＭｏ８
７ｍＣＴｔ−構成する場合には、大面積を要するとい
う欠点がある。However, in the above conventional technology, since the channel length is determined by the planar dimension, for example, Mo8 having a long channel length
The 7mCTt configuration has the disadvantage of requiring a large area.
本発明は上記従来技術の欠点をなくし、長いチャネル長
のＭａｓ ｙｘＴ＠成時にも小さな占有面積ですみ、
高集積化に適したＭＯＢ型半導体装置榔造を提供するこ
とを目的とする。The present invention eliminates the drawbacks of the prior art described above, occupies a small area even when forming Mas yxT@ with a long channel length, and
It is an object of the present invention to provide a MOB type semiconductor device structure suitable for high integration.
上記目的を達成するための本発明の基本的な構成は、Ｍ
ｏｓｇ牛導体装置において、半導体基板表面は凹凸状に
加工され、該凹凸状半導体表面の凸部の少なくとも一面
にはゲート絶縁膜とゲート電極とが形成されて成る事を
特徴とする。The basic configuration of the present invention to achieve the above object is as follows:
The OSG conductor device is characterized in that the surface of the semiconductor substrate is processed into an uneven shape, and a gate insulating film and a gate electrode are formed on at least one surface of the convex portion of the uneven semiconductor surface.
以下、実施例により本発明を詳述する。Hereinafter, the present invention will be explained in detail with reference to Examples.
＃Ｉ２図は本発明によるＭＯＳ型半導体装置の一実施例
を示す、８１基板１１の表面に形成された凸部１２の表
面にはゲート酸化膜１３，ゲート電極１４が形成され、
ｓ１基板の凹部の表面にはソース拡散領域１５とドレイ
ン拡散領域１６およびフィールド絶縁膜１７が形成され
てなる。#I2 shows an embodiment of a MOS type semiconductor device according to the present invention.A gate oxide film 13 and a gate electrode 14 are formed on the surface of a convex portion 12 formed on the surface of an 81 substrate 11.
A source diffusion region 15, a drain diffusion region 16, and a field insulating film 17 are formed on the surface of the concave portion of the s1 substrate.
縞５図は本発明によるＭｏ８１１［半導体装置の他の実
施例を示す。８１基＆２１の表面に形成された凸部の両
側面に各★ゲート酸化膜２５，２５’、ゲート電極２４
．２４’が形成され、ｓ１基板凹部表面にはソース拡散
領域２５と、ドレイン拡散領域２６．２６’およびフィ
ールド酸化＠２７が形成してなる。Stripe diagram 5 shows another embodiment of the Mo811 semiconductor device according to the present invention. Gate oxide films 25, 25' and gate electrodes 24 are formed on both sides of the convex portions formed on the surfaces of 81 and 21.
．． A source diffusion region 25, a drain diffusion region 26, 26' and a field oxide @27 are formed on the surface of the s1 substrate recess.
上記の実施例の如く、半導体基板表面の凸部の少なくと
も図面をゲート領域としたＭＯＳ型半導体装置に於ては
、ゲート長を長く要するＭＯＳ）ランジスタに於ても、
ゲート部は大面積を焚せず高集積化に向いた構造となる
効果がある。As in the above embodiment, in a MOS type semiconductor device in which at least the drawing of the protrusion on the surface of the semiconductor substrate is used as a gate region, even in a MOS transistor which requires a long gate length,
The gate part has the effect of creating a structure suitable for high integration without requiring a large area.
前記実施例は単チャネルのＭＯＳトランジスタについて
示したが、ＰチャネルとＮチャネルを半導体基板凸ｗＡ
Ｈ面に形成する相補型ＭＯ８集槓回路にも本構造を適用
できることはいうまでもないAlthough the above embodiments have shown a single channel MOS transistor, the P channel and N channel are connected to the semiconductor substrate convex wA.
It goes without saying that this structure can also be applied to complementary MO8 collector circuits formed on the H-plane.
第１図は従来技術によるＭＯＳ型半導体装置の断面図、
第２図および第３図は本発明によるＭ０Ｓ型半導体装置
を示す断面図である。
１．１１．２１・・・・・・半導体基板１２．２２・・
・・・・凸 部
２．１５．２５・・・・・・ソース拡散領域５．１６，
２６．２６’・・・・・・ドレイン拡散領域５．１３，
２３．２３’・旧・・ゲート絶縁膜ｄ、１４，２４．２
４’・・・・・・ゲート電極４．１７．２７・・・・・
・フィールド絶縁膜以 上
出願人 株式会社趣訪精工舎
代理人 弁理士 最上 務FIG. 1 is a cross-sectional view of a MOS type semiconductor device according to the prior art.
FIGS. 2 and 3 are cross-sectional views showing an M0S type semiconductor device according to the present invention. 1.11.21...Semiconductor substrate 12.22...
... Convex portion 2.15.25 ... Source diffusion region 5.16,
26.26'...Drain diffusion region 5.13,
23.23' Old... Gate insulating film d, 14, 24.2
4'...Gate electrode 4.17.27...
・Field insulation film and above Applicant Shuho Seikosha Co., Ltd. Agent Patent attorney Tsutomu Mogami
Claims (1)
面の凸部の少なくとも側面にはゲート絶縁膜とゲージ電
極とが形成されて成る事を特徴とするＭＯ８１１半導体
装置。An MO811 semiconductor device characterized in that a semiconductor substrate surface is processed into an uneven shape, and a gate insulating film and a gauge electrode are formed on at least side surfaces of the convex portions of the uneven semiconductor surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8036582A JPS58197773A (en) | 1982-05-13 | 1982-05-13 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8036582A JPS58197773A (en) | 1982-05-13 | 1982-05-13 | Mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58197773A true JPS58197773A (en) | 1983-11-17 |
Family
ID=13716229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8036582A Pending JPS58197773A (en) | 1982-05-13 | 1982-05-13 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58197773A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122569A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Semiconductor device |
| JPH02125667A (en) * | 1988-11-04 | 1990-05-14 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2006190985A (en) * | 2004-12-28 | 2006-07-20 | Hynix Semiconductor Inc | Semiconductor device with long channel and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5362985A (en) * | 1976-11-18 | 1978-06-05 | Toshiba Corp | Mis type field effect transistor and its production |
| JPS5775460A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
-
1982
- 1982-05-13 JP JP8036582A patent/JPS58197773A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5362985A (en) * | 1976-11-18 | 1978-06-05 | Toshiba Corp | Mis type field effect transistor and its production |
| JPS5775460A (en) * | 1980-10-28 | 1982-05-12 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02122569A (en) * | 1988-10-31 | 1990-05-10 | Nec Corp | Semiconductor device |
| JPH02125667A (en) * | 1988-11-04 | 1990-05-14 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2006190985A (en) * | 2004-12-28 | 2006-07-20 | Hynix Semiconductor Inc | Semiconductor device with long channel and manufacturing method thereof |
| JP4726612B2 (en) * | 2004-12-28 | 2011-07-20 | 株式会社ハイニックスセミコンダクター | Method for manufacturing a semiconductor device having a long channel length |
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