JPS58195976A - Multiple cpu system - Google Patents

Abstract

PURPOSE:To eliminate trouble in a system, by making plural mutually interruptible CPUs connected to a common bus request to interrupt, and transferring data after specified time, withdrawing the requests to interrupt when the requests to interrupt are generated nearly at the same time. CONSTITUTION:Plural CPUs 10-12 are connected to the common data bus 17. The CPU10 is provided with an interruption request terminal 13, interrupt input terminal 14, and recognition terminals 15 and 16. The CPUs 11 and 12 are also provided with terminals 19-23, and 24-27. Once the CPU10 sends a request- to-interrupt signal from the output terminal 13 when sending data to other CPUs, the CPUs 11 and 12 perform interruption processing to make input-output ports 23 and 28 ready. The CPU10 sends out the data a time T1 later. When there are plural requests to interrupt nearly at the same time, the requests to interrupt are withdrawn within the time T1. In this case, a request to interrupt is made again after a time T1+T2+alpha elapsed from the end of interrupt processing, where alpha is characteristic to each CPU. Thus, trouble in the system is prevented to exclude an overlap of interruptions.

Description

DETAILED DESCRIPTION OF THE INVENTION [@Example Mosquito Field] The present invention relates to a multi-CPU system that includes a plurality of CPUs and is capable of mutually transmitting information.

[Technical background of the invention]

In general, in devices that use microcomputers, due to system or storage capacity constraints, the system is not configured with only one microcomputer (hereinafter referred to as cPU), but with multiple CPUs. Sometimes.

In such a multi-CPU system, it is necessary to operate the 21vA CPUs in close synchronization, and also to operate them while exchanging tic t*@ with each other. may occur.

Conventionally, for this purpose, each CPU is provided with a resonance bus for data transfer, an interrupt signal output terminal, and a signal input terminal.

FIG. 1 is a block diagram showing an example of this conventional multi-CPU system. Figure 2 shows the distance between P and Yard (1) in Figure 1.

(2) is the CPU (IC), (3), +4) are the interrupt request output terminals, (υ), +64 are the recognition += signal input terminals -1+71 Vi data port X, +8.1 +
+97 is the data boat U and l71IJ2, tIJ), tq is the interrupt request output terminal (3) of the CPU (1), data boat (8), recognition signal 4+t
5) shows the output waveform.

To explain the operation, CPU (1) Color L: P U
When transferring information to +z), CPLItl) first transfers the interrupt request output ``-6'' output from terminal (3) to 15
'' and set it to l111 (time type 1 in Figure 2...the interrupt request output time) 1, C)' U 1.4) is the recognition human power level for the end f(6) l' L lθ 1) 111t
Set the port (9) from the high impedance state to the input port designation using the full detection L5. Then, the interrupt request output is changed from the 1-L level to the H- level and output from the terminal (4) to notify the CPU that information can be accepted.
Tell (1). The CPU (1) detects that the recognition input to the terminal (5) changes from the 1-L level to the rHJ level (time type 2) and outputs information to be transferred from the boat (8). Then, the interrupt request output from terminal (3) is [H
Lower from i level to rLJ level (at3). C.P.
tJ12) Detecting that the $1 terminal (6) heno input has changed rLJ L/bevel, the boat (9)) CP t
Read the transfer information from J (]). Then the terminal (
4) lowers the interrupt request output to the 1-L" level and sets the data port (9) to high impedance. C
The PU (1) detects that the input level of the terminal (5) reaches the 1-LJ level (time t4...the time when the data reception of the CPU t21 ends) and confirms that the data is securely V.
Confirm that the signal is transmitted to CCP [J12] and set the data boat (8) to high impedance.

(Time 1s/Data output OFF time) In this way, the information transmission from CPU (1) to CPU (2) is completed.In addition, the information transmission from CPU (12) to CPU (1) is as described above. The operation is the opposite.

[-Problems with Nikui technology]

Information is transmitted between the two CPIJs (ICs) in complete synchronization as described above. However, as the number of CPUs involved in information transmission increases, synchronization becomes difficult. Also, each CPU is synchronized with the one with the slowest waiting time, resulting in a decrease in processing efficiency. Furthermore, there is a drawback that providing a scheduler for controlling sK data transfer outside the CPU makes the configuration complicated.

[Purpose of the invention]

-C is also relatively easy to obtain, such as the same II #8, and is a multi-CP IJ that can reliably send and receive information.
The purpose is to provide the system II.

[Summary of the invention]

The present invention is a multi-CPU system composed of a plurality of CPUs connected to a common data bus. an interrupt request output terminal for issuing an interrupt request to a CPU, an interrupt input terminal for manually inputting an interrupt request from another CPU, and a recognition screen for recognizing the CPU that has requested an interrupt. A control means to which a terminal is connected is provided, and when data transfer is necessary, it outputs an interrupt request output to another CPU, outputs the data to the common data bus after a predetermined period of time after death, and outputs the data to the common data bus, and outputs the interrupt request output to the own CPU. The control means is configured to detect the interrupt from the other CPU within the predetermined time and cancel its own interrupt request output when the interrupt request output from the other CPU is output almost simultaneously. be.

1'I (1) Embodiment] Hereinafter, a multi-CPU system according to the present invention will be described based on the illustrated embodiment.

Figure 8g3 is a block diagram showing an embodiment of the multi-CPU system according to the present invention, and Figure 4 is a block diagram showing the internal configuration of each CP LJ. In FIG. 3, −, an, and ua are CPUs, and CPUGI has an interrupt request output terminal 0, an interrupt input terminal I, and a CPU that requested an interrupt.
Cognitive/dislike terminal 4, αe and CPIJα for understanding PU
A human output port (II) of the common data bus αD is provided to transfer data between .
Similarly, for CPUQI) and CPIJQ2, the interrupt vI request output terminal ([1 and @interrupt input terminal (2) and (to), itm4 child 30. (2) and (to), (2)
A human power boat (to) and (to) are provided. And ePUIQ interrupt request output terminal (13 is CPU0I)
and α are connected to each of the Il&g# terminals QD and (to), and are also connected to the interrupt input terminals (to) and (c) via diodes (2) and -, respectively. . Similarly, CPUQi)O interrupt request output m child Q'J
tf CP U tll ・f13noiigQg子Ql
and ■D, and are also connected to diodes 6υ,
The interrupt request output terminal of CPUn2), which is also connected to the interrupt input terminals 041 and (c) through (to), is CPUul.

Confirmation of Uυ! I! Connected to terminals α and @, and also connected to interrupt input terminals I and (to) via diodes
It is also connected to.

Next, each CPU (II, (1υ, α) will be explained in more detail using FIG. 4. As an example, cPUu*t
*Uploaded, but the internal configuration is CPUQI).

The same applies to 02+. There is a control circuit (4
υ, U, / Dumb access memory () tAM) (transfer), read I/J = memory (ROM) Bi2 is provided, and data transfer and interrupt manual processing are performed using these. 111JI41 means (goods) are constituted. 11. A M (Part of 4a has a counter (c)
, interrupt flag memory (2) is stored.

It has been a long time since one CPU in this system has
Data transfer to 1 4IhWIh - Explain.

The interrupt operation will be explained. What is interrupt operation? L: P
If t: is currently processing A, human input to the interrupt input terminal causes the interrupt processing to start at the end of the processing A, and after performing a series of interrupt processing, This is a transition to the original processing operation.

In this system, for example, CPU +1 (when I tries to send data to another CPU, CP 1.I
An interrupt request signal is output from the interrupt request output terminal 0 of Ql. Then, an interrupt is applied to CPUQ9 and CPUQ0. As a result, the CPU (Iυ and aa) enters interrupt processing operation, and specifies the input/output ports (to) and (to) as human-powered boats.This causes the CPU to enter a standby state for data from CPUQl, and after a predetermined time, data is sent to Wl. When CPU ! enters interrupt operation, g*i child υ occurs.

- detects the ethical level and determines whether the interrupt request is from CPLJQI or CPU Q3.

In the same way, CPUQ3 detects the logic level of the recognition terminal (to) and @ and determines whether the interrupt request is coming from CPUQG or αυ.In this system, synchronization is performed using human power to interrupt the other party. 1, the path an is the human output port (18, (to),
(to), and is normally set to specify a human-powered boat, and is specified as an output port only when transferring data. This data output is performed at time T1m, which is the first predetermined time, after outputting the interrupt request output terminal. Further, at the end of time T2, the data is withdrawn, the input/output boat is designated as a manual boat, and the interrupt request signal is withdrawn. As described above, the CPU on the data receiving side reads the K data after a predetermined time (Tt + 1 hour 11 in this T-rich embodiment) after receiving the interruption. Here, in this embodiment, data ll! The reason why the data is delayed for 9 hours is to ensure that the data is loaded properly. The setting of time T1 and TI will be described later. □ A time chart of the above data transmission is shown in Figure 5. The 51st prisoner, for example, outputs the output from the CPUQ/O interrupt request output terminal 0 in the same figure (8 indicates the output from the human output port X11 of the same CPU (II).

By the way, in this system, there is a case where two or more data buses are overlapped and designated for output on the Nomori common data bus aη, which is an interlayer. In this case, there is a possibility that the human output boat all (219 (to)) will be electrically destroyed. In this system, when an interrupt request is received for rounding to avoid this situation, the first predetermined time T, interrupt requests are canceled and no data is output.At this point, interrupt requests are output from two or more CPUs with a time difference of more than one instruction cycle (approximately 9 μsec or more). Considering the case, it is impossible for the interrupt request outputs to overlap in this case.
This is because U has moved to the step of manual interrupt processing.

Therefore, a problem arises when interrupt requests are output from multiple CPUs at the same time or almost simultaneously (within l instructions).In this case, in this case, the time until data is output is T1, and the interrupt request is output. That's what I do. At this time, by setting the time α (off is the second predetermined time) for each C'PUKzZ to be different, the interrupt request outputs will not overlap again in the case that the interrupt request outputs are canceled in each CPU. 4fisecf) CP
For U, Tl = 300 μsec.

T2 = 3m5ec, α=30~50m5e
Just set it as c. Furthermore, for rounding to increase the margin against noise, it is also possible to send and return the received nine data one more time and process it after confirming the coincidence of the two transmissions and receptions.Increasing the number of matching circuits increases the margin against noise. The degree can be set appropriately.

The flowchart of the above processing operation inside the CPU is shown in the sixth section.
7 and will be described in conjunction with FIG. 4.

FIG. 6 is a flowchart showing the operation within the control means (b) (control circuit -), and this flow includes a data transfer routine. FIG. 7 is a 70-chart when the number of interruptions is 6. Programs # and I (stored in 0M443) shown in these flowcharts are read out and executed by control circuit -0.

When the power is turned on, first the RA is turned on as shown in Figure 6.
M (counter (c) in 43, interrupt flag memory
and other specified registers are initialized (initial settings). Next, CPUul, 01) determines whether data transfer is necessary within Q4.

If data transfer is necessary, move on to the next data transfer routine. If not, go elsewhere J! Execute l and return to the point of determining whether data transfer is necessary.

When moving to the data transfer routine, first 1't A M
The contents of the interrupt flag memory in <43 are checked. That is, it is checked whether the interrupt flag is ON. As explained later in the 70-chart in Figure 7,
When an interrupt request from another CPU is made manually, this interrupt flag is turned ON (that is, the contents of the interrupt flag memory (preparation) are updated).If the interrupt flag is ON, it is set to 1 (A
The value of the counter (c) in M(43) is checked.

In other words, it is determined whether Kara/Ri (Ha) is a friend by measuring the time 'rl+'r2+α7. Unless this counter (Ha) is initialized, its value changes over time. You can know the elapsed time.
If T1+T2+α time has elapsed, turn off the interrupt flag.
and moves on to other processing programs. If the time has not passed, move on to another processing program immediately. Interrupt flag is O
If not N (that is, if no interrupt request has been input from another CPU), outputs a /fi interrupt request. In other words, the control circuit (4+) is connected to the interrupt request output terminal (131 in the case of CPUH) through the other terminal (in the case of DCPUC, tH (11)
, (13) Waits for T times at the 0th time an interrupt is applied. Furthermore, V (it is determined whether the interrupt flag is ON or not. If an interrupt is received from another CPU while outputting an interrupt request, Fj ti
l! If it is turned on as mentioned above, if it is turned on, it will be sent to another processing program, otherwise it will be sent to the data port (C
If it is PUQI, output the data by specifying 0 (0) as the output specification. After waiting for another T, the data boat is designated manually (7) and the interrupt Yasugi is completed.Then, it moves on to other processing programs.

Now, we return to the point of determining whether data transfer requires force or not. Although not shown in the flowchart, a counter (4) is a predetermined time (Tll T2 or TllT2).
+α) After counting the elapsed time, it is initialized.

When an interrupt request is received from another CPU, the process moves to the interrupt manual processing program. That is, as shown in Fig. 7 (C), when entering the interrupt manual processing, the register is first saved. It is to temporarily store it.Next, it is determined whether the interrupt request is currently being output.If it is being output, the interrupt request is canceled, otherwise it is left as is (~
Next, after determining that Tt+'9 time has elapsed by the counter 119, the data is read in. Next, the interrupt flag f is set to ON and the counter is initialized.

Press 1 to move the contents saved in A M +43 by 1% to the boat control circuit (register (not shown) in 4υ) f-. After that, interrupt processing is performed. Pass, 0 Zorog 2
Returning to the system, if two or more CPIJs output interrupt requests almost simultaneously, the other party's interrupt will be detected within T1 time and the interrupt request output will be canceled. All crowds of bus alpha power) Ql, @
, (J is designated as a human-powered boat. Therefore, for example, add a pull-up resistance U from the beginning of forging, set all the bits of the boat to r l J shape, read the code at this time, and find the unarmed code. If this is the case, there will be no problem even if the reading processing routine is used to read the data.
g'-) has been withdrawn (because the interrupt request output has been withdrawn), it is possible to prevent the data from being read.According to the m flowchart mentioned above, the data transfer routine When there is an interrupt request from another CPU, the interrupt flag is turned ON in the interrupt manual processing program, so the data transfer is not completed. In addition, in the flowchart of Fig. 6, if the interrupt flag is ON and the process moves to another process and returns to the judgment of whether data transfer is necessary 4, it is obvious that data transfer is required, so data transfer is not possible. Let's move on to the routine.

By the way, regarding the handling of the data bus a7) in this system, the data bus uses a tri-state input/output port or a human output port in the case of a consumer 4-bit CPU, and is normally designated as a human powered port as mentioned above. It can send and receive data as an output port only when it reads data and issues an interrupt request output. Add a series resistor to the human output boat terminal and
<It is therefore possible to electrically protect the human power boat.

Moreover, even if the number of CPUOs is increased in this/Sudem, the basic functions remain the same, and all that is required is to increase the number of terminals used to identify the CPU at the time of an interrupt. At this time, the number of identification lines also increases. In order to prevent this increase, the steps shown in Figure 8 are as follows:
U (50), (st), (52).

......, (53) interrupt request output # (54)
It is preferable that the code is passed through an encoder (55), encoded, and inputted to each CPU as an identification code through an identification code line (56).

Furthermore, this system accepts interrupts from each CPU by filling the interrupt request terminal with an ORm, and data transfer between CPUs can be easily selected.

Although the number of CPUs is three in the embodiment, it is clear ηλ that the present invention is not limited to this.

After i&, an application example of this system will be briefly described below.

For example, this system can be applied to a video system with a tuner that is compatible with remote control. The aforementioned Ct'1Jflll,
G1), QJ tttL sotL tie-r-JljI
C.

It is sufficient to make it compatible with the frequency synthesizer (P8) IC and the remote control reception IC. If you want to send the desired channel's video to the television receiver, use the FS device connected to the S ICK.
The channel to be received is input to the FS IC, and the FS IC drives the PLL IC, which is also connected to the FS IC, and performs the control. And furthermore for tie 1-■C
The receiving channel is displayed on the display connected to the timer 1c. The channel/channel data transfer at this time is the channel 2-digit information t.
- Divide into 1 digit and transfer (if 12 channels, divide into 1 and 2 separately). This and color data transfer can be done by following the data transfer routine in the flowchart of FIG. Naturally, the timer IC can tell from its recognition terminal that the data is from the FS IC. In addition, when channel data is transmitted from the remote control/transmitter, the remote control receiver IC1 receives the channel data from the light receiving element connected thereto, and further transfers the channel data to the FS IC. At this time, the timer IC can determine by its US terminal that the data is from the remote control receiving IC and ignore the data.

[Effects of the Invention] As described above, according to the multi-CPU system of the present invention, information can be reliably transmitted and received between CPUs with a relatively simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional one multi-CPU system, and Fig. 2 is a time chart of the system shown in Fig. 1. Block diagram shown, #! Figure 4 is the CP of Figure 3.
A block diagram showing the internal configuration of U, FIG. 5 is a time chart of data transmission of the system in FIG.
．． 11,12...CPU. 13. 19.24...Interrupt request output terminal, 14.2
0.25...Interrupt input terminal, 15, 16°21.22
, 26, 27... recognition terminal, 17... common data bus, U... control means. Representative, person Patent attorney Noriyuki Chika (and 1 other person) 10th/su2 z tt12 iJA, ni

Claims (2)

[Claims] (1) In a multi-CPU system consisting of multiple CPUs connected to a common data bus and capable of transmitting information between these CPUs, an interrupt request output terminal for each CPU to issue an interrupt request to other CPUs. , an interrupt input terminal to which an interrupt request output from another CPU is manually inputted, a double terminal for requesting an interrupt and transmitting the nine CPUs, and a control means connected to these terminals, When data transfer is necessary, after outputting an interrupt request output to another CPU, the data is output to the common data bus after a first predetermined time has elapsed, and the interrupt request output of itself and the interrupt from other CPUs are output. If the request output is issued at the same time as the request output, the other CPU
A multi-CPU whose control means is configured to detect an interrupt from the CPU and output its own interrupt request.
system. (2) When interrupt request outputs are issued almost simultaneously from multiple CPLJs and each CPU picks up the interrupt iI$ output,
27th) The control means is configured to issue an interrupt request output for the r-night transfer again for a predetermined time of 1 kpc, and the second predetermined time is made different for each CPU.
fffFClaim 1)) Multi-CPU system. .