JPS5819563A - Detecting circuit for speed - Google Patents

Detecting circuit for speed

Info

Publication number
JPS5819563A
JPS5819563A JP11737881A JP11737881A JPS5819563A JP S5819563 A JPS5819563 A JP S5819563A JP 11737881 A JP11737881 A JP 11737881A JP 11737881 A JP11737881 A JP 11737881A JP S5819563 A JPS5819563 A JP S5819563A
Authority
JP
Japan
Prior art keywords
signal
data
circuit
pulse
counter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11737881A
Other languages
Japanese (ja)
Inventor
Hideaki Hayashi
英昭 林
Shiro Watanabe
四郎 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Columbia Co Ltd
Original Assignee
Nippon Columbia Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Columbia Co Ltd filed Critical Nippon Columbia Co Ltd
Priority to JP11737881A priority Critical patent/JPS5819563A/en
Publication of JPS5819563A publication Critical patent/JPS5819563A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/42Devices characterised by the use of electric or magnetic means
    • G01P3/44Devices characterised by the use of electric or magnetic means for measuring angular speed
    • G01P3/48Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage
    • G01P3/481Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage of pulse signals
    • G01P3/489Digital circuits therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Rotational Drive Of Disk (AREA)
  • Linear Or Angular Velocity Measurement And Their Indicating Devices (AREA)

Abstract

PURPOSE:To obtain a speed signal without providing any special detecting mechanism, by obtaining the speed signal required for rotation or regeneration of a digital audiodisc from a regeneration signal of the disc. CONSTITUTION:A pulse-coded signal (a) from a disc is given to a waveform conversion circuit 3 and thereby a pulse corresponding to a part having inverted polarity is obtained. A counter circuit 4 counts a reference pulse C from a reference signal generating circuit 1 and is reset by an output (b) of the waveform conversion circuit 3, while an up-down counter circuit 5 is loaded with data therefrom. At this time, the part of the input data wherein the interval of inversion of polarity is long is constantly presented as the data of the up-down counter circuit 5 by a comparator 6. Moreover, subtraction is made constantly and gradually in the up-down counter circuit 5 by a signal (f) obtained through frequency division 2 of the reference pulse C, and therefore a load pulse (e) is always generated even with increased revolving speed of the disc. The data of said part is subjected to D/A conversion 8 and thereby a speed signal is obtained.

Description

【発明の詳細な説明】 本発明のディジタルオーデオディスク(以下DJと記す
。)ogi@篭−タO制御に関する0パルスコード化さ
れたデジタル信号を党ヘッド等を用いてディスクに書き
込み、再生を行う、DムD中ビデオディスク等Oディス
ク再生装置に於て社記鎌書度を上げる丸めにディスクの
半径方向で常に相対速度を一定wcw御する記録制御方
法が提案されている0こ〇一定ilt度記鍮によってデ
ータを記−し九ディスクに於ては再生時に?!生位置に
応じて回転速度を変化させる必要がある。仁の為に再生
用の光ヘツド位置を検出し、ディスクの半径に対応し九
回転速度信号を検出して必要な線速としなければならe
−0 この様な検出信号を基に所定のデータを再生し、該デー
タよ)同期信号を取〉出し位相ナーぽをかけていた。こ
の#!な制御方法によると生伍情報をヘッド位置から攻
〉出し、それに対応し大速度信号を必要とする九めK1
1m1が複雑と成るばか〉かドTIJyトなどの原因と
成〉、所定の正し一回転に成)II<、ヘッド位置竜ン
を−の堆付調整も必要となる。更に、記帰時O所定圏転
速度が再生時の回転速度と異なって−る場会に%互換性
で間層を残すことに成る。
DETAILED DESCRIPTION OF THE INVENTION A digital audio disc (hereinafter referred to as DJ) of the present invention writes a 0-pulse coded digital signal related to Ogi@Ko-ta O control to the disc using a party head etc. and plays it back. A recording control method has been proposed in which the relative speed is always controlled at a constant wcw in the radial direction of the disk in order to increase the writing speed in O disk playback devices such as D, D, and video disks. Is it possible to record data using an ilt recorder and play it back on a nine-disk? ! It is necessary to change the rotation speed depending on the raw position. The position of the optical head for reproduction must be detected for the purpose of recording, and the nine rotation speed signals corresponding to the radius of the disc must be detected to obtain the required linear velocity.
-0 Based on such a detection signal, predetermined data is reproduced, a synchronization signal is extracted from the data, and phase napping is applied. this#! According to a control method, raw information is transmitted from the head position, and correspondingly, the ninth K1 requires a high speed signal.
If 1 m1 becomes complicated, it is also necessary to adjust the head position in order to make one correct rotation. Furthermore, if the predetermined rotational speed at the time of recording is different from the rotational speed at the time of reproduction, an intermediate layer is left due to compatibility.

本発明は叙上O弊害を除去するために成され九%のでそ
O目的とすゐとζろは再生信号よ〉DムD等のディスク
O11転、又a*行に必!!亀速度信号を得為ようにし
たものであ〉、一般にパルスー−r化されIN、、信号
線通常、系O伝送帯域の制限などから言値信号O極りI
k夏転岡隔が峙定されてお)、最大反転間隔又は最小反
転間隔はその変調方式で定まっている◇そとで本発明で
は上述の最大又状最小反転間隔部分のみ取〕出して速度
信号とし、その間隔を所定の間隔とするものである。
The present invention was made in order to eliminate the above-mentioned disadvantages, and its purpose is to use the playback signals for discs such as D, D, etc., and also for the a* line. ! This is a signal that is designed to generate a speed signal, and is generally converted into a pulse signal.
The maximum reversal interval or the minimum reversal interval is determined by the modulation method.In the present invention, only the above-mentioned maximum or minimum reversal interval is taken out to determine the speed. The signals are set at predetermined intervals.

以下、本発明の1実施例を第1図及び第2図について詳
記する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

第1図は本発明の波形説明図、第2図れ本発明の系統図
を示すもので、第2図に於て、入力端子TIKはディス
ク等からの入力信号aが加えられる。
FIG. 1 is a waveform explanatory diagram of the present invention, and FIG. 2 is a system diagram of the present invention. In FIG. 2, an input signal a from a disk or the like is applied to the input terminal TIK.

数人力信号は第1図aに示す様にパルス間隔i種′々に
混っている0この場合はMFMで;−デッドされた波形
を示す■入力信号aは波形変換回路3に加えられて、極
性反転部分に対応したgi図すの如きパルスを得る。
As shown in Fig. 1a, the input signal a is mixed with various pulse intervals i. In this case, it is an MFM; , a pulse as shown in the gi diagram is obtained corresponding to the polarity inversion portion.

上記、波形変換回路3は微分回路で構成出来る。The waveform conversion circuit 3 mentioned above can be constructed from a differentiating circuit.

該波形変換回路3の出力はカウンタ回路4に加えられる
。該カウンタ回路4には水晶発振器等の基準信号発生回
路1よシの第1図Cに示す如き基準パルスが与えられて
いるので波形変換回路4のリセットパルスとして基準パ
ルスをカウントアツプする。カウンタ回路4は次のパル
スbが来るとアップダウンカウンタ回路5に上記カウン
タデータを四−ドし、カウンタ回路4をリセットする0
更に、パルスbはアンド回路70一方の入力に加えられ
、コンパレータ(6)よシO第1図d図示の出力パルス
dが他方の入力端子に加えられ、アップダウンカウンタ
回路5は第1図・に示す如くp−ドパルス・によってゲ
ートされる。
The output of the waveform conversion circuit 3 is applied to a counter circuit 4. Since the counter circuit 4 is supplied with a reference pulse as shown in FIG. When the next pulse b arrives, the counter circuit 4 loads the above counter data to the up/down counter circuit 5 and resets the counter circuit 4.
Furthermore, the pulse b is applied to one input of the AND circuit 70, the output pulse d shown in FIG. It is gated by a p-do pulse as shown in FIG.

上記コンパレータ6はカウンタ回路4の出力とアツプダ
をンカウンタ回路sの出力が入力され、カウンタ回路4
のデータがアップダウンカウンタ回路5のデータよ〉大
きい時のみ出力パルスdを出力するので該出力パルス4
がアンド回路7に加えられ走時カウンタ回路4のデータ
辻アツプダクンカクンタ回路5に移動することに成る。
The comparator 6 inputs the output of the counter circuit 4 and the output of the counter circuit s.
Since the output pulse d is output only when the data of the up/down counter circuit 5 is greater than the data of the up/down counter circuit 5, the output pulse 4
is added to the AND circuit 7 and the data of the running time counter circuit 4 is transferred to the up-down circuit 5.

依ってアップダウンカウンタ回路5のデータは常に入力
データの極性反転間隔が長い部分のデータのみが表れる
。次に基準信号発生回路1のクリックCを分周回路2で
分周し、パルスbo数倍の周期になる様に設定し九第1
図10信号でアップダウンカウンタ回路5の減算入力と
する。
Therefore, the data of the up/down counter circuit 5 always shows only the data of the part where the polarity inversion interval of the input data is long. Next, the frequency of the click C of the reference signal generation circuit 1 is divided by the frequency dividing circuit 2, and the period is set to be the number of pulses BO.
The signal shown in FIG. 10 is used as the subtraction input of the up/down counter circuit 5.

今、例えばディスクの回転数が増大し、パルス間隔が徐
々に全体的に小さくなってきても、アップダウンカウン
タ回路sH常に少しづつ減算されているために四−ドパ
ルス・が発生しなくなるととはない。
Now, for example, even if the number of revolutions of the disk increases and the pulse interval gradually decreases overall, the up/down counter circuit sH is always subtracting little by little, so no quad pulses will occur. do not have.

通常、入力信号が一定速度の巻金Kti出力のデータは
最小1ビツトOみ変化す為ことになる0もし、急に加速
しパルス間隔が急く狭くなると一定の傾きでカウントダ
ウンされ、徐々に正しい値を示す、この時の時定数社周
波数fで定まる〇ヒのように種々の間隔を持つパルスよ
〉常に特定のパルス間隔を検出する。例えば、MFMで
は101に対応し良嗣のパルスOみの間隔に対応したデ
ーターを得る0このデーターをデジタルーアナリダ変換
回路8でアナーダ変換して七−夕等の制御出力として出
力端子〒8に出力する。
Normally, when the input signal is at a constant speed, the data of the output of the winding Kti changes by a minimum of 1 bit, so if the pulse interval suddenly narrows due to sudden acceleration, the countdown will be performed at a constant slope, and the value will gradually become correct. A specific pulse interval is always detected, such as pulses having various intervals such as 〇〇, which is determined by the time constant frequency f at this time. For example, in the MFM, data corresponding to 101 and the interval between Yoshitsugu's pulses is obtained.0 This data is converted to analog data by the digital-to-analyzer conversion circuit 8, and sent to the output terminal 8 as a control output for Tanabata etc. Output.

上記実施例ではデータの最大間隔を出力するようにし九
がコンパレータ6を逆にカラyり回路4のデータか′ア
ップダウンカウンタ回路5のデータよシ小さい時に出力
パルスdを出すようにし、fの信号をアップダウンカウ
ンタ回路5のアップ(加算)信号とすれば最小間隔を取
〉出すことが出来る。入力信号はMFMで説明したが他
のコーデング方式、例えば3PMやダルーグ;−ド方式
を用いることが出来る〇 本発明は上述0様に構成させたので検出々力によってモ
ータを制御し、所定の回転にすればデータを正しくよみ
とシ、これによって位相ナーポ等を加えれば完全なサー
ボルーズを作ることが出来る。更に特別の検出機構を設
けることなくデータ内容から速度制御信号が得られる特
徴を有するものである・
In the above embodiment, the maximum interval of data is output, and the comparator 6 is reversely colored so that the output pulse d is output when the data of the circuit 4 is smaller than the data of the up/down counter circuit 5. If the signal is the up (addition) signal of the up/down counter circuit 5, the minimum interval can be obtained. Although the input signal was explained using MFM, other coding methods such as 3PM and DARGUARD method can be used. Since the present invention is configured in the above-mentioned manner, the motor is controlled by the detected force and the predetermined rotation is achieved. If you do this, you can read the data correctly, and by adding phase rotation etc., you can create a complete servo loose. Furthermore, it has the feature that a speed control signal can be obtained from the data content without providing a special detection mechanism.

【図面の簡単な説明】 311図は本発明の速度検出回路O波形I!明図、第2
図は本発明の速度検出回路の1実施例である。 図中、1は基準信号発生回路、2は分j1回路、3杜波
形変換回路、4はカウンタ回路、墨はアップダウンカウ
ンタ回路、6はプンバレータ囮路、7はアンド回路、8
aデジタル−アナ臣グ変換闘路である。 特 許 出原人    日本:xOムビア株式会社代理
人 弁理士   山 口 和 美 第1図 を 第2肉
[Brief Description of the Drawings] Figure 311 shows the O waveform I! of the speed detection circuit of the present invention. Mingzu, 2nd
The figure shows one embodiment of the speed detection circuit of the present invention. In the figure, 1 is a reference signal generation circuit, 2 is a division j1 circuit, 3 is a waveform conversion circuit, 4 is a counter circuit, black is an up/down counter circuit, 6 is a pumbareta decoy circuit, 7 is an AND circuit, and 8
It is a battleground for digital-to-analog conversion. Patent Originator Japan: xO Mbia Co., Ltd. Agent Patent Attorney Kazumi Yamaguchi Figure 1 is the second figure

Claims (1)

【特許請求の範囲】[Claims] 記銀厳体に/CCススード化したデータを記録し、該デ
ータの最大反転間隔又は最小反転間隔に対応した信号を
取〉出す手段と、該最大反転間隔又は最小反転間隔に対
応した信号によって諌記鎌諜体の再生速度信号を制御す
る手段とよ〕成る速度検出回路◇
A means for recording data that has been strictly converted into /CC mode, and outputting a signal corresponding to the maximum reversal interval or minimum reversal interval of the data; A speed detection circuit consisting of a means for controlling the reproduction speed signal of the kikama intelligence body◇
JP11737881A 1981-07-27 1981-07-27 Detecting circuit for speed Pending JPS5819563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11737881A JPS5819563A (en) 1981-07-27 1981-07-27 Detecting circuit for speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11737881A JPS5819563A (en) 1981-07-27 1981-07-27 Detecting circuit for speed

Publications (1)

Publication Number Publication Date
JPS5819563A true JPS5819563A (en) 1983-02-04

Family

ID=14710162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11737881A Pending JPS5819563A (en) 1981-07-27 1981-07-27 Detecting circuit for speed

Country Status (1)

Country Link
JP (1) JPS5819563A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758269A (en) * 1980-09-24 1982-04-07 Sony Corp Device for reproducing disk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758269A (en) * 1980-09-24 1982-04-07 Sony Corp Device for reproducing disk

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